JP4299850B2 - Counter circuit device - Google Patents

Description

  The present invention relates to a technique which is applied to, for example, the field of measurement and counts pulse signals whose frequency changes with time at regular intervals.

  Conventionally, as a method for increasing the maximum count value of the counter circuit, for example, as shown in a textbook such as Non-Patent Document 1, a toggle type flip-flop (hereinafter referred to as TFF) connected in cascade is used. A method for increasing the number is known. Similarly, the one shown in FIG. 8 is disclosed in Patent Document 1. This circuit obtains a 4-digit count value, and one digit is composed of a shift register 1 and an encoder 5 that encodes the shift state of the shift register 1 into, for example, a binary value. This configuration is connected in four stages in cascade to form a four-digit counter circuit. In the case of increasing the count value, the number of flip-flops (hereinafter abbreviated as FF) constituting the shift register is increased, or a change is made to increase the pair of the shift register 1 and the encoder 5 in units of groups.

By the way, when configuring various devices, a counter circuit alone does not hold. Usually, in addition to the counter circuit, a display circuit that displays the value and a conversion circuit that converts the value together form a device. To do. The configuration is performed either in a case where all are configured by hardware, or in a case where a microcontroller including a ROM, a RAM, and a CPU is configured by so-called firmware in which the operation of the hardware is controlled by software. This conventional firmware, for example, performs processing to convert a count value obtained by counting physical quantities from a temperature sensor or pressure sensor into numerical values that can be seen by humans, such as temperature and pressure. When increasing the number, the hardware was changed to increase the count value.
“Digital Electronic Circuits in the Age of Integrated Circuits”, pages 130-138, written by Nobuo Fujii, Shosodo Co., Ltd. JP 2002-204157 A (FIG. 1)

As described above, when dealing with a specification change that increases the count value, taking measures to increase the hardware causes problems such as a long time for the specification change and an increase in cost.
The present invention has been made in view of these points, and an object of the present invention is to provide a counter circuit that can easily increase the count value without increasing hardware.

  The counter circuit according to the present invention includes an nbit hardware counter that counts an output signal of a pulse train generating means for generating a pulse signal in which a physical quantity whose value continuously changes is converted into a pulse frequency signal at a predetermined time interval, And firmware that reads the count result at a constant interval that is equal to or greater than the predetermined time interval. The firmware stores the previous count value in the previous count value storage unit, and stores the current count value in the current count value storage unit. An overflow determination means determines whether the nbit hardware counter has a carry or a carry from the value obtained by subtracting the previous count value from the current count value. The number of carry is determined based on the determination result, and the count value generation means calculates the count value from the current count value and the value of the overflow determination means.

As described above, according to the counter circuit of the present invention, it is possible to cope with an increase in count value without increasing the scale of hardware. The n-bit hardware counter remains fixed, allowing counting of 2 ⁿ or more.

  Embodiments of the present invention will be described below with reference to the drawings. Corresponding parts are designated by the same reference numerals in the drawings, and description thereof will not be repeated.

  FIG. 1 is a functional configuration block diagram showing Embodiment 1 of the present invention. The counter circuit 20 includes an n-bit hardware counter 12 and firmware 140 including a ROM, a RAM, and a CPU (not shown) that controls the hardware counter 12. The hardware counter 12 is controlled by software stored in the ROM and RAM, and operates as the counter circuit 20. The pulse train generation means 16 converts an output signal of an optical fiber gyro (not shown) that detects an angular velocity into a pulse frequency signal f using, for example, a VCO (Voltage Control Oscillator) or the like and outputs the pulse frequency signal f to the n-bit hardware counter 12. The hardware counter 12 counts the pulse frequency signal f (Hz) output from the pulse train generator 16 at a predetermined interval. In the first embodiment, the number of bits of the n-bit hardware counter 12 is, for example, 10 bits.

  The count value of the hardware counter 12 counted at a predetermined interval is sequentially read into the current count value storage unit 141 and the previous count value storage unit 142 that constitute a part of the firmware 140. Each time this reading is performed, the subtraction unit 144 of the overflow determination unit 143 subtracts the count value stored in the previous count value storage unit 142 from the count value stored in the current count value storage unit 141. From the subtraction result, it is determined whether the hardware counter 12 has a carry or a carry, and the number of overflows is determined based on the determination result. When the number of overflows is determined, the count value generation unit 146 calculates a count value as the counter circuit 20 from the count value of the current count value storage unit 141 and the overflow number of the overflow determination unit 143.

  In the case of the first embodiment, the time width in which the hardware counter 12 counts the pulse frequency signal f output from the pulse train generating means 16 is the period of the reset signal 14r that resets the hardware counter 12 generated by the hardware counter control means 147. It is decided by. That is, for example, if the period of the reset signal 14r is 1 ms, the pulse frequency signal f is counted by the hardware counter 12 for 1 ms. The count value is: count value = pulse frequency signal f (Hz) × 1 ms. If the frequency of the pulse frequency signal f determined based on the magnitude of the angular velocity is 1 MHz, for example, the count value of the hardware counter 12 at that time is 1000.

  As described above, the hardware counter control unit 147 sequentially reads the count value of the hardware counter 12 immediately before resetting the hardware counter 12 into the current count value storage unit 141, and the count value in the current count value storage unit 141 until then is read. Is read in the previous count value storage unit 142 in advance, and the pulse frequency signal f output from the pulse train generating means 16 can be digitized.

  Next, the operation flow of the firmware 140 is shown in FIG. 2, and the operation of the first embodiment of the present invention will be described in more detail. The operation flow shows an interrupt operation flow in which a CPU (not shown) constituting the firmware 140 operates. When the CPU is interrupted, the count value Cn of the hardware counter 12 is read into the current count value storage unit 141 (step S200). When the count value Cn is read into the current count value storage unit 141, the hardware counter control unit 147 resets the hardware counter 12 (step S201). In step S202, it is determined whether or not the current count value Cn is the first data. If Cn is the first data, the value Cn-1 of the previous count value storage unit is set to Cn in step 203, and the overflow data An overflow counter (hereinafter abbreviated as OFC) for counting the number of times is reset (step S204), and a count value is calculated in step S205. Step S205 is the count value generation means 146. Since it is the first data now, the count value Cn stored in the current count value storage unit 141 becomes the count value. Then, the CPU is stopped (halted) until the processing is terminated and the next interrupt is generated.

Although omitted in this operation flow, the count value of the counter circuit 20 calculated in step S205 is the angular velocity data detected by the optical fiber gyro, and therefore, for example, the CPU halts the calculation shown in Expression (1). Go ahead and convert the count value to angular velocity Y (° / sec).
Y = (count value × F × Ω) / 3600 formula (1)
F is a frequency at which the hardware counter 12 takes in the pulse frequency signal f output from the pulse train generating means 16, and is 1000 Hz in this example. Ω is the pulse weight (second angle, arcsec) of the optical fiber gyroscope, and is a value such as 5 arcsec, which means the minimum angular velocity that can be detected by the optical fiber gyroscope, and is a specific value determined by the performance of the gyroscope. 3600 is a constant for converting the second angle to °.

When there is a next interrupt, the count value Cn of the hardware counter 12 is read into the current count value storage unit 141 again. Since this time is the second count value Cn, the previous count value Cn-1 is subtracted from the current count value Cn by the subtracting means 144 of the overflow determining means 143 (step S206). In preparation for the next interrupt, the current count value Cn is stored (stored) in the previous count value Cn-1 (step S207). Then, the comparison means 145a of the overflow calculation means 145 constituting the overflow determination means 143 determines whether the subtraction result Dn is positive or negative in step S208. If subtraction result Dn is negative, comparator 145a compares its Dn, threshold X _th 145b and the absolute value is equal polarity and a negative threshold value -X _th 145d (step S209) (hereinafter, threshold value X _th The reference numerals 145b and 145d are omitted because they can be discriminated without any particular description).

If subtraction result Dn is negative, if Dn is smaller than the negative threshold -X _th, the OFC145c in the overflow calculation unit 145 to +1 (step S210) through the root alpha. If subtraction result Dn is positive, by comparing the Dn and X _th at step S211, Dn is a to -1 OFC145c if larger than X _th (step S212) through the root gamma. When Dn other than the above is larger than −X _th , the route β is passed, and when Dn is smaller than X _{th, the} route δ is passed. In these routes γ and δ, the count of the OFC 145c is not changed and the process proceeds to the count value calculation (step S205). The CPU halts until the next interrupt is present. Thereafter, the counter circuit 20 operates by repeating the above operation every time there is an interrupt.

[Explanation of threshold value X _th ]
How to determine the threshold X _th shown in equation (2). The lower limit threshold value X _th is the current count value Cn and the previous count value Cn-1 which corresponds to the measuring range of the measuring counter circuit 20 of the present invention is applied, a value larger than the absolute value of the maximum value of the difference Set to. The upper limit threshold value X _th is set to 2 ⁿ / 2 or less determined by the bit number n of the hardware counter.
(Current count value Cn−previous count value Cn−1) <X _th ≦ 2 ⁿ / 2 Formula (2)
Corresponding to the measurement range for the lower limit is, for example, when the counter circuit 20 of the present invention is applied to an angular velocity meter, and the measurement range of the angular velocity meter is, for example, a specification that does not measure a change in angular velocity of 500 ° / second or more. This means that the threshold value X _th is set to the count value corresponding to 500 ° / second. When the count value corresponding to 500 ° / second is calculated backwards by assuming that F in the formula (1) for converting the above count value into the angular velocity Y is 1000 Hz and the pulse weight Ω is 5 arcsec, 360 is calculated. Therefore, it is necessary to set the lower limit value of the threshold value X _{th to} a value of 361 or more which is larger than that.

[Verification of lower limit value of threshold value X _th ]
The range of the threshold value X _th shown in Expression (2) is verified. First, the threshold value X _th = 361 is verified from the lower limit value. FIG. 3A shows the operation of the hardware counter 12. In FIG. 3A, the horizontal axis represents the number of pulses generated by the pulse train generating means 16, and the vertical axis represents the count value of the hardware counter 12 that counts the number. When the hardware counter 12 is 10 bits, for example, the count value changes in the range of 0 to 1023 and operates as a counter that overflows at 1024.
On the premise of the hardware counter 12 operating in this way, the operation status of the overflow calculation means 145 when the previous count value Cn-1 (◯ mark) = 1023 and the current count value Cn (● mark) is changed in the decreasing direction. Is shown in FIG.

The state (a) shown in FIG. 3B is a case where the OFC 145c in which no carry-down is not changed does not change. The state (A) is when the current count value Cn = 663, and Dn = current count value−previous count value = −360 (663-1023 = −360). If Dn is negative, Dn ≦ −X _th is determined to be No (−360 ≦ −361 → No in step S209) in step S209 of the overflow calculation means 145 shown in FIG. The process proceeds to calculation S205. Therefore, the OFC 145c does not change.

In the state (A) shown in FIG. 3B, the count value changes from 1023 to 662. As in the state (a), the hardware counter 12 has no carry or carry. In the state (A), the count value change Dn is set to 361 and an originally impossible value equal to or greater than the threshold value X _th = 361 for the convenience of explaining the erroneous count. At this time, Dn = current count value−previous count value = −361 (662-1023 = −361). In this case, as described above, there is essentially no change in the OFC 145c. However, in step S209 of the overflow calculation means 145 shown in FIG. 2, it is determined that Dn ≦ −X _th is Yes (−361 ≦ −361 → Yes in step S209), and the OFC 145c is incremented by 1 through the route α. . That is, the correct count value is 662, whereas the count value calculated in the count value calculation (step S205) is 1686.

As described above, when Dn changes by more than the threshold value X _th, an erroneous count occurs. Therefore, the lower limit of the threshold value X _th is larger than the absolute value of the maximum value of the difference between the current count value Cn and the previous count value Cn−1. Must be set to

[Verification of upper limit value of threshold value X _th ]
Next, the upper limit value is verified with the threshold value X _th = 512. The state (c) shown in FIG. 3C is a case where the count value of the OFC 145c does not change. The state (c) is the case where the previous count value Cn−1 = 1023 and the current count value Cn = 512, and Dn = current count value−previous count value = −511 (512-1023 = −511). If Dn is negative, Dn ≦ −X _th is determined to be No (−511 ≦ −512 → No in step S209) in step S209 of the overflow calculation means 145 shown in FIG. The process proceeds to calculation S205. Therefore, the OFC 145c does not change.

The state (d) shown in FIG. 3C is a state in which neither a carry nor a carry occurs in the hardware counter 12 whose count value changes from 1023 to 511. In the state (d), the count value change Dn is set to 512 and a threshold X _th = 512 or more, which is not possible, for the convenience of explaining the erroneous count. At this time, Dn = current count value−previous count value = −512 (512-1023 = −512). In this case, as described above, there is essentially no change in the OFC 145c. However, in step S209 of the overflow calculation means 145 shown in FIG. 2, it is determined that Dn ≦ −X _th is Yes (−512 ≦ −512 → Yes in step S209), and the OFC 145c is incremented by 1 through the route α. . As a result, the correct count value is 511, whereas the count value calculated in the count value calculation (step S205) is 1535.

Thus, the upper limit of the threshold X _th needs to be set to 2 ⁿ / 2 or less determined by the bit number n of the hardware counter. Therefore, the maximum value of Dn and 360, if the bit number of the hardware counter 12 and 10bit, threshold X _th may be set to a value in the range of 361-512. Although the occurrence of erroneous count has been described in the decreasing direction of the count value, the same is true in the increasing direction. The explanation of the increasing direction will be explained in the following examples of count values, and the explanation here is omitted.
Here, the threshold operation X _th = 361, the number of bits of the hardware counter 12 is 10 bits, and a specific example of the change of the count value is shown to explain the counting operation of the present invention.

[Count value example]
Examples of count values are shown in FIGS. In the figure, the horizontal axis represents the number of overflows of the hardware counter 12, the left vertical axis represents the count value, and the right vertical axis represents the angular velocity (° / second) obtained by converting the count value by the equation (1). As for the count value on the vertical axis, the count value from 0 to 1023 is indicated by a solid line, and the count value higher than that is indicated by a broken line. See also FIG. 2 of the operation flow in the following description.

[Previous number of pulses 1023 → Current number of pulses 1383]
4, the previous number of pulses (◇ mark, since the number of pulses and the count value match omitted ○ mark of the previous count value) in 1023, this number of pulses (◆ symbol) is the threshold value X _th marginal 1383 The change in the count value when the number of pulses increases is shown. In this case, the count value changes from the previous count value Cn-1 (o mark omitted) 1023 to the current count value Cn (● mark) 359 (1383-1024 = 359). Since the value Dn obtained by subtracting the previous count value Cn-1 (◯ mark) from the current count value Cn (● mark) is negative of −664 (359-1023 = −664), Dn ≦ −X _th is Yes ( −664 ≦ −361 → Yes in step S209, and OFC 145c is incremented by 1 (step S210). Through the route α in FIG. 2, the count value calculation in step S205 is 1024 × 1 + 359 = 1383, which is the same value as the current pulse number (♦ mark).

[Previous pulse number 1383 → Current pulse number 1023]
FIG. 5 shows a change in the reverse direction, the previous pulse number (◇ mark) is 1383, and the current pulse number (♦ mark, the number of pulses and the count value are the same, so the current count value is omitted) is 1023. It shows the change in the count value when a number of pulses decreases in the X _th last minute. In this case, the count value changes from the previous count value Cn-1 (◯ mark) 359 (1383-1024 = 359) to the current count value Cn (o mark omitted) 1023. The value Dn obtained by subtracting the previous count value Cn-1 (circle mark) from the current count value Cn (circle mark omitted) is 664 (1023-359 = 664), and Dn ≦ X _th is No (664 ≦ 361 → step) NO is determined in S211 and the OFC 145c is counted by -1 (Step S212). Through the route γ of FIG. 2, the count value calculation in step S205 is 1024 × 0 + 1023 = 1023, which is the same value as the current pulse number (♦ mark).

[Previous pulse number 1324 → Current pulse number 1524 example]
FIG. 6 shows a case where the previous pulse number (（mark) is 1324 and the current pulse number (♦ mark) is 1524. In this case, when the OFC 145c is 1, the previous count value Cn-1 (◯ mark) is 300 (1324-1024 = 300), and the current count value Cn (● mark) is 500 (1524-1024 = 500). . At this time, since Dn is 200 (500−200 = 300) and positive, and Dn ≦ X _th is Yes (200 ≦ 361 → Yes), the process proceeds to the count value calculation (step S205) via the route δ. The calculated value of the count at this time is 1024 × 1 + 500 = 1524, which is the same value as the current pulse number (♦ mark).

[Previous pulse number 1900 → Current pulse number 2148]
FIG. 7 shows a case where the previous pulse number (（mark) is 1900 and the current pulse number (♦ mark) is 2148. In this case, the OFC 145c is 1, the previous count value Cn-1 (◯ mark) is 876 (1900-1024 = 876), and the current count value Cn (● mark) is 100 (2148-2048 = 100). At this time, Dn is negative of −776 (100−876 = −776) and Dn ≦ −X _th is also Yes (−776 ≦ −361 → Yes), so that OFC 145c is incremented by 1 through the route α (step S210). ) The value of OFC 145c is 2, and the process proceeds to count value calculation (step S205). The count value calculation is 1024 × 2 + 100 = 2148, which is the same value as the current pulse number (♦ mark).

  As described above, the overflow determination unit 143 determines whether or not the nbit hardware counter 12 has overflowed from the value obtained by subtracting the previous count value from the current count value, and determines the number of overflows based on the determination result. The count value generation unit 146 calculates the count value from the current count value and the value of the overflow determination unit, so that it is possible to count more than the count number determined by the number of bits of the hardware counter 12.

  In the description of the embodiment, the optical gyro for detecting the angular velocity has been described as an example. However, the present invention can be applied to a counter circuit for detecting other physical quantities, for example, acceleration. In addition, the counter circuit according to the present invention can be applied to detection of temperature and luminance which are other physical quantities.

The figure which shows the function structure block of Example 1 of this invention. The figure which shows the example of the operation | movement flow of the firmware. 3A is a diagram showing the operation of the hardware counter 12, and FIG. 3B is a diagram showing the operation status of the overflow calculation means 145 when the current count value Cn is changed in the decreasing direction with the threshold value X _th = 361. is a diagram showing an operation status of the overflow calculation means 145 in the case where the current count value Cn is varied in the decreasing direction in FIG. 3 (c) threshold X _th = 512. The figure which shows the example of a count value in case this count value Cn (-mark) is 359 and last count value Cn-1 (circle mark) is 1023. The figure which shows the example of a count value in case this count value Cn (-mark) is 1023 and last count value Cn-1 ((circle) mark) is 359. FIG. The figure which shows the example of a count value in case OFC145c is 1 and this time count value Cn (-mark) is 500 and last count value Cn-1 (circle mark) is 300. FIG. The figure which shows the example of a count value when OFC145c is 1 and this time count value Cn (-mark) is 100 and the last count value Cn-1 (circle mark) is 876. FIG. 6 is a diagram showing a counter circuit disclosed in Patent Document 1.

Claims (1)

Pulse train generating means for converting a physical quantity into a pulse frequency signal;
An n-bit hardware counter that counts the pulse frequency signal output from the pulse train generating means at a predetermined time interval, where n is an integer of 2 or more;
The count value of the hardware counter and a counter circuit including a firmware to read at regular intervals over the predetermined time interval,
The above firmware
A previous count value storage unit for storing the previous count value of the hardware counter;
A current count value storage unit for storing the current count value of the hardware counter;
Based on a value obtained by subtracting the previous count value from the current count value, it is determined whether or not the hardware counter carries or carries a carry, and the determination result determines the number of times the hardware counter carries the current pulse frequency signal. Overflow determination means;
Comprising the count value generating means for calculating a count value from the value of the current count value and the overflow determination means,
Upper Symbol overflow determination means includes means for subtracting a previous count value from the count value currently,
A comparison means for comparing with a negative threshold value −X _th if the subtraction result is negative, and comparing with a positive threshold value X _th if the subtraction result is positive;
Negative subtraction result overflow counter is incremented if smaller than the negative threshold -X _th, and a overflow calculation means for -1 overflow counter if positive subtraction result is larger than the positive threshold value X _th And
Upper Symbol threshold X _th, the upper limit is at 2 ⁿ / 2 or less, the lower limit corresponds to the measuring range - it is set to a value larger than the absolute value of the maximum value of (current count value the previous count value) A characteristic counter circuit device .

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