JP2016181118A - Pulse counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To count the number of pulses up to a value exceeding the upper-limit value of a count unit.SOLUTION: A pulse counter 100 comprises a counter 1 in which an upper-limit count value Cmax is set, and which is configured so as to count the number of pulses from 0 again when having counted the number of pulses up to the upper-limit count value Cmax; and an arithmetic unit 4 for integrating the count values of the counter 1 and calculating the integrated value of pulses. The arithmetic unit 4 integrates the count values and calculates a first integrated value X1, integrates the integrated value X1 from 0 again when the first integrated value X1 reaches the upper-limit count value Cmax, and calculates a second integrated value X2 as the integrated value of pulses on the basis of an overflow count n, which is the number of times the first integrated value X1 has reached the upper-limit count value Cmax, and the first integrated value X1.SELECTED DRAWING: Figure 4

Description

  The technique disclosed herein relates to a pulse counter.

  Conventionally, pulse counters that count the number of pulses are known.

  For example, Patent Document 1 discloses a pulse counter that counts the number of pulses output from an external device.

JP 2007-17374 A

  Such a pulse counter has, for example, a counting unit composed of an IC or the like. The counting unit has an upper limit value that can be counted, and as a result, the pulse counter cannot count the number of pulses to a value larger than the upper limit value.

  The technique disclosed here has been made in view of such a point, and an object thereof is to count the number of pulses to a value exceeding the upper limit value of the counting unit.

  The pulse counter disclosed herein is configured such that when an upper limit count value is set and the number of pulses is counted up to the upper limit count value, a counting unit configured to count the pulse number from 0 again, and the counting unit A calculation unit that integrates the count value to calculate the integrated value of the pulse, the calculation unit calculates the first integrated value by integrating the count value, and the first integrated value is set to the upper limit count value. When it reaches, the first integrated value is integrated again from 0, and the integrated value of the pulse is calculated based on the overflow count that is the number of times the first integrated value reaches the upper limit count value and the first integrated value. The second integrated value is calculated.

  According to the pulse counter, the number of pulses can be counted up to a value exceeding the upper limit value of the counting unit.

FIG. 1 is a block diagram of a pulse counter. FIG. 2 is a diagram illustrating an example of changes in the count value and the integrated value when an internal reset occurs during battery driving. FIG. 3 is a diagram illustrating an example of changes in the count value and the integrated value when the power is turned off / on in battery driving. FIG. 4 is a diagram illustrating an example of changes in the count value and the integrated value in the external power supply driving. FIG. 5 is a block diagram of the node device. FIG. 6 is a schematic diagram of a network system.

  Hereinafter, exemplary embodiments will be described in detail with reference to the drawings.

Embodiment 1
Hereinafter, the pulse counter 100 according to the first embodiment will be described. FIG. 1 is a block diagram of a pulse counter 100.

  The pulse counter 100 is connected to a measuring instrument such as a wattmeter. The measuring instrument is configured to output a pulse corresponding to the measurement result. When the measuring instrument is a wattmeter, for example, the wattmeter outputs one pulse every 10 Wh. The pulse counter 100 includes a counter 1 that counts pulses, a power source 2 that supplies power to each part of the pulse counter 100, a memory 3 that stores various data, and an arithmetic unit 4 that calculates an integrated value of the number of pulses. Is provided.

  The counter 1 counts the number of input pulses. The number of pulses counted by the counter 1 is referred to as “count value”. The counter 1 counts from 0 again when the upper limit count value (upper limit value that can be counted) Cmax is set and the count value C reaches the upper limit count value Cmax. For example, the upper limit count value Cmax is 28 bits, and the counter 1 can count up to 28 bits. The counter 1 continues to count the number of input pulses, and outputs the count value at that time in response to a request from the calculation unit 4. The counter 1 is, for example, a CPLD (Complex Programmable Logic Device). The counter 1 is an example of a counting unit.

  Hereinafter, counting from 0 when the count value C reaches the upper limit count value Cmax is referred to as “overflow”.

  The power source 2 is configured to be able to switch between battery driving and external power driving. That is, when a battery is set in the power source 2, battery driving is performed, whereas when an external power source is connected to the power source 2, external power driving is performed.

  The memory 3 stores various data. The memory 3 is a semiconductor memory such as a FLASH memory, for example.

  The calculation unit 4 integrates the count value C of the counter 1 that can count up to 28 bits, calculates an integrated value of the number of bits exceeding 28 bits, and outputs the calculated value. For example, the calculation unit 4 is configured to integrate up to 32 bits. Hereinafter, a calculation method of the calculation unit 4 will be described.

  Although the count value C of the counter 1 will be described in detail later, there is a case where the count value C of the counter 1 is reset in the middle when the power is turned off. Will be accumulated. The first integrated value X1 is set to the same upper limit count value Cmax as that of the counter 1. When the first integrated value X1 reaches the upper limit count value Cmax, the first integrated value X1 becomes 0, and the integration is restarted from 0. The The calculation unit 4 counts the number of times that the first integrated value X1 has reached the upper limit count value Cmax as the overflow count n. Hereinafter, when the count value C or the first integrated value X1 reaches the upper limit count value Cmax and the value returns to 0 is referred to as “overflow”.

  Then, the final second integrated value X2 is expressed by the following formula (1) using the first integrated value X1.

  X2 = X1 + Cmax × n (1)

  Moreover, the calculating part 4 calculates the 1st integration value X1 by the following formula | equation (2).

  X1 = C−C ′ + X1 ′ (2)

  Here, C is the count value of the counter 1 at the calculation timing, C ′ is the previous count value, and X1 ′ is the previous first integrated value.

  The calculating unit 4 calculates the second integrated value X2 by substituting the calculated first integrated value X1 into the equation (1).

  The calculation unit 4 calculates the first integrated value X1 and the second integrated value X2 at a predetermined calculation timing. For example, the calculation timing may be a periodic timing managed in the pulse counter 100, or when there is a request command from an external device connected to the pulse counter 100 wirelessly or by wire. May be. The calculation unit 4 receives the count value C from the counter 1 when the calculation timing arrives, and uses the count value C, the previous count value C ′, the previous first integrated value X1 ′, and the overflow count n, The first integrated value X1 and the second integrated value X2 are calculated. The calculation unit 4 basically holds the received count value C, the calculated first integrated value X1, and the overflow count n, and uses them for the next calculation. In addition, the calculation unit 4 outputs the calculated second integrated value X2 as an integrated value of the number of pulses.

  When the count value C of the counter 1 overflows, the count value C once returns to 0, and thus the count value C cannot represent an increase from the previous count value C ′. Therefore, when the count value C of the counter 1 overflows, the calculation unit 4 calculates the first integrated value X1 not by the equation (2) but by the following equation (3).

  X1 = Cmax−C ′ + C + X1 ′ (3)

  The calculation unit 4 is only when the count value C received from the counter 1 at the calculation timing is smaller than the previous count value C ′ (provided that an abnormal state such as an internal reset or power-off has not occurred). Determines that an overflow has occurred. Usually, the time required for the counter 1 to count the number of pulses from 0 to the upper limit count value (depending on the transmission frequency of the pulse from which the pulse is generated and the upper limit count value of the counter 1) It is sufficiently longer than the time until the calculation timing. For this reason, the received count value C does not become larger than the previous count value C ′ in spite of the occurrence of overflow, so the above determination can be made.

  When the first integrated value X1 overflows, the calculation unit 4 increases the overflow count n by 1 and calculates the first integrated value X1 by the following equation (4).

  X1 = X1-Cmax (4)

  As a result, the first integrated value X1 is a value that once returned to 0 and resumed integration. Thus, each time the first integrated value X1 overflows, the number of overflows n is incremented, the first integrated value X1 is returned to 0, and the integration is restarted, thereby counting the number of pulses to a value larger than the upper limit count value. it can.

  Here, the calculation unit 4 changes the specific calculation method of the integrated value depending on whether the power source 2 is driven by a battery or an external power source. For example, when the calculation unit 4 operates abnormally, the pulse counter 100 may perform an internal reset, and the calculation process in that case differs between battery driving and external power supply driving. Furthermore, for example, the power supply 2 may be turned off because the battery runs out or the external power supply becomes an instantaneous power failure. Thereafter, the calculation processing when the power is turned on is battery driving and external power driving. It is different.

<Battery drive>
When the power source 2 is battery-driven, when the internal reset of the pulse counter 100 occurs, the counter 1 is not reset, and the overflow count n held by the arithmetic unit 4 is stored in the memory 3. That is, the count value C of the counter 1 is held. At the time of recovery after the internal reset, the counter 1 restarts counting from the held count value C. When the power supply 2 is turned off and the counter 1 is reset, that is, when the count value C is cleared, the overflow count n, the first integrated value X1, and the second integrated value X2 are also cleared. Counting and integration is resumed from 0.

  That is, the count value C is cleared when the power source 2 is turned off. At this time, the first integrated value X1 is also cleared, so the first integrated value X1 is always the same value as the count value C. . Of course, the previous first integrated value X1 'is always the same value as the previous count value C'.

Therefore, equation (2) is
X1 = C (2) ′
Therefore, when the calculation unit 4 receives the count value C from the counter 1 when returning after the internal reset, the first integrated value X1 is obtained. And the calculating part 4 reads the overflow count n preserve | saved at the memory 3, and calculates the 2nd integrated value X2 using Formula (1).

  That is, as shown in FIG. 2, even if an internal reset of the pulse counter 100 occurs, the count value C and the first integrated value X1 are not cleared, and the count value C retained after the pulse counter 100 returns. Then, the integration of the first integrated value X1 and the second integrated value X2 is resumed using the stored overflow count n. Thus, regardless of whether the pulse counter 100 is internally reset, the first integrated value X1 and the second integrated value X2 are calculated as continuous integrated values.

  On the other hand, as shown in FIG. 3, when the count value C of the counter 1 is cleared by turning off the power, the first integrated value X1 is also cleared and the second integrated value X2 is also cleared. When the power source 2 is turned on, the counter 1 resumes counting the count value C from 0, and the computing unit 4 also resumes computing the first integrated value X1, the overflow count n, and the second integrated value X2 from 0. To do.

<External power supply drive>
On the other hand, when the power supply 2 is driven by external electric power, the calculation unit 4 stores the first integrated value X1 and the overflow count n held by the calculation unit 4 at the time of calculation and when the internal reset of the pulse counter 100 occurs. Save to 3. When the internal reset of the pulse counter 100 is generated and when the power is turned off, the counter 1 is reset and the count value C of the counter 1 is cleared.

  At the time of recovery after the internal reset, the count value C is restarted from 0. Then, at the calculation timing immediately after the internal reset, the calculation unit 4 calculates the first integrated value X1 and the second integrated value X2 with reference to the first integrated value X1 and the overflow count n stored in the memory 3.

  For example, as shown in FIG. 4, when an internal reset occurs between the calculation timings (i) and (ii), at the calculation timing (ii) immediately after the occurrence of the internal reset, the calculation unit 4 The first integrated value X1 is calculated by the equation (2) using the count value C received in the above and the first integrated value X1 stored in the memory 3 as the previous first integrated value X1 ′. Specifically, the previous first integrated value X1 'is the latest first integrated value X1 stored in the memory 3, and is the first integrated value X1 when an internal reset occurs. Since the count value C is once cleared, the previous count value C ′ is zero. By this calculation, the increment of the count value C from the occurrence of the internal reset to the calculation timing (ii) is added to the first integrated value X1 when the internal reset occurs, and the first integrated value X1 at the calculation timing (ii). Is required. Further, the calculating unit 4 calculates the second integrated value X2 by the equation (1) using the calculated first integrated value X1 and the overflow count n stored in the memory 3 (in this example, 0). Thus, the first integrated value X1 and the second integrated value X2 are calculated as continuous integrated values.

  On the other hand, when the power supply 2 is turned off, the counter 1 is reset and the count value C is cleared. Thereafter, when the power supply 2 is turned on, the count value C is restarted from 0. Then, at the calculation timing immediately after the power is turned on, the calculation unit 4 calculates the first integrated value X1 and the second integrated value X2 with reference to the first integrated value X1 and the overflow count n stored in the memory 3. .

  For example, as shown in FIG. 4, when the power source 2 is temporarily turned off between the computation timings (v) and (vi) and then turned on, the computation timing (vi) immediately after the power on is The calculation unit 4 uses the count value C received at that time and the first accumulated value X1 stored in the memory 3 as the first accumulated value X1 ′, and the first accumulated value X1 according to the equation (2). Is calculated. Specifically, the previous first integrated value X1 'is the first integrated value X1 at the calculation timing (v), which is the latest first integrated value X1 stored in the memory 3. Since the count value C is once cleared, the previous count value C ′ is zero. By this calculation, the increment of the count value C from the power-on to the calculation timing (vi) is added to the first integrated value X1 at the calculation timing (v), and the first integrated value X1 at the calculation timing (vi) is obtained. Desired. That is, the increment of the count value C from the previous calculation timing (v) until the power is turned off cannot be integrated, but the first integrated value X1 at the latest calculation timing (v) is stored. Therefore, the integration can be continued by using it. Further, the calculation unit 4 calculates the second integrated value X2 by the equation (1) using the calculated first integrated value X1 and the overflow count n stored in the memory 3 (2 in this example). Thus, the first integrated value X1 and the second integrated value X2 are calculated as continuous integrated values.

  Thus, in external power supply driving, the power supply 2 may be turned on after being turned off once due to an instantaneous power failure or the like. In this case, the counter 1 cannot hold the count value C and must be cleared. Therefore, a first integrated value X1 having the same counting ability as that of the counter 1 (that is, having the same upper limit count value) is set, the count value C is integrated as the first integrated value X1, and the first accumulated value X1 is accumulated at a predetermined storage timing. One accumulated value X1 and overflow count n are stored in the memory 3. Thereby, even if the counter 1 is reset due to an instantaneous power failure or the like, the accumulation of the number of pulses can be continued using the stored first accumulated value X1. Then, by obtaining the second integrated value X2 from the first integrated value X1 and the overflow count n, the number of pulses can be counted up to a count value larger than the upper limit count value Cmax. Here, the storage timing is, for example, a calculation timing and an internal reset time.

  At the time of internal reset, the count value C of the counter 1 can be held as in the case of battery drive. However, by clearing the count value C at the time of internal reset, it is possible to perform the same processing as at power-off at the time of internal reset.

  As described above, the pulse counter 100 is configured such that when the upper limit count value Cmax is set and the number of pulses is counted up to the upper limit count value Cmax, the counter 1 configured to count the pulse number from 0 again and the counter 1 The calculation unit 4 calculates a first integrated value X1 by integrating the count value, and the first integrated value X1 is the upper limit count value. When Cmax is reached, the first integrated value X1 is again integrated from 0, and based on the overflow count n, which is the number of times the first integrated value X1 reaches the upper limit count value Cmax, and the first integrated value X1, A second integrated value X2 as an integrated value is calculated.

  According to this configuration, even if the counter 1 can only count up to the upper limit count value Cmax, the number of pulses can be counted up to a value greater than the upper limit count value Cmax by counting the overflow count n of the first integrated value X1. it can.

  Specifically, the calculation unit 4 calculates the second integrated value X2 by adding the first integrated value X1 to the value obtained by multiplying the upper limit count value Cmax by the overflow count n.

  The pulse counter 100 further includes a memory 3 for storing data, and the calculation unit 4 stores the first integrated value X1 and the overflow count n in the memory 3 at a predetermined storage timing, and the counter 1 is reset. After the calculation, the second integrated value X2 is calculated based on the count value C of the counter 1 when the calculation is performed, the first integrated value X1 stored in the memory 3, and the overflow count n.

  According to this configuration, even if the count value C of the counter 1 is cleared halfway, the second integrated value X2 is continuously integrated with reference to the first integrated value X1 and the overflow count n stored in the memory 3. It can be calculated as a value.

  Further, the pulse counter 100 further includes a power source 2 constituted by an external power source, and the counter 1 is reset when the power source 2 is turned off and when the pulse counter is internally reset.

  Further, the pulse counter 100 further includes a power source 2 constituted by a battery and a memory 3 for storing data, and the counter 1 is not reset even when the pulse counter 100 is internally reset. C, and the calculation unit 4 stores the overflow count n in the memory 3 at a predetermined storage timing, and the counter 1 count value when performing the calculation after the pulse counter 100 is internally reset. Based on C and the number of overflows n stored in the memory 3, the second integrated value X2 is calculated.

  According to this configuration, even when the internal reset of the pulse counter 100 occurs, the count value C of the counter 1 is not cleared. Therefore, if the overflow count n is appropriately stored in the memory 3, the second integrated value X2 can be calculated using the count value C of the counter 1 and the overflow count n stored in the memory 3.

  Further, the pulse counter 100 further includes a power source 2 capable of switching between a battery and an external power source, and a memory 3 for storing data. When the power source 2 is a battery, the counter 1 includes the pulse counter 100 Even when the internal reset is performed, the count value C is not retained, and the calculation unit 4 stores the overflow count n in the memory 3 at a predetermined storage timing, and after the pulse counter 100 is internally reset. When calculating the second integrated value X2 based on the count value C of the counter 1 when performing the calculation and the overflow count n stored in the memory 3, while the power source 2 is an external power source, The counter 1 is reset when the power source 2 is turned off and when the pulse counter is internally reset, and the calculation unit 4 sets the first integrated value X1 and the overflow count n to a predetermined value. The count value C of the counter 1 when performing the calculation after the counter 1 is reset, the first integrated value X1 and the overflow count n stored in the memory 3 are stored in the memory 3 at the existing timing. Based on the above, the second integrated value X2 is calculated.

  According to this configuration, the pulse counter 100 can appropriately switch the arithmetic processing depending on whether the power source 2 is a battery or an external power source.

  When the power supply 2 is a battery, the first integrated value X1 and the overflow count n held by the calculation unit 4 can be stored in the memory 3 at each calculation, as in the case where the power supply 2 is an external power supply. . However, by not doing so, current consumption can be suppressed and battery life can be extended.

<< Embodiment 2 >>
Next, the node device 110 according to the second embodiment will be described. FIG. 5 is a block diagram of the node device 110, and FIG. 6 is a schematic diagram of the network system 1000. The pulse counter 100 is built in the node device 110. The node device 110 forms a network system (hereinafter referred to as “system”) 1000. System 1000 is a wireless ad hoc network. This system 1000 is configured such that adjacent small wireless terminals autonomously construct a network. The system 1000 includes a plurality of node devices 110, 110,... And user devices 120, 120,. A user device 120 is connected to each node device 110. The user equipment includes a PC (personal computer) 120A, a measuring instrument 120B, and the like (hereinafter simply referred to as “user equipment 120” when each user equipment is not distinguished).

  In a plurality of user devices, the PC 120A functions as a master device, and the other measuring devices 120B, 120B,... Function as slave devices. That is, the PC 120A controls the measuring instruments 120B, 120B,. Hereinafter, the PC 120A is also referred to as a master user device 120A, and the measuring instrument 120B is also referred to as a slave user device 120B.

  The plurality of node devices 110, 110,... Are coupled wirelessly. That is, the plurality of node devices 110, 110,... Construct a wireless network. The plurality of node devices 110, 110,... Include one base station node device 110A and a plurality of child node devices 110B, 110B,. The base station node device 110A is a parent device, and the child node device 110B is a child device. The master user equipment 120A is connected to the base station node device 110A. The slave user device 120B is connected to the child node device 110B. Hereinafter, when each node device is not distinguished, it is simply referred to as “node device 110”.

  The wireless link between the plurality of node devices 110 and 110 may be, for example, a short-range wireless network that conforms to IEEE 802.15.4 using the 920 MHz band. This IEEE 802.15.4 is one of wireless communication standards called PAN (Personal Area Network) or WPAN (Wireless Personal Area Network), and has low cost, low power consumption, high reliability and security. Also, the wireless link is not limited to the specific wireless network described above, and can be any suitable network that can exchange information typically in the form of packets.

  Further, the node device 110 has an automatic relay function, and can autonomously configure a network by sensing the communication environment. The exemplary network is a true mesh and the number of hops is virtually unlimited. In other words, embodiments of the present invention can use multi-hop wireless networks. Thus, a wireless ad hoc network is constructed using one node device 110 as one wireless terminal.

  The node device 110 can typically be realized by a circuit element group including a semiconductor element mounted on a substrate. Typically, the node device 110 can be realized by a combination of an analog circuit that handles an analog signal from a user device and a high-frequency signal for a wireless network, and a digital circuit having an MCU as a main element.

  The control of the node device 110 can typically be realized by software. That is, the control of the node device 110 can be typically realized by software stored in a computer-readable medium. Examples of the computer readable medium include a hard disk drive and a semiconductor memory. Alternatively, the control of the node device 110 may be realized by a combination of software and hardware, or only by hardware.

  The measuring instrument 120B measures and detects various physical quantities (temperature, humidity, current, voltage, power, etc.) and can be any measuring instrument. For example, the measuring instrument 120 is a wattmeter. The measuring instrument 120B is configured to output a pulse corresponding to the measurement result. For example, if the measuring instrument 120B is a wattmeter, one pulse is output every 10 Wh.

  The measuring instrument 120B is coupled to the child node device 110B by wire. The child node device 110B and the measuring instrument 120B have a common communication standard (RS485 in this embodiment) interface.

  The PC 120A can visually display or statistically process data received from the measuring instrument 120B using, for example, software including a GUI (graphical user interface). Further, the PC 120A can transmit various control signals to the measuring instrument 120B using, for example, software.

  The node device 110 includes an RF unit 410 and an antenna 430. Data from the user device 120 is input to the RF unit 410. The RF unit 410 converts measurement data output from the user equipment 120 into a radio signal, and transmits the radio signal to another node device 110, for example, an upstream node (such as the base station node device 110A).

  The RF unit 410 includes an interface 440, a DC (direct current) power supply 445, an MCU (micro controller unit) 450, a ROM (read only memory) 452, a RAM (random access memory) 454, a timer 456, a wireless transmission / reception unit 458, and an RF interface 460. Have The interface 440 converts the signal output by the user equipment 120 into an appropriate signal (for example, a 10-bit digital signal) that can be processed by the MCU 450. The interface 440 is an interface common to the communication standard of the user device 120, and is an RS485 interface in this embodiment. The DC power source 445 supplies a DC power source to each functional block of the RF unit 410. The DC power source 445 can be, for example, a lithium battery that supplies a direct current of 3V.

  The MCU 450 is a microprocessor that is used to realize the functions of the node device 110. The ROM 452 or the RAM 454 stores programs and data necessary for realizing the functions of the node device 110. The timer 456 measures the timing of turning off the power, for example, and triggers the MCU 450 to cut off the power supply from the DC power supply 445 when a predetermined time has elapsed. MCU 450 may include peripheral elements such as ROM 452, RAM 454, and timer 456 therein.

  The wireless transmission / reception unit 458 converts data from the MCU 450 into a response packet to be sent to another node device 110, or converts a request packet received from the other node device 110 into data. The RF interface 460 converts the packet output from the wireless transmission / reception unit 458 into an RF signal and outputs the RF signal to the antenna, reproduces the packet from the RF signal received by the antenna, and outputs the packet to the wireless transmission / reception unit 458.

  Part or all of the functional block groups may be integrated and realized by being appropriately combined. For example, the RF unit 410 may be realized as a hybrid IC (integrated circuit). Furthermore, the RF unit 410 and the antenna 430 may be integrated on a single substrate.

  Thus, the pulse counter 100 can be applied to the node device 110 that constructs the network system 1000 as an example. The pulse counter 100 counts the pulses output from the measuring instrument 120B connected to the node device 110. Then, the pulse counter 100 outputs an integrated value of the pulse, and this integrated value of the pulse is finally transmitted to the PC 120A via the node device 110. For example, the PC 120A uses the integrated value of the pulse in a predetermined application. At this time, the PC 120A handles the integrated pulse value as 32-bit data. Here, even if the upper limit count value of the counter 1 of the pulse counter 100 is 28 bits, the pulse counter 100 accumulates the number of pulses up to a value larger than 28 bits, and the accumulated value according to the number of bits of the host device. Is output. In other words, the pulse counter 100 converts the 28-bit count value into a 32-bit integrated value.

<< Other Embodiments >>
As described above, the embodiment has been described as an example of the technique disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed. Moreover, it is also possible to combine each component demonstrated by the said embodiment and it can also be set as new embodiment. In addition, among the components described in the accompanying drawings and detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to exemplify the above technique May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  About the said embodiment, it is good also as following structures.

  In the above configuration, the power source 2 of the pulse counter 100 is configured to be able to select a battery or an external power source. However, the power source 2 may have a configuration in which only one of the battery and the external power source can be used. In that case, the above-described calculation method corresponding to the power source is employed.

  Further, although the pulse counter 100 is applied to the node device 110, it is not limited to this. The pulse counter 100 can be applied to any device that needs to count pulses.

  As described above, the technique disclosed herein is useful for a pulse counter.

100 Pulse counter 1 Counter (counter)
2 Power supply 3 Memory 4 Calculation unit

Claims (6)

When an upper limit count value is set and the number of pulses is counted up to the upper limit count value, a counting unit configured to count the pulse number from 0 again,
A calculation unit that calculates the integrated value of the pulse by integrating the count value of the counting unit,
The computing unit is
Calculating the first integrated value by integrating the count value;
When the first integrated value reaches the upper limit count value, the first integrated value is again integrated from 0,
A pulse counter that calculates a second integrated value as an integrated value of the pulse based on an overflow count that is the number of times the first integrated value reaches the upper limit count value and the first integrated value. The pulse counter according to claim 1.
The calculation unit is a pulse counter that calculates the second integrated value by adding the first integrated value to a value obtained by multiplying the upper limit count value by the overflow count. The pulse counter according to claim 1 or 2,
A storage unit for storing data;
The calculation unit stores the first integrated value and the overflow count in the storage unit at a predetermined storage timing, and the calculation unit counts when performing the calculation after the counting unit is reset. A pulse counter that calculates the second integrated value based on a numerical value and the first integrated value and the overflow count stored in the storage unit. The pulse counter according to claim 3,
A power supply composed of an external power supply is further provided.
The counter is a pulse counter that is reset when the power is turned off and when the pulse counter is internally reset. The pulse counter according to claim 1 or 2,
A power source comprised of batteries;
A storage unit for storing data;
The counting unit is not reset even when the pulse counter is internally reset, holds the count value,
The arithmetic unit stores the overflow count in the storage unit at a predetermined storage timing, and the count value of the counter when performing the calculation at the time of calculation after the pulse counter is internally reset, A pulse counter that calculates the second integrated value based on the overflow count stored in the storage unit. The pulse counter according to claim 1 or 2,
A power source capable of switching between a battery and an external power source;
A storage unit for storing data;
When the power source is a battery,
The counting unit is not reset even when the pulse counter is internally reset, holds the count value,
The arithmetic unit stores the overflow count in the storage unit at a predetermined storage timing, and the count value of the counter when performing the calculation at the time of calculation after the pulse counter is internally reset, While calculating the second integrated value based on the number of overflows stored in the storage unit,
When the power source is an external power source,
The counter is reset when the power is turned off and when the pulse counter is internally reset,
The calculation unit stores the first integrated value and the overflow count in the storage unit at a predetermined storage timing, and the calculation unit counts when performing the calculation after the counting unit is reset. A pulse counter that calculates the second integrated value based on a numerical value and the first integrated value and the overflow count stored in the storage unit.

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