JP4295915B2 - コンピュータプログラムとハードウェアモデルを並列にコンパイレーション、シミュレーション、及び実行するためのコンパイラ指向装置 - Google Patents

コンピュータプログラムとハードウェアモデルを並列にコンパイレーション、シミュレーション、及び実行するためのコンパイラ指向装置 Download PDF

Info

Publication number
JP4295915B2
JP4295915B2 JP2000517338A JP2000517338A JP4295915B2 JP 4295915 B2 JP4295915 B2 JP 4295915B2 JP 2000517338 A JP2000517338 A JP 2000517338A JP 2000517338 A JP2000517338 A JP 2000517338A JP 4295915 B2 JP4295915 B2 JP 4295915B2
Authority
JP
Japan
Prior art keywords
execution
database
simulation
client
parallel processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000517338A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001521218A (ja
JP2001521218A5 (enExample
Inventor
ジョン シー ウィーリス
ロバート エヌ ニューシューツ
Original Assignee
エフティーエル システムズ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エフティーエル システムズ インコーポレイテッド filed Critical エフティーエル システムズ インコーポレイテッド
Publication of JP2001521218A publication Critical patent/JP2001521218A/ja
Publication of JP2001521218A5 publication Critical patent/JP2001521218A5/ja
Application granted granted Critical
Publication of JP4295915B2 publication Critical patent/JP4295915B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/10—Requirements analysis; Specification techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP2000517338A 1997-10-21 1998-10-21 コンピュータプログラムとハードウェアモデルを並列にコンパイレーション、シミュレーション、及び実行するためのコンパイラ指向装置 Expired - Fee Related JP4295915B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/954,843 US5999734A (en) 1997-10-21 1997-10-21 Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models
US08/954,843 1997-10-21
PCT/US1998/022261 WO1999021085A1 (en) 1997-10-21 1998-10-21 Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models

Publications (3)

Publication Number Publication Date
JP2001521218A JP2001521218A (ja) 2001-11-06
JP2001521218A5 JP2001521218A5 (enExample) 2006-01-05
JP4295915B2 true JP4295915B2 (ja) 2009-07-15

Family

ID=25496004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000517338A Expired - Fee Related JP4295915B2 (ja) 1997-10-21 1998-10-21 コンピュータプログラムとハードウェアモデルを並列にコンパイレーション、シミュレーション、及び実行するためのコンパイラ指向装置

Country Status (5)

Country Link
US (1) US5999734A (enExample)
EP (3) EP1025491B1 (enExample)
JP (1) JP4295915B2 (enExample)
DE (1) DE69826700T2 (enExample)
WO (1) WO1999021085A1 (enExample)

Families Citing this family (163)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6938245B1 (en) * 1997-10-29 2005-08-30 Veritas Operating Corporation Interactive debugging system with debug data base system
US20020049573A1 (en) * 1998-05-13 2002-04-25 El Ata Nabil A. Abu Automated system and method for designing model based architectures of information systems
US7031901B2 (en) 1998-05-13 2006-04-18 Abu El Ata Nabil A System and method for improving predictive modeling of an information system
US6990437B1 (en) 1999-07-02 2006-01-24 Abu El Ata Nabil A Systems and method for determining performance metrics for constructing information systems
US7783468B2 (en) * 1998-05-13 2010-08-24 Accretive Technologies, Inc. Automated system and method for service and cost architecture modeling of enterprise systems
US6311144B1 (en) * 1998-05-13 2001-10-30 Nabil A. Abu El Ata Method and apparatus for designing and analyzing information systems using multi-layer mathematical models
US7389211B2 (en) * 1998-05-13 2008-06-17 Abu El Ata Nabil A System and method of predictive modeling for managing decisions for business enterprises
US6427234B1 (en) * 1998-06-11 2002-07-30 University Of Washington System and method for performing selective dynamic compilation using run-time information
US6862563B1 (en) 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US6330605B1 (en) * 1998-11-19 2001-12-11 Volera, Inc. Proxy cache cluster
US6467082B1 (en) * 1998-12-02 2002-10-15 Agere Systems Guardian Corp. Methods and apparatus for simulating external linkage points and control transfers in source translation systems
US6370492B1 (en) * 1998-12-08 2002-04-09 Lsi Logic Corporation Modified design representation for fast fault simulation of an integrated circuit
US6466898B1 (en) * 1999-01-12 2002-10-15 Terence Chan Multithreaded, mixed hardware description languages logic simulation on engineering workstations
US6343371B1 (en) * 1999-01-14 2002-01-29 Compaq Computer Corporation System and method for statically detecting potential race conditions in multi-threaded computer programs
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6591272B1 (en) * 1999-02-25 2003-07-08 Tricoron Networks, Inc. Method and apparatus to make and transmit objects from a database on a server computer to a client computer
US6502175B1 (en) * 1999-03-31 2002-12-31 Lucent Technologies Inc. Method and apparatus for locating caches in a network to optimize performance
US6560754B1 (en) * 1999-05-13 2003-05-06 Arc International Plc Method and apparatus for jump control in a pipelined processor
US6230114B1 (en) 1999-10-29 2001-05-08 Vast Systems Technology Corporation Hardware and software co-simulation including executing an analyzed user program
US6973417B1 (en) * 1999-11-05 2005-12-06 Metrowerks Corporation Method and system for simulating execution of a target program in a simulated target system
US6609246B1 (en) * 1999-12-07 2003-08-19 Bull Hn Information Systems Inc. Integrated development environment for high speed transaction processing WWW applications on heterogeneous computer systems
US6633865B1 (en) 1999-12-23 2003-10-14 Pmc-Sierra Limited Multithreaded address resolution system
US6721696B1 (en) 2000-02-25 2004-04-13 Centric Software, Inc. Simulation program having generic attribute access schema
US6944583B1 (en) * 2000-02-02 2005-09-13 Centric Software, Inc. Multi-threaded frame safe synchronization of a simulation
US6601229B1 (en) * 2000-03-09 2003-07-29 International Business Machines Corporation Client/server behavioral modeling and testcase development using VHDL for improved logic verification
WO2001069411A2 (en) 2000-03-10 2001-09-20 Arc International Plc Memory interface and method of interfacing between functional entities
JP2001325103A (ja) * 2000-05-16 2001-11-22 Denso Corp シミュレータ作成方法、シミュレータ作成装置およびシミュレータの作成支援方法
CN100520720C (zh) * 2000-06-19 2009-07-29 P·C·克劳斯及合伙人公司 分布式仿真
US6931636B2 (en) * 2000-08-08 2005-08-16 Texas Instruments Incorporated Multiprocessor emulation support using dynamic linking
US6826619B1 (en) 2000-08-21 2004-11-30 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US7881920B2 (en) 2000-08-29 2011-02-01 Abu El Ata Nabil A Systemic enterprise management method and apparatus
US6487643B1 (en) 2000-09-29 2002-11-26 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6772298B2 (en) 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US7016826B2 (en) * 2000-12-21 2006-03-21 Intel Corporation Apparatus and method of developing software for a multi-processor chip
US7234029B2 (en) 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US6791412B2 (en) 2000-12-28 2004-09-14 Intel Corporation Differential amplifier output stage
US6721918B2 (en) 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US6925634B2 (en) * 2001-01-24 2005-08-02 Texas Instruments Incorporated Method for maintaining cache coherency in software in a shared memory system
US20040133745A1 (en) 2002-10-28 2004-07-08 Quicksilver Technology, Inc. Adaptable datapath for a digital processing system
US7489779B2 (en) 2001-03-22 2009-02-10 Qstholdings, Llc Hardware implementation of the secure hash standard
US7400668B2 (en) 2001-03-22 2008-07-15 Qst Holdings, Llc Method and system for implementing a system acquisition function for use with a communication device
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US6577678B2 (en) 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
US20020169738A1 (en) * 2001-05-10 2002-11-14 Giel Peter Van Method and system for auditing an enterprise configuration
US20020184327A1 (en) 2001-05-11 2002-12-05 Major Robert Drew System and method for partitioning address space in a proxy cache server cluster
JPWO2002099704A1 (ja) * 2001-05-30 2004-09-16 株式会社鷹山 システム開発支援装置、システム開発支援方法、およびコンピュータ読み取り可能な記録媒体
US6971098B2 (en) 2001-06-27 2005-11-29 Intel Corporation Method and apparatus for managing transaction requests in a multi-node architecture
US7055144B2 (en) * 2001-07-12 2006-05-30 International Business Machines Corporation Method and system for optimizing the use of processors when compiling a program
US6668359B1 (en) * 2001-10-31 2003-12-23 Lsi Logic Corporation Verilog to vital translator
US20030149962A1 (en) * 2001-11-21 2003-08-07 Willis John Christopher Simulation of designs using programmable processors and electronically re-configurable logic arrays
US7328195B2 (en) 2001-11-21 2008-02-05 Ftl Systems, Inc. Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model
US7046635B2 (en) 2001-11-28 2006-05-16 Quicksilver Technology, Inc. System for authorizing functionality in adaptable hardware devices
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7493470B1 (en) 2001-12-07 2009-02-17 Arc International, Plc Processor apparatus and methods optimized for control applications
US7602740B2 (en) 2001-12-10 2009-10-13 Qst Holdings, Inc. System for adapting device standards after manufacture
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7403981B2 (en) 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US7996517B2 (en) * 2002-01-23 2011-08-09 Novell, Inc. Transparent network connection takeover
US7076555B1 (en) 2002-01-23 2006-07-11 Novell, Inc. System and method for transparent takeover of TCP connections between servers
US7007271B2 (en) * 2002-04-18 2006-02-28 Sun Microsystems, Inc. Method and apparatus for integrated instruction scheduling and register allocation in a postoptimizer
US6732354B2 (en) * 2002-04-23 2004-05-04 Quicksilver Technology, Inc. Method, system and software for programming reconfigurable hardware
CN1666202A (zh) * 2002-04-25 2005-09-07 Arc国际公司 管理集成电路设计的装置和方法
US7493375B2 (en) 2002-04-29 2009-02-17 Qst Holding, Llc Storage and delivery of device features
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US20040034858A1 (en) * 2002-08-14 2004-02-19 Kushlis Robert J. Programming a multi-threaded processor
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US7290089B2 (en) 2002-10-15 2007-10-30 Stmicroelectronics, Inc. Executing cache instructions in an increased latency mode
US7392165B2 (en) * 2002-10-21 2008-06-24 Fisher-Rosemount Systems, Inc. Simulation system for multi-node process control systems
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7478031B2 (en) 2002-11-07 2009-01-13 Qst Holdings, Llc Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
US7111287B2 (en) * 2003-01-10 2006-09-19 International Business Machines Corporation Global processor resource assignment in an assembler
US7269616B2 (en) * 2003-03-21 2007-09-11 Stretch, Inc. Transitive processing unit for performing complex operations
US7590829B2 (en) * 2003-03-31 2009-09-15 Stretch, Inc. Extension adapter
US7613900B2 (en) * 2003-03-31 2009-11-03 Stretch, Inc. Systems and methods for selecting input/output configuration in an integrated circuit
US8001266B1 (en) 2003-03-31 2011-08-16 Stretch, Inc. Configuring a multi-processor system
US7581081B2 (en) * 2003-03-31 2009-08-25 Stretch, Inc. Systems and methods for software extensible multi-processing
US7424703B1 (en) 2003-04-01 2008-09-09 Cadence Design Systems, Inc. Method and system for simulation of mixed-language circuit designs
US7712080B2 (en) * 2003-05-21 2010-05-04 The Regents Of The University Of California Systems and methods for parallel distributed programming
US20040236562A1 (en) * 2003-05-23 2004-11-25 Beckmann Carl J. Using multiple simulation environments
US7609297B2 (en) 2003-06-25 2009-10-27 Qst Holdings, Inc. Configurable hardware based digital imaging apparatus
US7373642B2 (en) * 2003-07-29 2008-05-13 Stretch, Inc. Defining instruction extensions in a standard programming language
US7418575B2 (en) * 2003-07-29 2008-08-26 Stretch, Inc. Long instruction word processing with instruction extensions
US20050049843A1 (en) * 2003-08-29 2005-03-03 Lee Hewitt Computerized extension apparatus and methods
US7797683B2 (en) * 2003-12-29 2010-09-14 Intel Corporation Decoupling the number of logical threads from the number of simultaneous physical threads in a processor
US20050193378A1 (en) * 2004-03-01 2005-09-01 Breault Richard E. System and method for building an executable program with a low probability of failure on demand
US20060031821A1 (en) * 2004-08-04 2006-02-09 Rutter Budd J Ii Divided compiling program application functionality for software development
US20060130018A1 (en) * 2004-11-23 2006-06-15 Hsieh Cheng-Hsueh A Method and apparatus for implementing a codeless intrinsic framework for embedded system processors
US7509633B2 (en) * 2004-12-16 2009-03-24 International Business Machines Corporation System and method for grid-based distribution of Java project compilation
US7509244B1 (en) 2004-12-22 2009-03-24 The Mathworks, Inc. Distributed model compilation
US8332844B1 (en) 2004-12-30 2012-12-11 Emendable Assets Limited Liability Company Root image caching and indexing for block-level distributed application management
US7721282B1 (en) * 2004-12-30 2010-05-18 Panta Systems, Inc. Block-level I/O subsystem for distributed application environment management
CN101198930B (zh) * 2005-04-13 2011-07-27 艾利森电话股份有限公司 用于支持计算机系统中的数据值一致性的系统和方法
GB0519981D0 (en) 2005-09-30 2005-11-09 Ignios Ltd Scheduling in a multicore architecture
US9038040B2 (en) * 2006-01-25 2015-05-19 International Business Machines Corporation Method for partitioning programs between a general purpose core and one or more accelerators
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
US8296430B2 (en) 2007-06-18 2012-10-23 International Business Machines Corporation Administering an epoch initiated for remote memory access
US7925487B2 (en) * 2007-06-29 2011-04-12 Microsoft Corporation Replaying distributed systems
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8095735B2 (en) * 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US9710384B2 (en) 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US8122229B2 (en) * 2007-09-12 2012-02-21 Convey Computer Dispatch mechanism for dispatching instructions from a host processor to a co-processor
US8561037B2 (en) 2007-08-29 2013-10-15 Convey Computer Compiler for generating an executable comprising instructions for a plurality of different instruction sets
US8156307B2 (en) * 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US8069021B2 (en) * 2007-09-28 2011-11-29 Rockwell Automation Technologies, Inc. Distributed simulation and synchronization
US20090089029A1 (en) * 2007-09-28 2009-04-02 Rockwell Automation Technologies, Inc. Enhanced execution speed to improve simulation performance
US7801710B2 (en) * 2007-09-28 2010-09-21 Rockwell Automation Technologies, Inc. Simulation controls for model variability and randomness
US8548777B2 (en) * 2007-09-28 2013-10-01 Rockwell Automation Technologies, Inc. Automated recommendations from simulation
US20090089031A1 (en) * 2007-09-28 2009-04-02 Rockwell Automation Technologies, Inc. Integrated simulation of controllers and devices
US20090089234A1 (en) * 2007-09-28 2009-04-02 Rockwell Automation Technologies, Inc. Automated code generation for simulators
US9065839B2 (en) 2007-10-02 2015-06-23 International Business Machines Corporation Minimally buffered data transfers between nodes in a data communications network
US20090112668A1 (en) * 2007-10-31 2009-04-30 Abu El Ata Nabil A Dynamic service emulation of corporate performance
US8245212B2 (en) * 2008-02-22 2012-08-14 Microsoft Corporation Building call tree branches and utilizing break points
US7933759B2 (en) * 2008-03-28 2011-04-26 Microsoft Corporation Predicate checking for distributed systems
US8122441B2 (en) * 2008-06-24 2012-02-21 International Business Machines Corporation Sharing compiler optimizations in a multi-node system
US8214814B2 (en) * 2008-06-24 2012-07-03 International Business Machines Corporation Sharing compiler optimizations in a multi-node system
US8495603B2 (en) * 2008-08-11 2013-07-23 International Business Machines Corporation Generating an executable version of an application using a distributed compiler operating on a plurality of compute nodes
US20100115233A1 (en) * 2008-10-31 2010-05-06 Convey Computer Dynamically-selectable vector register partitioning
US8205066B2 (en) * 2008-10-31 2012-06-19 Convey Computer Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor
US8302076B2 (en) * 2008-11-12 2012-10-30 Landmark Graphics Corporation Systems and methods for improved parallel ILU factorization in distributed sparse linear systems
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US9189233B2 (en) 2008-11-24 2015-11-17 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US20100242014A1 (en) * 2009-03-17 2010-09-23 Xiaohan Zhu Symmetric multi-processor operating system for asymmetric multi-processor architecture
US8423745B1 (en) 2009-11-16 2013-04-16 Convey Computer Systems and methods for mapping a neighborhood of data to general registers of a processing element
USD685464S1 (en) 2010-01-11 2013-07-02 Sanofi-Aventis Deutschland Gmbh Medical injector
WO2011091323A1 (en) 2010-01-21 2011-07-28 Qst Holdings, Llc A method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations
US8606979B2 (en) 2010-03-29 2013-12-10 International Business Machines Corporation Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network
US8365186B2 (en) 2010-04-14 2013-01-29 International Business Machines Corporation Runtime optimization of an application executing on a parallel computer
US8504730B2 (en) 2010-07-30 2013-08-06 International Business Machines Corporation Administering connection identifiers for collective operations in a parallel computer
US8578340B1 (en) 2010-09-24 2013-11-05 Ca, Inc. Recording and replaying computer program execution with recorded execution event breakpoints
US8565120B2 (en) 2011-01-05 2013-10-22 International Business Machines Corporation Locality mapping in a distributed processing system
US9317637B2 (en) 2011-01-14 2016-04-19 International Business Machines Corporation Distributed hardware device simulation
JP5751669B2 (ja) * 2011-07-08 2015-07-22 ルネサスエレクトロニクス株式会社 言語変換処理方法及び言語変換処理プログラム
US8689228B2 (en) 2011-07-19 2014-04-01 International Business Machines Corporation Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system
US20130086564A1 (en) * 2011-08-26 2013-04-04 Cognitive Electronics, Inc. Methods and systems for optimizing execution of a program in an environment having simultaneously parallel and serial processing capability
US9250948B2 (en) 2011-09-13 2016-02-02 International Business Machines Corporation Establishing a group of endpoints in a parallel computer
US9417855B2 (en) 2011-09-30 2016-08-16 Intel Corporation Instruction and logic to perform dynamic binary translation
US9361079B2 (en) * 2012-01-30 2016-06-07 Nvidia Corporation Method for compiling a parallel thread execution program for general execution
US9128747B2 (en) * 2012-03-20 2015-09-08 Infosys Limited Methods and systems for optimizing the performance of software applications at runtime
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
EP2687981B1 (en) * 2012-07-18 2017-12-27 MStar Semiconductor, Inc. Automated compiler specialisation for global optimisation
KR20140021389A (ko) * 2012-08-10 2014-02-20 한국전자통신연구원 모델 제작 및 실행 분리형 시뮬레이션 장치 및 그 방법
US10333820B1 (en) 2012-10-23 2019-06-25 Quest Software Inc. System for inferring dependencies among computing systems
US9880842B2 (en) 2013-03-15 2018-01-30 Intel Corporation Using control flow data structures to direct and track instruction execution
KR102092921B1 (ko) 2013-06-28 2020-03-24 삼성전자주식회사 시뮬레이션 장치 및 분산 시뮬레이션 시스템
US10042621B2 (en) * 2013-08-08 2018-08-07 Empire Technology Development Llc Migration of executing processes
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
US11005738B1 (en) 2014-04-09 2021-05-11 Quest Software Inc. System and method for end-to-end response-time analysis
GB2529842A (en) * 2014-09-03 2016-03-09 Ibm Generating coverage metrics for black-box testing
US9250900B1 (en) 2014-10-01 2016-02-02 Cadence Design Systems, Inc. Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network
US10291493B1 (en) 2014-12-05 2019-05-14 Quest Software Inc. System and method for determining relevant computer performance events
US10187260B1 (en) 2015-05-29 2019-01-22 Quest Software Inc. Systems and methods for multilayer monitoring of network function virtualization architectures
US10200252B1 (en) 2015-09-18 2019-02-05 Quest Software Inc. Systems and methods for integrated modeling of monitored virtual desktop infrastructure systems
US10230601B1 (en) * 2016-07-05 2019-03-12 Quest Software Inc. Systems and methods for integrated modeling and performance measurements of monitored virtual desktop infrastructure systems
CN109828758A (zh) * 2018-12-05 2019-05-31 苏州蜗牛数字科技股份有限公司 一种so文件的解析方法
IL289482B2 (en) * 2021-01-15 2025-02-01 Drivenets Ltd A Distributed Database System

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493029A (en) * 1982-05-14 1985-01-08 At&T Bell Laboratories Microprocessor with PLA adapted to implement subroutines
US4661901A (en) 1982-12-23 1987-04-28 International Business Machines Corporation Microprocessor control system utilizing overlapped programmable logic arrays
JP2738692B2 (ja) * 1988-01-29 1998-04-08 株式会社日立製作所 並列化コンパイル方法
US5644497A (en) * 1988-03-15 1997-07-01 Hyman; Edward Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array
US5111413A (en) * 1989-03-24 1992-05-05 Vantage Analysis Systems, Inc. Computer-aided engineering
US5390320A (en) * 1991-01-22 1995-02-14 Grumman Aerospace Corporation Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable standardized metafile
US5339429A (en) * 1991-05-08 1994-08-16 Hitachi, Ltd. Parallel processing system and compiling method used therefor
US5506999A (en) * 1992-01-22 1996-04-09 The Boeing Company Event driven blackboard processing system that provides dynamic load balancing and shared data between knowledge source processors
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5418953A (en) * 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
ATE257611T1 (de) * 1995-10-23 2004-01-15 Imec Inter Uni Micro Electr Entwurfssystem und -verfahren zum kombinierten entwurf von hardware und software
US5784636A (en) * 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation

Also Published As

Publication number Publication date
JP2001521218A (ja) 2001-11-06
DE69826700T2 (de) 2005-10-20
US5999734A (en) 1999-12-07
EP2328082A2 (en) 2011-06-01
WO1999021085A1 (en) 1999-04-29
EP2328082A3 (en) 2011-12-14
DE69826700D1 (de) 2004-11-04
EP1025491B1 (en) 2004-09-29
EP1025491A1 (en) 2000-08-09
EP1501009A1 (en) 2005-01-26

Similar Documents

Publication Publication Date Title
JP4295915B2 (ja) コンピュータプログラムとハードウェアモデルを並列にコンパイレーション、シミュレーション、及び実行するためのコンパイラ指向装置
JP4403080B2 (ja) 再構成可能なハードウェアエミュレーションによる制御データフローグラフを用いたデバッグ
JP4482454B2 (ja) 高級プログラミング言語におけるプログラムをハイブリッド計算プラットフォームの統一された実行可能要素に変換するためのプロセス
US7533246B2 (en) Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation
Kerr et al. Modeling GPU-CPU workloads and systems
Cheung et al. Sloth: Being lazy is a virtue (when issuing database queries)
US20040088666A1 (en) System and method for partitioning control-dataflow graph representations
JP2006505056A (ja) 制御フローグラフ表現を制御データフローグラフ表現に変換するためのシステムおよび方法
US6467082B1 (en) Methods and apparatus for simulating external linkage points and control transfers in source translation systems
Kleir et al. Optimization strategies for microprograms
Bijo et al. A Maude framework for cache coherent multicore architectures
Borriello et al. RISCs vs. CISCs for Prolog: A case study
Mitchell et al. A workbench for computer architects
Moreno et al. Simulation/evaluation environment for a VLIW processor architecture
Kelm et al. CIGAR: Application partitioning for a CPU/coprocessor architecture
Van Delm et al. The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead
Shipnes et al. A modular approach to Motorola PowerPC compilers.
KHALILI MAYBODI A Data-Flow Threads Co-processor for MPSoC FPGA Clusters
Wolski et al. Compiler‐Enforced Cache Coherence Using a Functional Language
Roostaie Design and analysis of a coherent memory sub-system for FPGA-based embedded systems
Shah An optimized CAM-8 simulator for the SPARC architecture
Wirt The challenges of new software for a new architecture
Mahmoodi et al. Improving CPU performance modelling in QEMU
Rigler Dynamic binary translation for automatically generated simulators
Shinde Debug Support for Retargetable Simulator FSim Using GDB

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051019

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051019

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071022

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080122

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080129

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080422

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080908

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20081208

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20081215

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090108

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090116

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090209

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090323

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090413

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140417

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees