JP4294977B2 - Nonvolatile storage device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory device using a static random access memory (SRAM) as a data buffer RAM of an erasable and writable nonvolatile memory section, and more particularly to initialization of a data buffer RAM, for example, in a flash memory. It is related to effective technology.
[0002]
[Prior art]
When initializing the stored information in the SRAM, the operation power of one of the CMOS inverters of the complementary MOS (CMOS) static memory cell is turned off to avoid collision between the initialization data and the driving power of the CMOS inverter. There are some (see Patent Documents 1 and 2).
[0003]
[Patent Document 1]
JP 2000-260184 A
[Patent Document 2]
JP-A-5-325557
[0004]
[Problems to be solved by the invention]
The present inventor has examined initialization of an SRAM when the SRAM is used as a data buffer RAM of a nonvolatile memory unit such as a flash memory unit. In this case, different from simply initializing the SRAM memory cell, the nature of the nonvolatile memory portion as a data buffer must be considered. For example, when only a part of the write unit of the nonvolatile memory unit is additionally written, the data buffer RAM is initialized to the write blocking logical value and then only the additional write data is transferred to the data buffer RAM. It is only necessary to transfer the write blocking data to the data buffer RAM one by one. Further, the number of data buffer RAMs increases in response to the increase in capacity of the nonvolatile memory unit, and when the data buffer RAMs are collectively initialized, the peak current must not be excessively increased.
[0005]
An object of the present invention is to provide a nonvolatile memory device that can initialize a data buffer RAM of a nonvolatile memory unit so as to contribute to an efficient access to the nonvolatile memory unit.
[0006]
Another object of the present invention is to provide a nonvolatile memory device that can reduce the peak current when the data buffer RAM of the nonvolatile memory section is initialized.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0009]
[1] A nonvolatile memory device according to the present invention includes an erasable and writable nonvolatile memory unit (FARY0 to FARY3), a data buffer RAM (BMRY0 to BMRY3) of the nonvolatile memory unit, and a control unit (CNT). And have. The data buffer RAM has a plurality of static memory cells. In a state where the supply of operating power is restarted by forcing one storage node (SR2) to the first polarity while the supply of operating power to the static memory cell is cut off. An initialization operation for forcing the other storage node (SR1) to a second polarity opposite to the first polarity is enabled. The controller instructs an initialization operation for the data buffer RAM in response to an external command.
[0010]
From the above, in the initialization operation, even if one storage node is forced to the first polarity in the state where the supply of the operation power of the static memory cell is cut off, no large current flows unnecessarily from the power supply side. Even if the supply of the operating power is restarted in this state and the other storage node is forced to the second polarity, the complementary state of the storage node is already determined, so that the transient memory current hardly flows and the static memory cell It is initialized. As a result, the initialization operation of the data buffer RAM can be speeded up, and the current flowing in the initialization operation can be kept small.
[0011]
Since the initialization operation can be instructed by an external command, the nonvolatile memory device is used when unnecessary data is cleared before partial writing to the nonvolatile memory unit or before the data buffer RAM is used as a data cache. When necessary, the data buffer RAM can be initialized as needed.
[0012]
In consideration of partial writing to the nonvolatile memory unit, the information stored in the data buffer RAM by the initialization operation is preferably a logical value for preventing writing in the nonvolatile memory unit. This improvement in the efficiency of partial write processing becomes apparent when the write unit in the nonvolatile memory unit is larger than the data input / output unit of the data buffer RAM. Further, it is most efficient that the initialization operation is a batch initialization operation for the data buffer RAM.
[0013]
As a specific form for performing the initialization operation, the data input / output terminals of the static memory cells are connected to complementary bit lines (BLB, BLT), and load transistors (Q7, Q8) that can be switch-controlled are connected to the complementary bit lines. ) Is connected, and one of the complementary bit lines is connected to a discharge transistor (Q10) which can be switched in a complementary manner with the load transistor of the one bit line, and the discharge transistor in the on state is one of the static memory cells. Force the storage node to the first polarity. The operation of forcing the other storage node of the static memory cell to the second polarity is performed by turning on the other load transistor of the complementary bit line.
[0014]
[2] Another nonvolatile memory device according to the present invention includes a plurality of memory banks and a control unit, wherein the memory bank is an erasable and writable nonvolatile memory unit, and a data buffer RAM of the nonvolatile memory unit And have. The data buffer RAM has a plurality of static memory cells. One storage node is forced to the first polarity while the supply of operating power to the static memory cells is cut off, and the other memory is stored with the supply of operating power resumed. An initialization operation is allowed that forces the node to a second polarity opposite to the first polarity. The controller instructs the initialization operation to the plurality of memory banks in a time-sharing manner.
[0015]
By performing the initialization operation in a time-sharing manner, it is easy to reduce the peak current when initializing the data buffer RAM of the nonvolatile memory unit.
[0016]
In consideration of partial writing to the nonvolatile memory unit, the information stored in the data buffer RAM by the initialization operation is preferably a logical value for preventing writing in the nonvolatile memory unit.
[0017]
In order to further suppress the initialization peak current of the data buffer RAM, when the data buffer RAM is divided into a plurality of memory mats (MATU, MATL), the initialization operation is performed in a time division manner between the memory mats. Good.
[0018]
[3] Still another nonvolatile memory device according to the present invention includes a plurality of memory banks and a control unit, wherein the memory bank is an erasable and writable nonvolatile memory unit, and a data buffer of the nonvolatile memory unit RAM. The data buffer RAM has a plurality of static memory cells, and after the supply of operation power to the static memory cells is cut off to reduce the accumulated charge in one storage node, the initial potential and static memory cell are set in both storage nodes. The initialization operation for supplying the operation power is enabled. Information stored in the data buffer RAM by the initialization operation has a logical value for preventing writing in the nonvolatile memory unit. It is most suitable for partial writing to the nonvolatile memory portion and contributes to improvement of access efficiency for partial writing.
[0019]
Also in the above, the control unit may collectively instruct the initialization operation to the plurality of memory banks in response to an external command. The controller may instruct the plurality of memory banks to perform the initialization operation in a time-sharing manner.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a planar layout configuration of a flash memory which is an example of a semiconductor memory device according to the present invention. The flash memory 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (chip) such as single crystal silicon by a known MOS integrated circuit manufacturing method.
[0021]
The flash memory 1 includes, for example, four memory banks BNK0 to BNK3 and a control unit CNT. The memory banks BNK0 to BNK3 include flash memory arrays FARY0 to FARY3 as nonvolatile memory units and buffer memories BMRY0 to BMRY3 as data buffer RAMs (buffer units). Corresponding to one flash memory array, the buffer memory is divided into two parts on the left and right. For convenience, the right buffer memory is suffixed (R), and the left buffer memory is suffixed (L).
[0022]
External input / output terminals i / o0 to i / o7 of the flash memory 1 are also used as address input terminals, data input terminals, data output terminals, and command input terminals. The flash memory 1 receives a command latch enable signal CLE, an address latch enable signal ALE, a chip enable signal CEb, a read enable signal REb, and a write enable signal WEb as external control signals such as a strobe signal, and a ready / busy signal R / Bb. Output. The chip enable signal CEb indicates a chip selection state in the flash memory 1, the read enable signal REb instructs a read operation from the external input / output terminals i / o0 to i / o7, and the write enable signal WEb is an external input / output terminal i. The write operation from / o0 to i / o7 is instructed. The command latch enable signal CLE means that a command is supplied from the outside to the external input / output terminals i / o0 to i / o7, and the address latch enable signal ALE is supplied from the outside to the external input / output terminals i / o0 to i / o7. This means that an address signal is supplied. The ready / busy signal R / Bb indicates, by a low level (L), that any of the flash memory arrays FARY0 to FARY3 is being erased, written, or read (busy state). The busy state or ready state for each flash memory array (FARY0 to FARY3) can be recognized from the outside by reading status information described later.
[0023]
The control unit CNT controls a signal interface function with the outside in accordance with the state of the strobe signal, and controls internal operations of the memory banks BNK0 to BNK3 in accordance with an input command.
[0024]
Each of the flash memory arrays FARY0 to FARY3 has a large number of nonvolatile memory cells arranged in a matrix. Although this non-volatile memory cell is not particularly limited, one memory cell is constituted by one known floating gate type transistor. For example, a nonvolatile memory cell includes a source and drain formed in a well region, a floating gate formed in a channel region between the source and drain via a tunnel oxide film, and an interlayer insulating film in the floating gate. Consists of stacked control gates. The control gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the source line. FIG. 1 representatively shows one nonvolatile memory cell MC and one bit line G-BL, and one end of the bit line G-BL is connected to a sense launch SL formed of a static latch circuit. .
[0025]
In the flash memory 1 of FIG. 1, 512 bytes (512B) of stored information is called one sector. The information storage unit for writing and reading is 2048 bytes (= 4 sectors), and this unit is called one page. 1024 bytes are also referred to as 1 kilobyte. One page is specified by a page address. Since the flash memory has field element isolation, the information storage unit for erasure is twice the write unit (= 4096 bytes), which is called one block. The even page address designation in the erase mode is the block designation.
[0026]
Although not particularly limited, in the flash memory 1, one non-volatile memory cell stores information of 2 bits. Accordingly, in each flash memory array FARY0 to FARY3, 2048 bytes of nonvolatile memory cells are connected to one word line, and page address information is even-numbered or odd-numbered 1024 connected to one corresponding word line. 1024-byte sense latches SL are arranged in parallel so as to correspond to the 1024 memory cells designated by the page address information on a one-to-one basis. Page address information specifies the page address within the entire memory bank, its least significant bit specifies an even or odd number of page address, its upper side specifies a word line, and the most significant 2 bits specify a memory bank To do. The word line selection is performed by a word line selection decoder (not shown), and the bit line selection in even page or odd page units is performed by an even / odd bit line selector (not shown). The 1024 bytes selected by the even / odd bit line selector. One bit line is connected to 1024 bytes of sense latches SL. In the erase mode, even page addresses are regarded as block addresses (addresses for two pages of one word line).
[0027]
The nonvolatile memory cell stores information by utilizing the change in the threshold voltage of the memory cell in accordance with the amount of charge stored in the floating gate. At this time, the threshold voltage of the memory cell is limited to a desired range according to the value of the stored data, and the threshold voltage distribution is called a memory threshold voltage distribution. For example, in this example, one non-volatile memory cell stores information of 2 bits, and four types of memory threshold values corresponding to data “01”, “00”, “10”, “11” of the stored information. The voltage distribution is determined. That is, the information storage state of one memory cell includes the erase state (“11”) as the fourth threshold voltage (Vth4) state and the first write state (“10”) as the first threshold voltage (Vth1) state. The second write state (“00”) as the second threshold voltage (Vth2) state and the third write state (“01”) as the third threshold voltage (Vth3) state are selected. Although not particularly limited, the threshold voltage has a relationship of Vth4 <Vth1 <Vth2 <Vth3. A total of four information storage states are determined by 2-bit data. In order to obtain the above memory threshold distribution, the write verify voltage applied to the word line during the write operation after erasure is set to three different voltages, and these three voltages are sequentially switched to three times. Separately, write operation is performed. In each of these three write operations, 0 V is applied to the write-selected bit line and 1 V is applied to the non-selected bit line. Although not particularly limited, the word line is set to 17 V, for example. As the write high voltage application time is increased, the threshold voltage of the memory cell is increased. Three kinds of write threshold voltage control can be performed by such time control in a high voltage state, and further by level control of a high voltage applied to the word line. Whether 0V or 1V is applied to the bit line is determined by the logical value of the write control information latched by the sense latch circuit SL. For example, the latch data of the sense latch circuit SL is controlled so that writing is not selected (write blocking) when the logic value is “1” and writing is selected when the logic value is “0”. Whether the sense latch SL is set to “1” or “0” during the write operation is determined by the control unit CNT according to the corresponding write data on the buffer memories BMRY0 to BMRY3 according to the write threshold voltage state to be written. To do. At the time of block erasing, the selected word line is set to -16V, the non-selected word line is set to 0V, and the selected bit line is set to 2V. For reading out stored information, three kinds of voltages as word line selection levels to be applied to the word lines are set, and the three kinds of word line selection levels are sequentially changed, and read operation is performed three times at a maximum. The 2-bit storage information is determined based on the binary (1 bit) value read from the memory cell.
[0028]
The controller CNT controls erasing, writing, and reading with respect to the flash memory arrays FARY0 to FARY3.
[0029]
The buffer memories BMRY0 to BMRY3 are constituted by, for example, SRAM (Static Random Access Memory), and write data input to the external input / output terminals i / o0 to i / o7 in binary from the outside and the external input / output terminals i / o0 to i / o0. The binary read data to be output from i / o7 to the outside is temporarily stored. The buffer memories BMRY0 to BMRY3 are divided into two for each memory bank, and the buffer memories BMRY0 to BMRY3 for each memory bank have a minimum storage capacity equal to a write unit and a read unit in each corresponding flash memory array. For example, in the case of the flash memory 1, since the write information unit and the read information unit are one page (= 2K bytes), each of the buffer memories BMRY0 to BMRY3 as on-chip buffers has a storage capacity of 2K bytes. As described above, the corresponding buffer memories BMRY0 to BMRY3 are arranged one by one in the memory bank, and the buffer memories arranged in the same memory bank are preferentially used for the same flash memory array. Depending on the operation mode, a buffer memory that is not preferentially supported may be used. The control is performed by the control unit CNT according to a command and an address signal.
[0030]
Data input / output between the flash memory array and the buffer memory is performed in units of 8 bits. In the flash memory arrays FARY0 to FARY3, selection of the sense latch SL in units of 8 bits is performed by a sense latch selection circuit not shown. The buffer memories BMRY0 to BMRY3 are made accessible in units of 8 bits. The control unit CNT performs data transfer between the flash memory arrays FARY0 to FARY3 and the buffer memories BMRY0 to BMRY3 and access control to the buffer memories BMRY0 to BMRY3 based on externally applied commands and access address information.
[0031]
FIG. 2 illustrates details of the address, data, and command code transmission paths in the flash memory 1. The command code supplied to the external input / output terminals i / o0 to i / o7 is input to the control unit CNT.
[0032]
The external address information given to the external input / output terminals i / o0 to i / o7 is supplied to the address buffer (ABUF) 10. The address information input to the address buffer 10 includes page address information specifying the page address of the flash memory array in the entire memory banks BNK0 to BNK3, access start address information (buffer start column address information) of the buffer memory, and the like. The address information is latched in an address latch circuit (not shown). The address buffer has a flash address counter (FAC) 11 and a buffer address counter (BAC) 12. The flash address counter 11 is an address counter that generates an address signal for sequentially selecting sense latches for one page in byte units. The buffer address counter 12 is an address counter that presets buffer head column address information and generates an access address signal when sequentially accessing the buffer memory in units of 8 bits using the preset value as an initial value. The page address information and the output of the flash address counter 11 are supplied to the flash memory arrays FARY0 to FARY3. The output of the buffer address counter 12 is supplied to address buffers (buffer unit address buffer = BABUF) 13a to 13d of the buffer memories BMRY0 to BMRY3. From there, it is supplied to the buffer memories BMRY0 to BMRY3.
[0033]
Write data applied to the external input / output terminals i / o0 to i / o7 is applied to one buffer memory BMRYi (I = 0 to 3) of the buffer memories BMRY0 to BMRY3. Data read from the buffer memory BMRYi is transferred to the external input / output terminal i via the data buffers (buffer unit data buffer = BDBUF) 14a to 14d, the data multiplexer (MPX) 15, and the data buffer (DBUF) 16 of the corresponding buffer memory BMRYi. Output from / o0 to i / o7 to the outside.
[0034]
Data is input / output in units of 8 bits between the buffer memories BMRY to BMRY3 and the flash memory arrays FARY0 to FARY3.
[0035]
FIG. 3 illustrates a data transfer mode between the external input / output terminals i / o0 to i / o7 and the buffer memory BMRY (i = 0 to 3). In the read operation for the flash memory 1, the buffer memory BMRYi that temporarily holds the storage information of the flash memory array FARYi selected based on the page address information is interfaced with the external input / output terminals i / o0 to i / o7. Of the one buffer memory BMRYi selected based on the page address information, the left buffer memory BMRYi (L) is interfaced with the external input / output terminals i / o0 to i / o3, and based on the page address information and the like. Of the selected buffer memory BMRYi, the right buffer memory BMRYi (R) is interfaced with the external input / output terminals i / o4 to i / o7, and the stored information is read out to the outside. In the write operation to the flash memory 1, the write data given to the external input / output terminals i / o0 to i / o3 is the left buffer memory BMRYi among the one buffer memory BMRYi selected based on the page address information or the like. The write data temporarily held in (L) and applied to the external input / output terminals i / o4 to i / o7 is the right-side buffer memory BMRYi among the one buffer memory BMRYi selected based on the page address information or the like. (R) is temporarily held.
[0036]
FIG. 4 illustrates a data transfer form between the buffer memory BMRYi and the flash FARYi. In the access operation to the flash memory 1, in the write operation designating the memory bank BNKi, the write information temporarily held in the buffer memory BMRYi designated based on the page address information etc. is designated based on the page address information etc. Data is written to the flash memory array FARYi. In the access operation to the flash memory 1, in the read operation in which the memory bank BNKi is specified, the storage information from the flash memory array FARYi specified based on the page address information or the like is specified based on the page address information. Temporarily held in BMRYi.
[0037]
FIG. 5 illustrates an initialization control signal for the buffer memory BMRYi. The control circuit CNT inputs a clear command as one of external commands. The clear command has a clear command code “FEH” and instructs to clear all the buffer memories BMRY0 to BMRY3 at once. Although not particularly limited, here, setting all the stored information to the logical value “0” is referred to as “clear”. In the flash memory arrays FARY0 to FARY3, the write data having a logical value “0” is set to a write blocking logical value. By preparing a clear command for the buffer memories BMRY0 to BMRY3, writing (= additional writing) of an arbitrary small area in one page can be accelerated. When performing additional writing, if there is no clear command for the buffer memories BMRY0 to BMRY3, it is necessary to input dummy data (a pattern of logical value “0”) indicating that writing is prohibited in an area where writing is not performed. Then, it is necessary to change the clock of the write enable signal WEb by the writing unit. On the other hand, if there is a clear command for the buffer memories BMRY0 to BMRY3, dummy data indicating write prohibition is set on the buffer memories BMRY0 to BMRY3 when the buffer memories BMRY0 to BMRY3 are cleared. The write enable signal WEb may be clocked according to the data size.
[0038]
By receiving the clear command, the control circuit CNT receives the initialization clear signals MCSRAM <1> to MCSRAM <4> and the initialization write signal MWSRAM <1> as initialization control signals in synchronization with the change of the write enable signal WEb. ~ MWSRAM <4> are generated and supplied to predetermined buffer memories BMRY0 to BMRY3. The delay circuits DEL1 and DEL2 output initialization clear delay signals MCSRAM_D <2> and MCSRAM_D <4> by delaying the initialization clear signals MCSRAM <2> and MCSRAM <4>, for example, by 5 nanoseconds (5 ns). The initialization clear signal MCSRAM <1> and the initialization write signal MWSRAM <1> are supplied to the buffer memories MBRY0 (L) and BMRY1 (L). The initialization clear delay signal MCSRAM_D <2> and the initialization write signal MWSRAM <2> are supplied to the buffer memories MBRY0 (R) and BMRY1 (R). The initialization clear signal MCSRAM <3> and the initialization write signal MWSRAM <3> are supplied to the buffer memories MBRY2 (L) and BMRY3 (L). The initialization clear delay signal MCSRAM_D <4> and the initialization write signal MWSRAM <4> are supplied to the buffer memories MBRY2 (R) and BMRY3 (R).
[0039]
FIG. 6 illustrates change timings of the initialization clear signals MCSRAM <1> to MCSRAM <4> and the initialization write signals MWSRAM <1> to MWSRAM <4>. Although not particularly limited, the write enable signal WEb is changed with a period of 30 ns. The initialization clear signals MCSRAM <3> and MCSRAM <4> are changed with a half cycle delay of the write enable signal WEb with respect to the initialization clear signals MCSRAM <1> and MCSRAM <2>. The initialization write signals MWSRAM <1> and MWSRAM <2> are changed with a delay of one cycle of the write enable signal WEb with respect to the initialization clear signals MCSRAM <1> and MCSRAM <2>. The initialization write signals MWSRAM <3> and MWSRAM <4> are changed with a delay of one cycle of the write enable signal WEb with respect to the initialization clear signals MCSRAM <3> and MCSRAM <4>.
[0040]
FIG. 7 illustrates a part of the buffer memory BMRY0. The static memory cell 20 cross-couples the inputs and outputs of a CMOS inverter comprising a p-channel MOS transistor Q1 and an n-channel MOS transistor Q2 and a CMOS inverter comprising a p-channel MOS transistor Q3 and an n-channel MOS transistor Q4. One storage node SR2 is connected to the bit line BLB via an n-channel type select MOS transistor Q5, and the other storage node SR1 is connected to the bit line BLT via an n-channel type select MOS transistor Q6. Connected to. Selection terminals of the selection MOS transistors Q5 and Q6 are connected to the word line WL. Actually, a large number of memory cells are arranged in a matrix in the XY direction, the selection terminals of the memory cells in the same row are commonly connected to the corresponding word lines, and the data input / output terminals of the memory cells arranged in the same column are Commonly connected to the corresponding complementary bit lines. Although not shown, one end of the complementary bit line is made conductive to a complementary common data line via a Y selection switch circuit (column selection switch circuit), and the complementary common data line is driven to be written by a write amplifier. The data read to the complementary common data line is sense amplified by the read amplifier.
[0041]
The other ends of the complementary bit lines BLB and BLT are connected to the memory power supply terminal VSR of the SRAM via p-channel type load MOS transistors Q7 and Q8. The load MOS transistors Q7 and Q8 are switch-controllable by control signals WEQB1 and WEQB2. The complementary bit lines BLB and BLT can be equalized by a p-channel type equalize MOS transistor Q9 that is switch-controlled by a control signal WEQB0. One bit line BTB is connected to an n-channel discharge MOS transistor Q10 that is switch-controlled by a control signal WEQ1. Selection of the word line WL is performed by an address decoder logic circuit 22 to which the corresponding internal complementary address signal 21 and the initialization clear signal MCSRAM <1> are input. The initialization clear signal MCSRAM <1> is input in common to the address decoder logic circuits 22 of all the word lines WL, and the internal complementary address signal 21 is individual for each address decoder logic circuit 22. In the example of FIG. 7, the address decoder logic circuit 22 is composed of NAND gates NAND1 and NAND2 and an inverter IV. When all the bits of the corresponding internal complementary address signal 21 are at high level, or the initialization clear signal MCSRAM <1> is at high level. The corresponding word line WL is driven to the selected level. When the initialization clear signal MCSRAM <1> is set to the high level, all the word lines WL of the buffer memory BMRY0 (L) are driven to the selection level.
[0042]
The timing control circuit 23 generates the control signals WEQ1, WEQB0, WEQB1, and WEQB2 based on the initialization clear signal MCSRAM <1> and the initialization write signal MWSRAM <1>. Based on the initialization clear signal MCSRAM <1>, the power supply control circuit 24 selectively controls the bit line load and the power supply terminal VSR of the static memory cell 20 to the power supply voltage VCC of the buffer memory or the ground voltage VSS of the circuit.
[0043]
Although not shown, the other buffer memories BMRY1 (L) to BMRY3 (L) and BMRY0 (R) to BMRY3 (R) are similarly configured.
[0044]
FIG. 8 illustrates the operation timing of the circuit of FIG. 7 when the initialization command is instructed to the flash memory 1 by the initialization command. When the initialization clear signal MCSRAM is changed to the high level at time t0, the word lines WL of the buffer memory BMRY0 are changed to the high level which is the selected level in synchronism with this, and the power supply terminal VSR is turned The voltage is changed from VCC to the ground voltage VSS, and the control signal WEQ1 is changed to a high level. At this time, the control signals WEQB0, WEQB1, and WEQB2 remain at a high level. When the initialization operation is performed according to the initialization command, all the column switches of the buffer memory are in a non-selected state. In this state, when the supply of the operating power supply VCC to the power supply terminal VSR is cut off, the pair of storage nodes SR1 and SR2 (gate parasitic capacitances of MOS transistors) of the static memory cell 20 try to hold charge information corresponding to the stored information. To do. Since storage node SR1 is in a floating state, it tries to hold its charge information. On the other hand, the storage node SR2 is discharged to the circuit ground potential VSS via the bit line BLB. Thereafter, when the signal MWSRAM <1> is changed to a high level at time t1, the discharge MOS transistor Q10 is cut off and one load MOS transistor Q8 is turned on, and the power supply voltage VCC is supplied to the power supply terminal VSR. Is started, and the storage node SR1 is charged toward the high level. As a result, the static memory cell 20 holds a prescribed initial value. At time t2, MCSRAM <1> and MWSRAM <1> are set to the low level, and the initialization for the buffer memory is completed.
[0045]
The initialization operation of the flash memory cell 20 based on FIG. 7 can be grasped as follows. That is, in the initialization operation, the supply of the operating power supply VCC to the power supply terminal VSR is cut off to reduce the accumulated charge in one storage node SR2, and then the initial value potential and the power supply terminal VSR are applied to both storage nodes SR1 and SR2. It can be grasped as an operation of supplying the operation power supply VCC.
[0046]
For the other buffer memory, the configuration and operation for initialization by the clear command are the same as the buffer memory of FIG. However, as is apparent from the timing of FIG. 6, the initialization operation is performed in a time division manner between the buffer memories. According to FIGS. 6 and 7, the order of BMRY0 (L) and BMRY1 (L), BMRY0 (R) and BMRY1 (R), BMRY2 (L) and BMRY3 (L), BMRY2 (R) and BMRY3 (R) It is said.
[0047]
FIG. 9 illustrates a configuration in which the initialization operation is performed in the buffer memory by time division. FIG. 9 illustrates the case of the buffer memories BMRY0 (L) and BMRY1 (L). The buffer memories BMRY0 (L) and BMRY1 (L) are divided into two memory mats MATU and MATL, respectively. The initialization clear signals MCSRAM <1> of the buffer memories BMRY0 (L), BMRY1 (L) are sequentially delayed by three serial delay stages DL1, DL2, DL3, and the initialization clear delay signals MCSRAM <1> _D1, MCSRAM <1> _D2, MCSRAM <1> _D3 are generated. The signal waveform is illustrated in FIG. For the initialization write signal MWSRAM <1>, the initialization data is not written in a time division manner, but the initialization data may be written in a time division manner for each memory mat.
[0048]
Signals MCSRAM <1> and MWSRAM <1> are supplied to the memory mat MATU of the buffer memory BMRY0 (L). Signals MCSRAM <1> _D1 and MWSRAM <1> are supplied to the memory mat MATL of the buffer memory BMRY0 (L). Signals MCSRAM <1> _D2 and MWSRAM <1> are supplied to the memory mat MATU of the buffer memory BMRY1 (L). Signals MCSRAM <1> _D3 and MWSRAM <1> are supplied to the memory mat MATL of the buffer memory BMRY1 (L).
[0049]
Other buffer memories BMRY0 (R), BMRY1 (R), BMRY2 (L), BMRY3 (L), BMRY2 (R), and BMRY3 (R) are initialized by time division in the buffer memory in the same manner as described above. Can be performed.
[0050]
According to the microcomputer described above, the following operational effects are obtained.
[0051]
In the initialization operation, even if one storage node SR2 is discharged to the ground potential in a state where the supply of operation power to the static memory cell 20 is cut off, no large current flows unnecessarily from the power supply terminal VSR side. Even if the supply of the operating power from the power supply terminal VSR is resumed in this state and the other storage node SR1 is charged from the power supply terminal VSR toward the power supply voltage, the complementary states of the storage nodes SR1 and SR2 are already determined. The static memory cell 20 is initialized with almost no transient response current flowing. As a result, the initialization operation of the buffer memory can be speeded up, and the current flowing in the initialization operation can be reduced.
[0052]
Since the above initialization operation can be instructed by an external command such as a clear command, the flash memory is used to erase unnecessary data before partial writing to the flash memory array or before using the buffer memory as a data cache. The buffer memory can be initialized appropriately as required for the access operation to the memory 1.
[0053]
Since the information stored in the buffer memories BMRY0 to BMRY3 by the initialization operation is a logical value for preventing writing in the flash memory arrays FARY0 to FARY3, it is suitable for partial writing to the flash memory arrays FARY0 to FARY3. This improvement in the efficiency of partial write processing becomes apparent when the write unit (2048 bytes) in the flash memory arrays FARY0 to FARY3 is larger than the data input / output unit (8 bits) of the buffer memories BMRY0 to BMRY3. . Further, it is most efficient that the initialization operation is a batch initialization operation for the buffer memories BMRY0 to BMRY3.
[0054]
By performing the initialization operation in a time-sharing manner, the peak current can be reduced when the buffer memories BMRY0 to BMRY3 are initialized.
[0055]
When the buffer memories BMRY0 to BMRY3 are divided into a plurality of memory mats MATU and MATL, the initialization peak current can be further suppressed by performing the initialization operation in a time division manner between the memory mats.
[0056]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0057]
For example, the buffer memory employs a serial transfer system in which page-unit data is serially transferred using an SRAM that performs byte-unit access, but the access unit is not limited to bytes, and can be changed as appropriate in word units. It is. Serial clocks for writing to and reading from the buffer memory are prepared separately for writing (WEb) and reading (REb), but buffer access control commands may be prepared separately. In that case, one serial clock can be shared. The size of the buffer memory may be n pages or more (n is a natural number larger than 1) per bank. Further, the number of mat divisions of the buffer memory is not limited to two memory mats and can be changed as appropriate. Similarly, the number of bank divisions is not limited to four divisions and can be changed as appropriate.
[0058]
The present invention can be applied not only to a multi-value flash memory such as a 4-value but also to a binary flash memory. In addition, the storage format of the multilevel flash memory is not limited to the case where the threshold voltage is sequentially changed according to the value of the stored information. You may employ | adopt the memory cell structure using the electric charge trap film | membrane (silicon nitride film) to perform. Further, other storage formats such as a high dielectric memory cell can be employed as the nonvolatile memory cell.
[0059]
The present invention can be widely applied to a semiconductor integrated circuit such as a microcomputer or a system LSI having a flash memory chip having an on-chip data buffer RAM and a flash memory having a data buffer RAM as an on-chip nonvolatile memory.
[0060]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0061]
In the initialization operation of the data buffer RAM, even if one storage node is forced to the first polarity with the supply of operation power to the static memory cell cut off, no large current flows unnecessarily from the power supply side. Even if the supply of the operating power is restarted in this state and the other storage node is forced to the second polarity, the complementary state of the storage node is already determined, so that the transient memory current hardly flows and the static memory cell It is initialized. As a result, the initialization operation of the data buffer RAM can be speeded up, and the current flowing in the initialization operation can be kept small.
[0062]
Since the initialization operation is instructed by an external command, the access operation to the non-volatile storage device is performed, for example, when unnecessary data is cleared before partial writing to the non-volatile memory unit or before the data buffer RAM is used as a data cache. If necessary, the data buffer RAM can be initialized appropriately.
[0063]
By performing the initialization operation in a time-sharing manner, it is easy to reduce the peak current when initializing the data buffer RAM of the nonvolatile memory unit.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a planar layout configuration of a flash memory which is an example of a semiconductor memory device according to the present invention.
FIG. 2 is a block diagram illustrating details of an address, data, and command code transmission path in a flash memory;
FIG. 3 is an explanatory diagram illustrating a data transfer form between an external input / output terminal and a buffer memory;
FIG. 4 is an explanatory diagram illustrating a data transfer mode between a buffer memory and a flash memory array;
FIG. 5 is a block diagram illustrating a configuration of an initialization control signal of a buffer memory.
FIG. 6 is a timing diagram illustrating the timing of changing the initialization clear signal and the initialization write signal.
FIG. 7 is a circuit diagram illustrating a part of the buffer memory in detail.
8 is a timing chart illustrating the operation timing of the circuit of FIG. 7 when an initialization operation is instructed by an initialization command.
FIG. 9 is a block diagram illustrating a configuration in which an initialization operation is performed in a buffer memory in a time-sharing manner.
FIG. 10 is a timing diagram illustrating signal waveforms of an initialization clear delay signal and an initialization write delay signal.
[Explanation of symbols]
1 Flash memory
BNK0 to BNK3 memory bank
FARY0 to FARY3 Flash memory array
BMRY0-BMRY3 buffer memory
CNT control circuit
MCSRAM <1> to MCSRAM <4> Initialization clear signal
MWSRAM <1> to MWSRAM <4> Initialization write signal
VCC power supply voltage
VSR power supply terminal
VSS ground voltage
20 Static memory cells
Q7, Q8 Load MOS transistor
Q10 Discharge MOS transistor
22 Address decoder logic circuit
MATL, MATU Memory mat
MCSRAM <1> _D1 to MCSRAM <1> _D3 Initialization clear delay signal
MWSRAM <1> _D1 to MWSRAM <1> _D3 Initialization write delay signal

Claims (9)

An erasable and writable nonvolatile memory unit, a data buffer RAM of the nonvolatile memory unit, and a control unit,
The data buffer RAM has a plurality of static memory cells. One storage node is forced to the first polarity while the supply of operating power to the static memory cells is cut off, and the other memory is stored with the supply of operating power resumed. An initialization operation is allowed to force the node to a second polarity opposite to the first polarity;
The nonvolatile memory device according to claim 1, wherein the control unit instructs an initialization operation for the data buffer RAM in response to an external command.   2. The nonvolatile memory device according to claim 1, wherein information stored in the data buffer RAM by the initialization operation has a logical value for preventing writing in the nonvolatile memory unit.   2. The nonvolatile memory device according to claim 1, wherein a write unit in the nonvolatile memory unit is a multiple of a data input / output unit of the data buffer RAM.   2. The nonvolatile memory device according to claim 1, wherein the initialization operation is a batch initialization operation for the data buffer RAM.   The data input / output terminal of the static memory cell is connected to a complementary bit line, a load transistor capable of switch control is connected to the complementary bit line, and one of the complementary bit lines is complementary to the load transistor of the one bit line. 5. The non-volatile memory device according to claim 4, wherein a discharge controllable discharge transistor is connected to the on-state, and the on-state discharge transistor forces one storage node of the static memory cell to a first polarity.   6. The nonvolatile memory device according to claim 5, wherein the operation of forcing the other storage node of the static memory cell to the second polarity is performed by turning on the other load transistor of the complementary bit line. A plurality of memory banks and a control unit;
The memory bank includes an erasable and writable nonvolatile memory unit, and a data buffer RAM of the nonvolatile memory unit,
The data buffer RAM has a plurality of static memory cells. One storage node is forced to the first polarity while the supply of operating power to the static memory cells is cut off, and the other memory is stored with the supply of operating power resumed. An initialization operation is allowed to force the node to a second polarity opposite to the first polarity;
The nonvolatile memory device, wherein the control unit instructs the plurality of memory banks to perform the initialization operation in a time-sharing manner.   8. The nonvolatile memory device according to claim 7, wherein the information stored in the data buffer RAM by the initialization operation has a logical value for preventing writing in the nonvolatile memory unit.   8. The nonvolatile memory device according to claim 7, wherein the data buffer RAM has a plurality of memory mats, and the initialization operation is performed in a time division manner in the plurality of memory mats.

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