KR102483906B1 - Nas memory cell combined with nand flash memory and static random access memory and nas memory array using the same - Google Patents

Abstract

The present invention relates to a NAS memory cell that is fused with a NAND flash memory and an SRAM and a NAS memory array using the same, wherein an NST unit is connected to the first data node of an SRAM cell together with a NAND flash string, thereby having an effect of transmitting the data from the NAND flash string to the SRAM cell or vice versa for all selected rows at once without going through any intermediate process including an I/O buffer.

Description

NAS memory cell in which NAND flash memory and SRAM are fused and NAS memory array using the same

The present invention relates to a semiconductor memory device, and more particularly, to a NAS memory cell in which a NAND flash memory and an SRAM are fused in a single chip and a NAS memory array using the same.

A NAS memory cell is a unit of a semiconductor memory array, which means that NAND flash memory and SRAM (Static Random Access Memory) are fused and integrated within a single chip, and the name is derived from 'NA' in NAND and 'S' in SRAM.

Modern computers are designed based on the von Neumann structure in which a processing unit and a memory unit are separated. The processing unit performs a role such as logic operation and command transmission, and the memory unit performs a role such as data storage. Computer operation is achieved by exchanging data between these two units organically. For this reason, in order to improve the performance of the entire system, it is necessary to improve the performance of both units, not just one of the units. In a current computer system, a bottleneck phenomenon in which the performance of the entire system is limited because the operating speed of a memory unit is slow compared to the operating speed of a processing unit is emerging. To improve this, it is necessary to improve the overall performance of the memory system.

As one of the methods for improving the performance of the memory system, there is a method of increasing data transmission speed between several memories in the memory system. Within a memory system, there are various types of memory, each with different characteristics and uses. For example, NAND Flash is a non-volatile memory with excellent density and is used as a solid state drive (SSD). On the other hand, SRAM is a volatile memory and is used as a CPU cache memory and buffer because of its high reading and writing speed. The memory system efficiently operates the system by moving data from memory to memory according to the situation. When data needs to be stored for a long time, it is stored in non-volatile memory such as NAND Flash, and when data needs to be continuously exchanged with the CPU, it is moved to memory with fast data access speed, such as SRAM or DRAM (Dynamic Random Access Memory). is the expression used Such data transmission occurs very actively during actual memory unit operation, and the operation speed of the entire system can be effectively increased by increasing the data transmission speed.

In a general memory system, NAND Flash and SRAM exist in the form of independent chips, and data transmission is performed through a bus. In this structure, when data is transmitted, data must pass through the I/O buffer of each chip, resulting in latency and additional power consumption. be limited In particular, when a large amount of data is transmitted, each memory cuts the data in a certain unit and transmits the data, which adds to the aforementioned inefficiency in terms of speed and power. 1 shows a data transfer flow when data stored from the m-th row to the n-th row of an SRAM array is transferred to a NAND Flash in a conventional general memory system. First, the data of the mth row of the SRAM array is read and stored in the I/O buffer (①). Next, it is stored in the NAND flash I/O buffer through the data bus (②), and finally, the data is stored in the NAND flash (③). Reading or writing data from each memory can only be performed in WL units, so the above process must be repeated continuously for all rows from the mth row to the nth row.

In addition, since SRAM is a volatile memory, data is lost when the power supply is disconnected due to a power outage, etc. To prevent this, a technology for connecting a non-volatile memory device to one or both sides of the storage unit is disclosed in U.S. Patent Nos. 6,414,873 and 8,018,768. call is disclosed. The former connects two non-volatile memory devices to both sides of the SRAM storage unit, and the latter connects one non-volatile memory device to one side of the SRAM storage unit and an inverter to the other side. Since both of these technologies are for storage and recall of data when power is disconnected from SRAM, it is difficult to operate as NAND Flash by connecting a plurality of non-volatile memories. Therefore, the NAND Flash must be configured through a separate chip, and in this case, as described above, there is a problem in that data transmission is inevitable to the SRAM through the bus.

In order to solve the problems of the prior art, the present invention provides a NAS memory cell in which NAND flash memory and SRAM are fused to enable data transmission within a single chip without going through a bus, a NAS memory array using the same, and an operating method related thereto. want to provide

In order to achieve the above object, a NAS memory cell according to the present invention includes a NAND flash string in which an upper select transistor, a plurality of inactive memory elements, and a lower select transistor are connected in series; an SRAM cell having a volatile storage unit having a first data node connected to a lower end of the lower select transistor and a second data node in which an electrical signal of the first data node is inverted; and an NST unit connected to the first data node and a transmission control line (NSE) to transmit data from the NAND Flash string to the SRAM cell.

The volatile storage unit is composed of two inverters, the output of one inverter is connected to the input of the other inverter, the input of one inverter is connected to the output of the other inverter, the other of the NAS memory cell according to the present invention to be characterized

The volatile storage unit is composed of two storage transistors and two resistors, a first storage transistor between the first data node and the ground, and a first resistor between the first data node and a supply voltage, respectively. A second storage transistor is connected between the second data node and the ground, and a second resistor is connected between the second data node and the supply voltage terminal, and a gate of the first storage transistor is connected to the first storage transistor. Another feature of the NAS memory cell according to the present invention is that it is connected to two data nodes, and the gate of the second storage transistor is connected to the first data node.

The NST unit is composed of first and second transistors connected in series to the first data node, a gate of the first transistor is connected to the transfer control line, and a gate of the second transistor is connected to the NAND Flash string. a first access transistor coupled between the last inactive memory element and the low select transistor, the SRAM cell having a first access transistor coupled between the first data node and the SRAM bit line and between the second data node and the SRAM inverting bit line It further includes a connected second access transistor, wherein the gate of the first access transistor and the gate of the second access transistor are connected to an SRAM word line, an upper end of the upper select transistor is a Flash bit line, and the upper select transistor The gate of the NAS memory cell according to the present invention is connected to an upper control line (SSL), each gate of the plurality of inactive memory elements is connected to a plurality of word lines, and the gate of the lower selection transistor is connected to a lower control line (GSL), respectively. with different characteristics.

The NAS memory array according to the present invention is characterized by being configured by arranging the above-described NAS memory cells in a matrix form (M x N) with M rows and N columns.

The NAS memory cells arranged in M rows connect the upper control line SSL, the plurality of word lines, the transmission control line NSE, the lower control line GSL, and the SRAM word line to each other in each row. Another feature of the NAS memory array according to the present invention is that the NAS memory cells arranged in N columns share the flash bit line, the SRAM bit line, and the SRAM inversion bit line for each column.

The NAS memory cells arranged in the M rows are independently controlled for each row by a NAND Flash word line decoder and an SRAM word line decoder so that data of two or more rows can be simultaneously transmitted. to be characterized

A method of operating a NAS memory cell according to an embodiment of the present invention is characterized in that the NAS memory cell is used as a NAND flash memory by applying V _SS to the transmission control line (NSE).

A method of operating a NAS memory cell according to another embodiment of the present invention is characterized in that the NAS memory cell is used as an SRAM cell by applying V _SS to the transmission control line (NSE) and the lower control line (GSL), respectively. .

A method of operating a NAS memory cell according to another embodiment of the present invention includes a first step of making the first data node V _SS ; a second step of making the output node V _SS ; a third step of making the first data node equal to V _DD1 ; and a fourth step of turning on the first transistor through the transfer control line NSE to transmit the data stored in the NAND Flash string to the SRAM cell.

According to another embodiment of the present invention, a method of operating a NAS memory cell turns off the first transistor and the upper select transistor with the transfer control line NSE and the upper control line SSL, respectively, Transmitting data of the first data node of the SRAM cell to the NAND flash string by a write operation of the plurality of inactive memory devices after turning on the lower selection transistor through the lower control line (GSL). to be characterized

In the method of operating a NAS memory array according to an embodiment of the present invention, one or more rows are selected from among the M rows in the NAND Flash word line decoder, and NAS memory cells are arranged in each row selected as the one or more rows. A first step of making the first data node V _SS , respectively; a second step of making the output node V _SS ; a third step of making the first data node equal to V _DD1 ; and a fourth step of turning on the first transistor through the transfer control line (NSE) to transfer the data stored in the NAND Flash string of the NAS memory cells disposed in each selected row to the SRAM cell once. It is characterized by transmission to.

In the method of operating a NAS memory array according to another embodiment of the present invention, one or more rows are selected from among the M rows in the NAND Flash word line decoder, and NAS memory cells are disposed in each row selected as the one or more rows. The control signal of each row of s turns off the first transistor and the upper selection transistor through the transfer control line NSE and the upper control line SSL, respectively, and the lower control line GSL After turning on the lower selection transistor, data stored in the first data node of the SRAM cell of the NAS memory cells arranged in each row is converted to a NAND Flash string by a write operation of the plurality of inactive memory elements. It is characterized by transmission to.

In the present invention, the NST unit is connected to the first data node of the SRAM cell along with the NAND Flash string, and as shown in FIG. There is an effect that data can be transferred (①) from the string to the SRAM cell or vice versa.

1 is a block diagram showing the configuration of a conventional memory system.
2 is a block diagram showing the configuration of a NAS memory system according to an embodiment of the present invention.
3 is a circuit diagram showing the configuration of a NAS memory cell according to an embodiment of the present invention.
4 is a timing diagram of an SRAM mode write operation of a NAS memory cell according to an embodiment of the present invention.
5 is a timing diagram of an SRAM mode read operation of a NAS memory cell according to an embodiment of the present invention.
6 is a timing diagram of a NAND Flash mode write operation of a NAS memory cell according to an embodiment of the present invention.
7 is a timing diagram of a NAND Flash mode read operation of a NAS memory cell according to an embodiment of the present invention.
8 is a SNT mode operation timing diagram of a NAS memory cell according to an embodiment of the present invention.
9 is an NST mode operation timing diagram of a NAS memory cell according to an embodiment of the present invention.
10 is a block diagram showing the configuration of a NAS memory array and system according to an embodiment of the present invention.
11 is a timing diagram of an SRAM mode read operation of a NAS memory array according to an embodiment of the present invention.
12 is a SNT mode operation timing diagram of a NAS memory array according to an embodiment of the present invention.
13 is an NST mode operation timing diagram of a NAS memory array according to an embodiment of the present invention.
14 is a simulation result diagram of an SNT mode operation of a NAS memory cell according to an embodiment of the present invention.
15 is a diagram showing a simulation result of an NST mode operation of a NAS memory cell according to an embodiment of the present invention.
16 is a circuit diagram showing the configuration of a NAS memory cell having a V _DD type NST unit according to another embodiment of the present invention.
17 is a circuit diagram showing the configuration of a NAS memory cell having an NST unit connected to a transfer control line (NSE) along with a gate in another embodiment of the present invention.
18 is a circuit diagram showing the configuration of a NAS memory cell having a 4T SRAM cell according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

)를 갖는 휘발성 저장 유닛을 갖는 SRAM 셀(20); 및 상기 제 1 데이터 노드(Q)와 전송 제어 라인(NSE)에 연결되어 상기 NAND Flash 스트링(10)에서 상기 SRAM 셀(20)로 데이터를 전송하는 NST 유닛(30)을 포함한다.As illustrated in FIG. 3 , a NAS memory cell according to an embodiment of the present invention includes an upper selection transistor N5, a plurality of inactive memory elements NV1, NV2, ..., NVn, and a lower selection transistor N6. ) is serially connected NAND Flash string (10); A first data node Q connected to the lower end of the lower selection transistor N6 and a second data node in which an electrical signal of the first data node is inverted (

) SRAM cell 20 having a volatile storage unit having; and an NST unit 30 connected to the first data node Q and a transmission control line NSE to transmit data from the NAND Flash string 10 to the SRAM cell 20 .

Here, since the NAS memory cell of the present invention is named after 'NA' of NAND and 'S' of SRAM, NAND flash memory and SRAM (Static Random Access Memory) are fused and integrated in a single chip as a unit of a memory array. If it is used, it should be regarded as corresponding to this.

According to a specific embodiment of the NAS memory cell, in the NAND Flash string 10 of FIG. 3, a plurality of inactive memory elements (NV1, NV2, ..., NVn) are freely configured from 1 to 128 or more can do. Here, since the inactive memory device is enough to function as an inactive memory, a flash memory device is not only a floating-gate MOSFET and charge trap flash (CTF), but also a single-poly embedded flash and tunnel FET (TFET) composed of several transistors. , Ferroelectric FET (FeFET), or other commercially available or researched memory devices.

) 사이에 구비되어 전원 인가시 앞의 두 노드의 전기적 신호가 반전된 상태로 데이터를 저장할 수 있게 하는 것이면 모두 이에 해당된다. 일 실시예로, 도 3과 같이, 두 개의 인버터(P1과 N1, P2과 N2)로 구성되되, 어느 하나의 인버터(P1과 N1)의 출력은 다른 인버터(P2과 N2)의 입력과 연결되고, 어느 하나의 인버터(P1과 N1)의 입력은 다른 인버터(P2과 N2)의 출력과 연결될 수 있다.The volatile storage unit of the SRAM cell 20 includes a first data node (Q) and a second data node (

) to store data in a state in which the electrical signals of the preceding two nodes are inverted when power is applied. In one embodiment, as shown in FIG. 3, it is composed of two inverters (P1 and N1, P2 and N2), and the output of one inverter (P1 and N1) is connected to the input of the other inverter (P2 and N2) , the input of one of the inverters P1 and N1 may be connected to the output of the other inverters P2 and N2.

)와 접지 사이에는 제 2 저장용 트랜지스터(N2)가, 상기 제 2 데이터 노드(

)와 상기 공급전압단(V_DD2) 사이에는 제 2 저항(R2)이 각각 연결되고, 상기 제 1 저장용 트랜지스터(N1)의 게이트는 상기 제 2 데이터 노드(

)에 연결되고, 상기 제 2 저장용 트랜지스터(N2)의 게이트는 상기 제 1 데이터 노드(Q)에 연결될 수 있다.As another embodiment of the volatile storage unit, as shown in FIG. 18, it is composed of two storage transistors (N1 and N2) and two resistors (R1 and R2), between the first data node (Q) and the ground A first storage transistor (N1), a first resistor (R1) is connected between the first data node (Q) and the supply voltage terminal (V _DD2 ), respectively, the second data node (

) And a second storage transistor N2 between the ground, the second data node (

) and the supply voltage terminal (V _DD2 ), a second resistor (R2) is connected, respectively, and the gate of the first storage transistor (N1) is connected to the second data node (

), and a gate of the second storage transistor N2 may be connected to the first data node Q.

The NST unit 30 is an abbreviation of NAND Flash to SRAM Transfer Unit, and is connected to the first data node (Q) and the transfer control line (NSE), from the NAND Flash string 10 to the SRAM cell 20 If it is equipped to transmit data, it corresponds to this.

Referring to FIG. 3, the NST unit 30 is basically composed of first and second transistors N7 and N8 connected in series to the first data node Q, and the first transistor N7 A gate is connected to the transfer control line NSE, and the gate of the second transistor N8 is between the last inactive memory device NVn at the lower end of the NAND Flash string 10 and the lower selection transistor N6. It may be provided as being connected to the output node (G) of.

Here, the lower end of the second transistor N8 is connected to the first data node Q, and the embodiment of the NST unit 30 may be different depending on the connection of the upper end of the first transistor N7. .

First, as shown in FIG. 3 , an upper end of the first transistor N7 may be grounded (GND type NST unit). In another embodiment, as shown in FIG. 16, the upper end of the first transistor N7 is connected to the supply voltage terminal V _DD2 ( V _DD type NST unit), or as shown in FIG. 17, the transfer control line NSE (Diode-type NST unit).

The V _DD type NST unit has the advantage of simplifying operation since there is no need to initially set the voltage of the first data node (Q) to V _SS and then change it back to V _DD2 during a NAND Flash to SRAM Transfer (NST) operation. However, compared to the GND-type NST unit, the power to change the first data node (Q) from V _SS to V _DD2 is weak, resulting in latency and the need to set the channel width of the second transistor (N8) large.

Meanwhile, the diode-type NST unit can better change the first data node (Q) voltage compared to the V _DD2 -type NST unit when a voltage greater than V _DD2 is applied to the transmission control line (NSE).

)와 SRAM 반전 비트 라인(

, 46) 사이에 연결된 제 2 액세스 트랜지스터(N4)를 더 포함하여 구성되고, 상기 제 1 액세스 트랜지스터(N3)의 게이트와 상기 제 2 액세스 트랜지스터(N4)의 게이트는 SRAM 워드 라인(WL_SRAM, 60)에 연결된다.Referring to FIG. 3 , the SRAM cell 20 includes a first access transistor N3 connected between the first data node Q and an SRAM bit line BL _SRAM 42 and the second data node (

) and the SRAM inverted bit line (

, 46), and the gate of the first access transistor N3 and the gate of the second access transistor N4 are connected to the SRAM word line (WL _SRAM , 60 ) is connected to

In addition, the upper end of the upper select transistor N5 is a flash bit line (BL _Flash , 44), the gate of the upper select transistor (N5) is an upper control line (SSL, 52), and the plurality of inactive memory elements (NV1, Each gate of NV2, ..., NVn is a plurality of word lines (WL _Flash,0 , WL _Flash,1 , ..., WL _Flash,n-1 ; 54), the gate of the lower selection transistor N6 are respectively connected to the lower control line (GSL, 56)

Referring to FIG. 10, the NAS memory array 100 according to an embodiment of the present invention is a matrix (M x N) with M rows and N columns using the above-described NAS memory cells as one unit 110. placed and configured. Here, M and N are 1 or natural numbers greater than 1 (provided that they do not become 1 at the same time).

, 46)을 서로 공유할 수 있다.Referring to FIGS. 3 and 10 together, the NAS memory cells arranged in M rows have the upper control line (SSL, 52) and the plurality of word lines (WL _Flash,0 , WL _Flash,1 , ..., WL _Flash,n−1 ; 54), the transmission control line (NSE, 70), the lower control line (GSL, 56), and the SRAM word line (WL _SRAM , 60) may be shared with each other. . Meanwhile, in the NAS memory cells arranged in N columns, the Flash bit line (BL _Flash , 44), the SRAM bit line (BL _SRAM , 42) and the SRAM inverted bit line (

, 46) can be shared with each other.

The NAS memory cells arranged in the M rows may be independently controlled for each row by the NAND Flash word line decoder 210 and the SRAM word line decoder 310 so that data of two or more rows can be simultaneously transmitted.

As shown in FIG. 10, the NAS memory array 100 is provided with NAND Peripheral Circuits 200 and SRAM Peripheral Circuits 300 for operation.

The NAND Peripheral Circuits 200 are provided with a NAND Flash word line decoder 210 on the left side and a NAND Flash column decoder 220 and a NAND Flash Page Buffer 230 on the top of the NAS memory array 100, It controls the voltage applied to each BL _Flash and is involved in performing the NAND flash mode read operation.

의 전압을 조절하고, SRAM 셀(20)에 저장된 정보를 읽기 동작 등을 수행할 때 관여한다.The SRAM Peripheral Circuits 300 include the SRAM word line decoder 310 provided on the right side and the Precharge Circuit 320 for driving the SRAM cell 20 at the bottom of the NAS memory array 100, Columm Mux 330, Write Circuit (340) and Sense _Amplifier (350) are provided to

It regulates the voltage of the SRAM cell 20 and participates in reading the information stored in the cell 20.

Referring to FIG. 10, when data comes in from the outside, it is temporarily stored in the upper NAND Flash I/O Buffers (400) or the lower SRAM I/O Buffers (500), then the command is Command Register (410) and the address is With the Address Register/Counter 430, data to be stored in the NAS memory array 100 is transferred to the NAND Peripheral Circuits 200 or SRAM Peripheral Circuits 300. Commands entered into the Command Register 410 are transferred to the Command Interface Logic circuit 420, and the Command Interface Logic circuit 420 sends the command to a location required to implement the command. Address data input to the address register/counter 430 is transferred to each decoder, and the decoder selects a location of a memory cell in the array 100 to read or write data based on the received data. Therefore, data input to be stored in the array 100 is transferred to the I/O buffers 400 and 500 from the outside and transferred to the array 100 through the I/O bus. Conversely, the data of the array 100 read through the read operation is transferred to the I/O buffers 400 and 500 through the I/O bus and then output to the outside.

Next, with reference to FIGS. 4 to 9, the operating method of the NAS memory cell of the present invention will be described.

<SRAM mode>

4 is a timing diagram of an SRAM mode write operation of a NAS memory cell according to an embodiment of the present invention. First, by applying V _SS (eg, 0V) to the GSL 56 and the NSE 70, respectively, the NAND Flash string 10 and the SRAM cell 20 and the NST unit 30 and the SRAM cell 20 are connected. Disconnect the electrical connection. Subsequent operations are the same as write operations of the general SRAM cell 20 .

(46) 을 각각 제 1 데이터 노드(Q) 및 제 2 데이터 노드(

)에 연결되게 해준다. 동시에 저장하고자 하는 정보에 따라 BL_SRAM(42)과

(46) 중 하나의 전압을 V _DD2에서 V _SS로 내린다. 마지막으로 WL_SRAM(60)의 전압을 V _SS로 내려 제 1 액세스 트랜지스터(N3)와 제 2 액세스 트랜지스터(N4)를 꺼주면 SRAM 셀(20)에 정보가 저장된다. 이후 다음 동작을 수행할 수 있도록 BL Pair_SRAM(42, 46)를 다시 V _DD2로 precharge 해놓는다.The write operation of the SRAM cell 20 is performed by precharging the BL Pair _SRAM (42, 46) with V _DD2 (e.g., about 1V. However, it can be changed in various ways depending on the applied system or application field). Raise the voltage of _SRAM (60) to V _DD2 to connect BL _SRAM (42) and

(46) to the first data node (Q) and the second data node (

) to connect to. Depending on the information to be stored at the same time, BL _SRAM (42) and

Step the voltage of one of (46) from V _DD2 to V _SS . Finally, when the voltage of the WL _SRAM 60 is lowered to V _SS and the first access transistor N3 and the second access transistor N4 are turned off, information is stored in the SRAM cell 20 . After that, the BL Pair _SRAM (42, 46) is precharged again with V _DD2 so that the next operation can be performed.

5 is a timing diagram of an SRAM mode read operation of a NAS memory cell according to an embodiment of the present invention. Similar to the SRAM mode write operation, V _SS is first applied to both GSL 56 and NSE 70 to make the entire NAS memory cell operate like a single SRAM cell 20. Subsequent operations are the same as read operations of a general SRAM cell 20 .

(46)을 각각 제 1 데이터 노드(Q) 및 제 2 데이터 노드(

)에 연결되게 해준다. 이때 제 1 데이터 노드(Q)와 제 2 데이터 노드(

)는 이미 정보를 저장하고 있는 상태로 한쪽 노드는 V _DD2, 다른 한쪽 노드에는 V _SS의 전압을 형성하고 있다. 연결이 되면 제 1 데이터 노드(Q)와 제 2 데이터 노드(

) 중 V _SS의 전압을 저장하고 있는 노드와 연결된 BL_SRAM의 전압이 V _DD2에서 V _SS로 내려가게 되는데, sense amplifier에서 이 전압 변화를 감지하여 SRAM 셀(20)에 저장된 정보를 읽는다.The read operation of the _SRAM cell 20 is performed by raising the voltage of the WL _SRAM 60 to V _DD while the BL Pair _SRAMs 42 and 46 are precharged to V _DD2 .

(46) to the first data node (Q) and the second data node (

) to connect to. At this time, the first data node (Q) and the second data node (

) already stores information, and forms a voltage of V _DD2 at one node and V _SS at the other node. When connected, the first data node (Q) and the second data node (

), the voltage of the BL _SRAM connected to the node storing the voltage of V _SS decreases from V _DD2 to V _SS , and the sense amplifier detects this voltage change and reads the information stored in the SRAM cell 20.

<NAND Flash mode>

A write operation in NAND flash mode is performed simultaneously in all flash memory devices connected to the selected WL _Flash , not in one device among a plurality of non-volatile memory devices (flash memory devices). Here, V _SS is applied to the BL _Flash of the flash memory device to be programmed, and V _DD1 (eg, about 3V) is applied to the BL _Flash of the flash memory device not to be programmed for self-boosting.

6 is a timing diagram of a NAND Flash mode write operation of a NAS memory cell according to an embodiment of the present invention. First, the connection between the NAND Flash string 10 and the SRAM cell 20 is disconnected by applying V _SS (eg, about 0V) to the GSL 56 . The subsequent operation is the same as the general NAND Flash write operation.

The write operation of the NAND Flash string 10 applies V _SS or V _DD1 to the BL _Flash and at the same time raises the voltage of the SSL 52 to V _DD1 to connect the BL _Flash and flash memory elements. Thereafter, the voltages of all WL _Flashes are raised to V _pass,p (eg, about 6V), and the voltage of only the selected WL _Flashes is additionally raised to _Vpp (eg, about 20V). To the flash memory elements to which V _SS is applied to the BL _Flash , a voltage of V _pp is applied between the gate and the channel of the flash memory element connected to the selected WL _Flash , and FN-type programming occurs. On the other hand, in the flash memory devices to which V _DD1 is applied to the BL _Flash , self boosting occurs and the channel voltage rises. As a result, the voltage between the gate and the channel of the flash memory device connected to the selected WL _Flash is reduced, preventing programming from occurring.

Read operation in NAND flash mode is performed by detecting changes in the precharged BL _flash voltage in the page buffer. The BL _Flash voltage maintains its original state or goes down to V _SS according to the V _th value of the flash memory device connected to the selected WL _Flash .

7 is a timing diagram of a NAND Flash mode read operation of a NAS memory cell according to an embodiment of the present invention. First, a write operation of the SRAM cell 20 is performed to make the voltage of the first data node Q equal to V _SS . In general NAND Flash, the lower end of the NAND Flash string (the source part of the lower selection transistor connected to GSL) is connected to the Common Source Line (CSL), and V _SS is applied to CSL during read operation. However, in the NAS memory cell of the present invention, since the lower end of the NAND Flash string 10 is connected to the SRAM cell 20 through the first data node Q, V _SS cannot be applied directly. Instead, if the first data node Q is made V _SS at the beginning of operation, the same effect as applying V _SS to CSL can be obtained. The subsequent operation is the same as the read operation of general NAND Flash memory.

The read operation of the NAND Flash string 10 precharges the BL _Flash with V _BL,r (e.g., about 2V), and at the same time, V _DD voltage is applied to SSL(52) and GSL(56) respectively, and V _read to selected WL _Flash A (eg, about 2V) voltage and a V _pass,r (eg, about 6V) voltage are applied to the unselected WL _Flash . When the voltage is applied in this way, if the V _th of the flash memory device connected to the selected WL _Flash is greater than V _read , the connection between the BL _Flash and the first data node (Q) is disconnected, and the BL _Flash maintains the original voltage, and V _th becomes V If it is smaller than _read , BL _Flash and the first data node (Q) are connected and BL _Flash falls to V _SS .

<SNT mode>

SNT stands for SRAM-to-NAND Data Transfer, and SNT mode is used to transfer information stored in the SRAM cell 20 to the NAND flash string 10. The operation method of SNT mode is similar to the write operation of NAND flash mode, because both modes program the flash memory device. However, if the NAND flash mode write operation controls the program of each flash memory device with the voltage of the BL _Flash , the SNT mode depends on the information stored in the SRAM cell 20, that is, according to the voltage of the first data node (Q). Whether or not to program in the NAND flash device is determined.

8 is a SNT mode operation timing diagram of a NAS memory cell according to an embodiment of the present invention. First, the GSL 56 is raised to V _DD1 (eg, about 1V) to connect the flash memory device and the first data node (Q). Afterwards, all the WL _Flash voltages are raised to V _pass,p (eg, about 6V), and the selected WL _Flash is raised to V _pp (eg, about 20V). When the voltage of the first data node (Q) is V _SS , the voltage of V _pp is applied between the gate and the channel of the selected flash memory device to program the device, and the voltage of the first data node (Q) is V _DD2 In this case, self-boosting occurs and the corresponding device is not programmed.

<NST mode>

NST stands for NAND-to-SRAM Data Transfer, and NST mode is used to transfer information stored in the NAND flash string 10 to the SRAM cell 20. V _SS or V _DD2 is stored in the first data node (Q) according to V _th of the selected flash memory device.

9 is an NST mode operation timing diagram of a NAS memory cell according to an embodiment of the present invention. First, a write operation of the SRAM cell 20 is performed to initially set the voltage of the first data node Q to V _SS . Afterwards, selected WL _Flash raises the voltage with V _read and unselected WL _Flash with V _pass,r . At the same time, the voltage of the GSL 56 is raised to V _DD1 to connect the output node (G) and the first data node (Q), and the voltage of the output node (G) is set to V _SS . In this way, the initial voltage of the output node (G) must be set to prevent malfunction due to self-boosting. When the initial voltage setting of the output node (G) is completed, the GSL (56) is lowered to V _SS to separate the output node (G) and the first data node (Q). Then, the voltage of the first data node (Q) is made V _DD2 . Next, raise the voltage of BL _Flash (44) and SSL (52) to V _DD1 , respectively, and raise the voltage of NSE (70) to V _DD2 to activate the NST unit. When the V _th of the selected flash memory device is large, the electrical connection between the BL _Flash (44) and the output node (G) is disconnected, and the output node (G) maintains V _SS . In this case, the initial voltage V _DD2 is maintained at the first data node Q. Conversely, when the V _th of the selected device is small, the output node (G) is electrically connected to the BL _Flash (44) and the voltage of the output node (G) rises. In this case, the first data node (Q) is connected to the ground (GND) of the NST unit to store V _SS in the first data node (Q).

Next, with reference to FIGS. 10 to 13, the operating method of the NAS memory array of the present invention will be described.

<SRAM mode and NAND Flash mode>

10 is a block diagram showing the configuration of a NAS memory array and system according to an embodiment of the present invention. In the SRAM mode and NAND flash mode operations of the NAS memory array 100, the same operations as the SRAM mode and NAND flash mode operations of the NAS memory cells 110 described above are performed in units of rows of the array. In other words, simultaneous SRAM mode and NAND flash mode operations cannot be performed on multiple rows. This means that data moves through BL during SRAM mode and NAND flash mode operation, and each row shares BL with each other due to the array structure, so if one row uses BL, another row cannot use BL. Accordingly, when reading and writing a large amount of data, operations are sequentially performed row by row.

들을 모두 precharge 한 후, WL_SRAM,n을 켜 n번째 행에 저장된 데이터를 읽는다. 다음으로 BL_SRAM과

들을 다시 precharge 한 후, WL_SRAM,n+1을 켜 n+1번째 행에 저장된 데이터를 읽는다. 이와 같이 여러 행에 저장된 데이터를 읽을 경우 행 단위로 끊어 순차적으로 읽기 동작을 수행한다. 이러한 동작은 SRAM 읽기 동작 뿐만이 아닌, SRAM 쓰기 동작, flash 읽기 동작, 그리고 flash 쓰기 동작까지 동일하게 적용된다.11 is a timing diagram in a situation in which data stored in SRAM cells of the n-th row and the n+1-th row in the NAS memory array 100 of the present invention, that is, data stored in two rows is read. First, BL _SRAM and

After precharging all of them, turn on WL _SRAM,n to read the data stored in the nth row. Next, BL _SRAM and

After precharging them again, turn on WL _SRAM,n+1 to read the data stored in the n+1th row. In this way, when reading data stored in multiple rows, read operations are performed sequentially by cutting rows. These operations apply not only to SRAM read operations, but also to SRAM write operations, flash read operations, and flash write operations.

<SNT mode>

12 is a timing diagram when performing an SNT mode operation in the NAS memory array 100 of the present invention. Turn on the GSL, that is, GSL _sel , of the rows where the SNT operation is to be performed, and adjust the WL, that is, the WL _Flash,sel voltage of the rows to suit the SNT operation. Here, the selected row does not mean one row, but all rows for which the SNT operation is to be performed. The remaining WL _{Flash,Unsel that will not perform the SNT operation.} and GSL _Unsel. V _SS is applied to , and V _SS is also applied to the remaining lines that are not needed during SNT operation. In this way, SNT operation is possible in all desired rows simultaneously.

<NST mode>

13 is a timing diagram when NST mode operation is performed in the NAS memory array 100 of the present invention. The lines of the line to be operated on, that is, the SSL _Sel. , WL _{Flash, Sel.} , GSL _Sel. , NSE _Sel. , WL _{SRAM, Sel.} Adjust the voltage according to NST operation. The rest of the lines that do not perform NST operation, i.e. SSL _Unsel. , WL _{Flash, Unsel.} , GSL _Unsel. , NSE _Unsel. , WL _{SRAM, Unsel.} V _SS is applied to Lastly, if BL Pair _SRAM and BL _Flash are adjusted according to NST operation, NST operation is possible in all rows at the same time.

Next, with reference to FIGS. 14 and 15, simulation results for the NAS memory cell of FIG. 3 will be described.

The NAS memory cell of FIG. 3 was simulated in the SNT mode and NST mode of Tables 1 and 2 below using the Cadence Virtuoso ^® circuit simulation tool. The number of flash memory elements of the NAND string was set to 64.

<Voltage applied in SNT mode simulation> Simulation Parameters Values V _DD2 1V V _SS 0V V _pass,p 10V V _pp 20V

Referring to FIG. 14 , when the state of the first data node Q is V _SS , it can be seen that the voltage of the memory node K rises to some extent and then falls at T ₂ . This is because the voltage of the WL _flash increases simultaneously and the channel voltage of the flash memory device also increases due to capacitance coupling. However, since V _SS is stored in the first data node Q connected to the memory node K, it can be confirmed that the voltage that has risen over time is reduced to V _SS again.

<Voltage applied in NST mode simulation> Simulation Parameters Values V _DD1 3V V _DD2 1V V _SS 0V V _read 2V V _pass,r 6V

Referring to FIG. 15, the voltage of the output node (G) temporarily rises at T2. As in the SNT mode, this is because the voltage of the WL _Flash simultaneously rises and the channel voltage of the flash memory device also rises due to capacitance coupling. . When the first data node (Q) is set to V _SS and the GSL is turned on to connect the first data node (Q) and the memory node (K), it can be confirmed that the voltage that went up immediately goes down again. In both modes, you can see the results match your expectations.

One of the biggest advantages of the NAS memory of the present invention is that data can be sent at once regardless of the size of the data when transferring data between NAND flash and SRAM. In a general memory system, as shown in FIG. 1 , data transmission time increases in proportion to the size of data because data is divided and transmitted in predetermined units. A data transmission process in a general memory system is as follows. 1) First, read data in the nth row of SRAM. 2) Next, the read data is transferred to the I/O buffer of NAND Flash. At the same time, the data of the n+1th row, which is the next row, is read. 3) Next, the data of the nth row of SRAM stored in the I/O buffer of NAND Flash is stored in NAND Flash. At the same time, data read from the n+1 row of SRAM is sent to the I/O buffer of NAND Flash, and the n+2 row of SRAM is read. By repeating the above process, the transfer of up to the mth row data of the SRAM is completed. Due to this characteristic, data transmission time increases in proportion to the size of the data. However, in the NAS memory according to the present invention, as shown in FIG. 2, data can be transmitted at once by performing an SNT operation or an NST operation on a desired plurality of rows regardless of the size of data. Because of these characteristics, it is more efficient than conventional general memory systems in terms of speed and power.

Claims (13)

a NAND Flash string in which an upper selection transistor, a plurality of inactive memory elements, and a lower selection transistor are connected in series;
an SRAM cell having a volatile storage unit having a first data node connected to a lower end of the lower select transistor and a second data node in which an electrical signal of the first data node is inverted; and
An NST unit connected to the first data node and a transmission control line (NSE) to transmit data from the NAND Flash string to the SRAM cell,
The NST unit is composed of first and second transistors connected in series to the first data node, a gate of the first transistor is connected to the transfer control line, and a gate of the second transistor is connected to the NAND Flash string. A NAS memory cell, characterized in that connected to an output node between the last inactive memory element and the low side select transistor.
According to claim 1,
The volatile storage unit is composed of two inverters, wherein the output of one inverter is connected to the input of another inverter, and the input of one inverter is connected to the output of the other inverter.
According to claim 1,
The volatile storage unit is composed of two storage transistors and two resistors, a first storage transistor between the first data node and the ground, and a first resistor between the first data node and a supply voltage, respectively. A second storage transistor is connected between the second data node and the ground, and a second resistor is connected between the second data node and the supply voltage terminal, and a gate of the first storage transistor is connected to the first storage transistor. 2 data nodes, wherein the gate of the second storage transistor is connected to the first data node.
According to any one of claims 1 to 3,
The SRAM cell further comprises a first access transistor connected between the first data node and an SRAM bit line and a second access transistor connected between the second data node and an SRAM inverted bit line, wherein the first access transistor A gate of and a gate of the second access transistor are connected to an SRAM word line;
The upper end of the upper select transistor is a flash bit line, the gate of the upper select transistor is an upper control line (SSL), each gate of the plurality of inactive memory elements is a plurality of word lines, and the gate of the lower select transistor is a lower control line NAS memory cells, characterized in that each connected to (GSL).
A NAS memory array characterized in that it is configured by arranging the NAS memory cells of claim 4 in a matrix form (M x N) with M rows and N columns.
According to claim 5,
The NAS memory cells arranged in M rows connect the upper control line SSL, the plurality of word lines, the transmission control line NSE, the lower control line GSL, and the SRAM word line to each other in each row. share,
The NAS memory array, characterized in that the NAS memory cells arranged in N columns share the Flash bit line, the SRAM bit line, and the SRAM inversion bit line for each column.
According to claim 6,
The NAS memory array, characterized in that the NAS memory cells arranged in the M rows are independently controlled for each row by a NAND Flash word line decoder and an SRAM word line decoder so that data of two or more rows can be transmitted simultaneously.
A method of operating the NAS memory cell of claim 4,
The method of operating a NAS memory cell, characterized in that by applying V _SS to the transmission control line (NSE) to use the NAS memory cell as a NAND flash memory.
A method of operating the NAS memory cell of claim 4,
The method of operating a NAS memory cell, characterized in that by applying V _SS to each of the transmission control line (NSE) and the lower control line (GSL) to use the NAS memory cell as an SRAM cell.
A method of operating the NAS memory cell of claim 4,
a first step of making the first data node V _SS ;
a second step of making the output node V _SS ;
a third step of making the first data node equal to V _DD1 ; and
A method of operating a NAS memory cell, comprising a fourth step of turning on the first transistor through the transfer control line (NSE) to transmit data stored in the NAND Flash string to the SRAM cell.
A method of operating the NAS memory cell of claim 4,
The first transistor and the upper selection transistor are turned off through the transfer control line NSE and the upper control line SSL, respectively, and the lower selection transistor is turned on through the lower control line GSL. After turning on), data of the first data node of the SRAM cell is transmitted to the NAND Flash string by a write operation of the plurality of inactive memory devices.
In the method of operating the NAS memory array of claim 7,
In the NAND Flash word line decoder, one or more rows are selected from among the M rows, and NAS memory cells disposed in each row selected as the one or more rows are respectively
a first step of making the first data node V _SS ;
a second step of making the output node V _SS ;
a third step of making the first data node equal to V _DD1 ; and
In an operation including a fourth step of turning on the first transistor through the transfer control line (NSE), the data stored in the NAND Flash string of the NAS memory cells disposed in each selected row is transferred to the SRAM cell at once. A method of operating a NAS memory array, characterized in that for transmitting.
In the method of operating the NAS memory array of claim 7,
In the NAND Flash word line decoder, one or more rows are selected from among the M rows, and a control signal of each row of NAS memory cells arranged in each row selected as the one or more rows is transmitted through the transmission control line (NSE) After turning off the first transistor and the upper selection transistor through the upper control line SSL and turning on the lower selection transistor through the lower control line GSL, the plurality of A method of operating a NAS memory array, characterized in that transferring data stored in a first data node of an SRAM cell of the NAS memory cells disposed in each row to a NAND flash string at once by a write operation of the number of inactive memory elements.

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