JP4290818B2 - Bit transfer additional data high-speed transfer circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer circuit that adds additional data obtained by bit operation to data to be transferred and transfers the additional data to the transfer data, and more particularly to a data transfer circuit used in a PDC or PHS telephone or other wireless device.
[0002]
[Prior art]
Such data transfer is generally retimed at a data rate and transferred in synchronization with a transfer frame. However, in recent years, the number of retiming has been reduced, and CRC or the like can be performed at a higher speed. Data transfer with bit operation added is required.
[0003]
As a general example of data transfer including CRC bits, as disclosed in Japanese Patent Laid-Open No. 7-283757, a CRC calculation is performed in advance, and data with the CRC bits added is stored in a temporary data buffer and transmitted. Data is transferred according to the request. This is shown in FIG.
[0004]
[Problems to be solved by the invention]
In such a conventional data transfer circuit, since data is stored in the buffer in advance, a long waiting time is required until the data is transmitted, and data transfer cannot be performed at high speed. In addition, this circuit shows a single-channel transfer circuit for audio data converted into data through a microphone. However, if multiple channels are to be multiplexed and transferred, the transfer usually consists of a CRC calculator and a data buffer, etc. The entire process must be configured in parallel. Therefore, there is a problem that the circuit scale of the data transfer circuit becomes large.
[0005]
Therefore, the present invention aims to enable high-speed transfer even with a data transfer circuit that transfers data in which bit operations such as CRC are added to transmission data, and can be realized with a small circuit. To do.
[0006]
[Means for Solving the Problems]
According to the present invention, in a data transfer circuit for transferring data to which bit operation data generated by performing bit operation on the data is transferred before data to be transferred, a memory for storing the data to be transferred; A control unit that gives a read signal at least twice to the same data stored in the memory, and data read from the memory as inputs, and bit operation data is generated and output by performing bit operations on the data. The bit arithmetic unit, the output of the bit arithmetic unit and the data read from the memory are input, and either one of the bit arithmetic data or the data read from the memory is selected according to the timing output by the control unit. A selector that outputs the bit, and the control unit performs a bit operation by performing bit operation on the first memory read data. Bit operation data generated by applying a control signal to the selector so that the bit operation data is output while data is being input to the selector, and performing bit operation on the data read at the first time. And a second read signal is output to the memory at a timing at which the second read data is output from the selector in succession. be able to.
[0007]
In addition, the control unit starts a count operation in response to an input of a start timing, and counts up while the first counter holds a predetermined value, and controls the timing of the read signal and the number of memory accesses. And a second counter that outputs an address signal necessary for memory access, and a decoder that decodes the outputs of the first counter and the second counter and outputs a control signal to each circuit.
[0008]
Further, the data to be transferred is composed of two channels, and after transferring the data to which the first bit operation data generated by performing bit operation on the data before the first channel data is transferred, In a data transfer circuit for transferring data in which second bit operation data generated by performing bit operation on the data after the second channel data is transferred, first data for storing the first channel data is stored. Memory, the second memory for storing the data of the second channel, and the same data stored in the first memory are successively given two read signals, and after the memory access is completed, A control unit for supplying a read signal to the second memory continuously and a bit operation by performing a bit operation on the data read from the first and second memories A bit calculator for generating and outputting data, and the first channel according to a timing at which the output of the bit calculator and data read from the first and second memories are input and output by the controller And a selector that selects and outputs one of the data, the second channel data, the first bit operation data, or the second bit operation data, and the control unit includes: Bit calculation is performed on the first bit operation data generated by performing bit operation on the first channel data read for the first time and the second channel data read from the second memory. While the second bit operation data generated by this is input to the selector, the selector controls the first and second bit operation data to be output. All of the first bit operation data generated by performing bit operation on the data read out at the first time is completed, and subsequently read out from the first memory for the second time. It is also possible to obtain a data transfer circuit characterized in that the second read signal is output to the first memory at the timing when the processed data is output from the selector.
[0009]
Further, the control unit sends the first read signal so that the timing at which the bit operation data generated by performing the bit operation on the first read data coincides with the frame timing of the data transfer. By outputting, a data transfer circuit synchronized with the transmission frame can be obtained.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a data transfer circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the present embodiment. Referring to FIG. 1, the data transfer circuit has a memory 2 for temporarily storing transfer data in order to add operation data to the head of the transfer data. The control unit 1 is responsible for overall control of the data transfer circuit, and has functions such as selecting output data of the selector 5 in addition to controlling the number of times of reading data to be transferred from the memory. The P / S conversion circuit 3 is provided between the memory 2 and the CRC calculator 4 and converts parallel data output from the memory 2 into serial data. The CRC calculator 4 performs a CRC calculation on the data output from the P / S conversion circuit 3, and outputs CRC data obtained as a result of the calculation to the selector 5. The selector 5 selects and outputs data (output data of the P / S conversion circuit 3) or a CRC bit (output data of the CRC calculator 4) under the control of the control unit 1.
[0011]
FIG. 2 is a block diagram showing a configuration example of the control unit 1 in the embodiment of the present invention. In FIG. 2, the control unit 1 includes a counter 1a, a counter 1b, and a decoder 1c. The counter 1a is for controlling the timing and the number of times of memory access, and starts the counting operation upon receiving the start timing. The counter 1b is for controlling the access period for each number of memory accesses, and continues counting up unless it is incremented or reset depending on the change of the counter 1a. The decoder 1c serves to output the operation timing to the memory 2, the P / S conversion circuit 3, the CRC calculator 4, and the selector 5. The decoder 1c decodes the outputs of the counter 1a and the counter 1b and outputs various control signals. Output. The control information defined in advance by the system is given to the decoder 1c, or a control signal necessary for continuous transfer is outputted by being given each time from the upper part.
[0012]
Next, the operation of the data transfer circuit of FIG. 1 will be described with reference to the time chart shown in FIG.
[0013]
The time chart shown in FIG. 3 shows an operation in the case where the CRC calculation is performed on the transfer data, and the data in which the calculated CRC bit is added before the transfer data is transferred. In the present invention, when transferring one frame to which bit operation data is added, the transfer operation can be performed at a high speed and continuously, so that the same data stored in the memory 2 is stored twice. Access is performed, and the first memory access is used for CRC calculation, and the second memory access is used for data transfer.
[0014]
The period from the start of these two memory accesses to the completion of data transfer is defined as one cycle, and the period from the count value “0” to “2” of the counter 1a that starts the operation upon receiving the input of the start timing is This corresponds to one cycle. When one cycle is completed, the count value of the counter 1a is reset to “0”, and thereafter the same operation is repeated. The counter 1b linked to the counter 1a starts counting up by a change in the count value of the counter 1a, and continues counting up until the counter 1a changes next time.
[0015]
First, in the first memory access, the counter 1a holds “0” for a predetermined period with the start timing as a trigger. On the other hand, the counter 1b continues to count up from 0 to n. The decoder 1c decodes the count values of the counter 1a and the counter 1b and outputs an address signal to the memory 2 to perform the first data read (DATA READ 1 in the figure), via the P / S conversion circuit 3. The CRC calculator 4 performs calculation processing in units of clocks to generate CRC data.
[0016]
Here, paying attention to the first memory access, it can be seen that the reading of the transfer data is completed in the middle of the period in which the counter 1a shows a value of “0”. In other words, an additional period is provided for reading the data to be transferred, which is obtained by performing a CRC operation on the read data and reading it by the second memory access in succession to the transfer of the generated CRC data. The period is provided in excess of the time required for memory access so that data transfer can be started continuously.
[0017]
The second memory access corresponds to a period in which the count value of the counter 1a is “1”, and the counter 1b that has continued to count up so far resets the previous value and counts up again from zero. The decoder 1c decodes the outputs of both counters and reads the same data for the second time as described above. Then, the data read out for the second time is started to be transferred in succession to the last bit of the CRC data in the additional period whose timing is adjusted in advance. When the count value of the counter 1b ends to “m”, the second memory access is ended.
[0018]
When the second memory access is completed, the count value of the counter 1a is incremented to “2”. This period is provided to complement the delay time from the completion of the memory access to the data transfer.
[0019]
Note that even in the period provided to supplement the additional period and the delay time, the count value of each counter is output to the decoder 1c, but the combination of the count values is input to the decoder 1c. In this case, unnecessary data transfer can be avoided by invalidating memory access or outputting a control signal for prohibiting transfer of read data to the selector 5.
[0020]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. As an embodiment of the present invention, the first embodiment described above has the basic configuration. In the data transfer circuit shown below, data of two channels (hereinafter referred to as CH) is multiplexed and transmitted.
[0021]
Referring to FIG. 4, under the control of the control unit 1, this data transfer circuit temporarily stores 2CH of audio data encoded by CODEC and 2CH of control data output from the CPU in dedicated memories 2a and 2b, respectively. Then, a CRC bit obtained by CRC calculation is added and output from the selector 5.
[0022]
Next, each block constituting the data transfer circuit will be briefly described. The control unit 1 outputs a control signal for determining operation timing and the like to each circuit block based on the control information received from the CPU.
[0023]
In addition to outputting control information to the control unit 1, the CPU has control data that is one of the multiplexed CHs, and outputs the control data to the control data memory 2b in the subsequent stage. The CPU performs storage in the control data memory 2a and basic control of the CH.
[0024]
A memory unit composed of the audio data memory 2a and the control data memory 2b is a memory for storing audio data and control data, and is connected in parallel to the selector 2c. Reading of the memory is performed according to a counter value of the control unit 1 described later.
[0025]
The selector 2c selects the data read from the memories 2a and 2b according to the control of the control unit 1 and outputs it to the P / S conversion circuit 3 at the subsequent stage.
[0026]
The functions and connection relationships of the P / S conversion circuit 3, the CRC calculator 4, and the selector 5 are the same as in the previous embodiment, but the data to be transferred is a multiplexed CH and the CRC bit calculated from these. Is different from the previous embodiment mainly in terms of the operation timing of each part.
[0027]
FIG. 5 shows the configuration of the control unit 1 of FIG. The control unit 1 includes a counter 1a, a counter 1b, and a decoder 1c as in the above-described embodiment, and includes a selector 1d in order to support control of multiple CHs. The counter 1a and the counter 1b start the count operation at the start timing output from the CPU. The decoder 1c decodes the count values of the counters 1a and 1b in accordance with the operation timing of each block. The selector 1d selects the decode value of the decoder 1d because the operation timing of each block differs depending on the type and rate of the CH. This output becomes a control signal for controlling each block.
[0028]
Next, the operation of the data transfer circuit of FIG. 4 will be described with reference to the time chart shown in FIG.
[0029]
In the time chart shown in FIG. 6, the timing when CRC data obtained by CRC calculation of voice data is added before the voice data, and then the CRC data obtained by CRC calculation of control data is added after the control data is transferred. Show. In this embodiment, memory access to the memory unit is performed three times. That is, for audio data, the CRC data is added to the audio data memory twice in order to add the CRC calculated CRC data before the audio data, and for the control data, the CRC data is added after the control data. Therefore, one memory access is performed to the control data memory.
[0030]
The period from the start of these three memory accesses to the completion of the data transfer is defined as one cycle, and the period from the count value “0” to “2” of the counter 1a that starts the operation in response to the input of the start timing is This corresponds to one cycle. When one cycle is completed, the count value of the counter 1a is reset to “0”, and thereafter the same operation is repeated. The counter 1b starts counting up due to a change in the count value of the counter 1a, and continues counting up until the counter 1a changes next time.
[0031]
First, the first memory access is to the audio data memory, and the counter 1a holds “0” for a predetermined period with the start timing as a trigger. On the other hand, the counter 1b continues to count up from 0 to n. The decoder 1c decodes the count values of the counter 1a and the counter 1b and outputs an address signal to the memory 2 so that the first data read is performed (sound DATA READ 1 in the figure), and the P / S conversion circuit 3 is Thus, the CRC calculator 4 performs arithmetic processing in units of clocks to generate CRC data. The setting of the period in which the counter 1a indicates “0” is determined according to the same criteria as in the first embodiment.
[0032]
For the second memory access, the same operation as in the first embodiment is performed, and the setting of the period in which the counter 1a indicates “1” corresponds to the period in which the count value of the counter 1a is “1”. The counter 1b that has continued to count up so far resets the previous value and counts up again from zero. The decoder 1c decodes the outputs of both counters and performs the second memory access to the same data as described above (sound DATA READ2 in the figure). Since the data is provided with an additional period required for continuous transfer in the first memory access described above, the transfer is started continuously with the last bit of the CRC data. When the count value of the counter 1b ends to “m”, the second memory access is ended. This count value “m” coincides with the audio data reading period.
[0033]
When the audio data memory access is completed, the count value of the counter 1a is incremented to “2”, and the control data is read from the control data memory 2b in succession to the audio data as the third memory access (see FIG. Inside control DATA READ1). In the third memory access, the CRC calculation is performed on the control data simultaneously with the transfer of the control data, so that the CRC data can be continuously transferred after the data transfer is completed.
[0034]
When the third memory access is completed, the count value of the counter 1a is counted up to “3” in order to complement the delay time from the completion of data reading to the data transfer. The count is reset to “0”, and one cycle from memory access to data transfer is completed.
[0035]
Further, since the start timing to be designated is advanced by the processing time required for the CRC calculation processing in the CPU, data transfer synchronized with the frame timing can be realized. Since the processing delay time at this time is determined by the type of CH to be transferred, this circuit notifies the CPU of this time in advance.
[0036]
As described above, according to the present embodiment, it is possible to obtain an effect that multi-channels can be transferred without interruption in one frame.
[0037]
In the above embodiment, the CRC calculator has been described as an example. However, it is not particularly limited to the CRC calculator, and calculation data calculated with respect to the transfer data at the time of data transfer is added before the transfer data. Since it can be applied to all transfer circuits, other bit arithmetic units may be used. Further, when handling data having different bit operation methods, it is possible to cope with this by merely configuring the bit arithmetic unit in parallel. Furthermore, when transferring multiple channels within one frame, it is possible to add a setting to increase the count value of the counter 1a.
[0038]
【The invention's effect】
In each of the above embodiments, the operation and effect of data transfer without straddling frames is obtained by using the control of the counter, and the object of the present invention is achieved.
[0039]
In addition, in this embodiment, since the frame timing is advanced by the necessary time for each case by CPU control, there is a synergistic effect that data synchronized with the frame can be transferred.
[0040]
As described above, according to the present invention, it is possible to provide a data transfer circuit that realizes high speed based on a basic configuration of control by a counter of bit operation additional data. Further, when increasing the multiplicity of data, the circuit configuration can be simplified because the parts configured in parallel are minimized in the circuit configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram of a data transfer circuit according to a first embodiment to which the present invention is applied.
FIG. 2 is a configuration diagram of a control unit of the data transfer circuit according to the first embodiment.
FIG. 3 is a timing chart showing the operation of the data transfer circuit according to the first embodiment.
FIG. 4 is a block diagram of a data transfer circuit according to a second embodiment to which the present invention is applied.
FIG. 5 is a configuration diagram of a control unit of a data transfer circuit according to a second embodiment.
FIG. 6 is a timing chart showing the operation of the data transfer circuit according to the second embodiment.
FIG. 7 is a block diagram of a conventional data transfer circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Control part 1a Counter 1b Counter 1c Decoder 1d Selector 2 Memory 2a Audio data memory 2b Control data memory 2c Selector 3 P / S conversion circuit 4 CRC calculator 5 Selector

Claims (4)

In a data transfer circuit for transferring data to which bit operation data generated by performing bit operation on the data is transferred before data to be transferred,
A memory for storing the data to be transferred;
A control unit for providing a read signal at least twice for the same data stored in the memory;
A bit arithmetic unit that receives data read from the memory as input and generates and outputs bit operation data by performing bit operation on the data;
A selector that receives the output of the bit arithmetic unit and the data read from the memory, and selects and outputs either the bit arithmetic data or the data read from the memory according to the timing output by the control unit; Prepared,
The control unit provides a control signal to the selector so that the bit operation data is output while the bit operation data obtained by performing bit operation on the first memory read data is input to the selector. All the bit operation data generated by performing bit operation on the read data is completed, and then the second read is performed at the timing when the second read data is output from the selector. A data transfer circuit for outputting a signal to the memory. The control unit starts a count operation in response to an input of a start timing, and continues to count up while the first counter holds a predetermined value while controlling the timing of the read signal and the number of memory accesses. 2. A second counter that outputs an address signal required for memory access, and a decoder that decodes outputs of the first counter and the second counter and outputs a control signal to each circuit. The data transfer circuit described in 1. The data to be transferred is composed of two channels, and after the data added with the first bit operation data generated by performing bit operation on the data before the data of the first channel is transferred, In the data transfer circuit for transferring the data with the second bit operation data generated by performing bit operation on the data after the channel data,
A first memory for storing data of the first channel; a second memory for storing data of the second channel;
A control unit that continuously gives a read signal twice to the same data stored in the first memory, and gives a read signal to the second memory continuously after the end of the memory access;
A bit calculator that generates and outputs bit operation data by performing bit operations on the data read from the first and second memories;
The first channel data, the second channel data, the first channel data, and the data output from the first and second memories and the timing output by the control unit are input. A selector that selects and outputs one of the bit operation data of 1 or the second bit operation data;
The control unit performs first bit operation data generated by performing bit operation on data of the first channel read for the first time with respect to the first memory, and second read from the second memory. A control signal is sent to the selector so that the first and second bit operation data are output while the second bit operation data generated by performing the bit operation on the data of the channel is input to the selector. All the transfer of the first bit operation data generated by performing bit operation on the data read out at the first time is completed and read out from the first memory for the second time continuously. A data transfer circuit which outputs a second read signal to the first memory at a timing when the data is output from the selector. The control unit outputs the first read signal so that the timing at which the bit operation data generated by performing bit operation on the data read at the first time coincides with the frame timing of data transfer. 4. The data transfer circuit according to claim 1, wherein the data transfer circuit outputs the data.

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