JP4289195B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply device, and more particularly, a coil having a power supply voltage applied to one end thereof, a MOS transistor having a drain-source connected between the other end of the coil and an output terminal, and an output output from the output terminal. The present invention relates to a power supply device having a control circuit unit that detects a voltage and controls a MOS transistor so that a voltage at an output terminal becomes a predetermined voltage.

  FIG. 3 is a circuit diagram showing an example of a conventional power supply device.

  The conventional power supply device 1 constitutes a chopper type step-up switching regulator by a coil L, MOS transistors Q1 to Q4, resistors R1 and R2, a capacitor C1, an inverter 21, and a control circuit 22, and includes a direct current made of a battery or the like. The output voltage of the power supply 11 is boosted and output from the output terminal Tout (see Patent Document 1).

  The DC power supply 11 is supplied to one end of the coil L. The other end of the coil L is connected to the ground terminal Tgnd via the N-channel MOS transistor Q1, and is connected to the output terminal Tout via the P-channel MOS transistor Q2.

  Resistors R1 and R2 are connected in series and a capacitor C is connected between the output terminal Tout and the ground terminal Tgnd. A voltage Vs obtained by dividing the output voltage Vout output from the output terminal Tout appears at a connection point between the resistors R1 and R2. The voltage Vs that appears at the connection point between the resistor R1 and the resistor R2 is supplied to the control circuit 22.

  The control circuit 22 turns on the MOS transistor Q1 and the MOS transistor Q2 alternately according to the voltage Vs. At this time, the cycle is controlled so that the output voltage Vout output from the output terminal Tout is constant.

  The MOS transistors Q3 and Q4 are switch means for switching the substrate voltage of the MOS transistor Q2, and are circuits for preventing leakage current from flowing to the output terminal Tout when the MOS transistor Q2 is off.

  FIG. 4 shows a cross-sectional view of a p-channel MOS transistor.

  In the p-channel MOS transistor, an n-type well region 32 is provided on a p-type substrate 31, and high-concentration p-type regions 33 and 34 are provided on the well region 32 to serve as a source and a drain. The gate electrode 36 is formed on the region between the concentration p-type region 34 with the insulating layer 35 interposed therebetween. At this time, parasitic diodes D1 and D2 are formed by the high-concentration p-type regions 33 and 34, the well region 32, and the high-concentration n-type region 37.

  At this time, when the substrate potential is determined by connecting the high-concentration n-type region 37 which is the back gate of the MOS transistor Q2 to the source or drain like a normal MOS transistor, the coil is passed through the parasitic diode when the MOS transistor Q2 is off. Current flows from the L side to the output terminal Tout side.

  For this reason, MOS transistors Q3 and Q4 are provided, and the substrate potential of the MOS transistor Q2 is switched to prevent a current from flowing from the coil L side to the output terminal Tout side when the MOS transistor Q2 is turned off.

  A control signal is supplied to the terminal Tcnt from the outside. The control signal is a signal for outputting or stopping the output voltage Vout from the output terminal Tout. The control signal supplied to the terminal Tcnt is supplied to the control circuit 22 and to the gate of the MOS transistor Q4 and the gate of the MOS transistor Q3 via the inverter 21.

  The MOS transistor Q3 has a source-drain connected between the other end of the coil L and the substrate of the MOS transistor Q1. Further, the MOS transistor Q4 has a source-drain connected between the output terminal Tout and a substrate which is the back gate of the MOS transistor Q1.

  MOS transistor Q3 is turned off because its gate potential is high when the control signal is low. When the control signal is at a high level, the gate potential is at a low level and is turned on.

  The MOS transistor Q4 is turned on because its gate potential is low when the control signal is low. When the control signal is at a high level, the gate potential is at a high level and is turned off. By switching the MOS transistors Q3 and Q4 according to the control signal, the substrate potential of the MOS transistor Q2 is switched when output of the output voltage Vout is stopped, so that no unnecessary current flows.

JP-A-8-251913

  However, since the conventional power supply device 1 simply switches the substrate voltage by switching the MOS transistors Q3 and Q4, the substrate potential of the MOS transistor Q2 cannot be freely set.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a power supply apparatus that can reduce a leakage current when a circuit operation is stopped and can easily design a circuit.

  The present invention provides a coil (L) having a power supply voltage (VDD) applied to one end thereof, and a first MOS transistor having a drain-source connected between the other end of the coil (L) and an output terminal (Tout). (Q2) and the output voltage (Vout) output from the output terminal (Tout) are detected, and the connection of the other end of the coil (L) is controlled so that the voltage of the output terminal (Tout) becomes a predetermined voltage. In the power supply circuit having the control circuit (112), the second MOS transistor (Q12) connected between the substrate of the first MOS transistor (Q2) and the output terminal (Tout), and the first MOS transistor The first resistor (R11) connected between the substrate of (Q2) and the coil (L), and between the substrate of the first MOS transistor (Q2) and the gate of the second MOS transistor (Q12) A second resistor (R12) connected to And a switching means (Q11) connected between the connection point between the gate of the second MOS transistor (Q12) and the second resistor (R12) and the reference potential (GND).

  In the present invention, the parasitic diode (D13) is formed so that the second MOS transistor (Q12) is in the forward direction from the output terminal (Tout) side toward the substrate side of the first MOS transistor (Q2). It is characterized by having been configured.

  Further, the second MOS transistor (Q12) is composed of a P-channel MOS transistor, and the substrate is connected to the substrate of the first MOS transistor (Q2).

  The switch means (Q11) is turned on when the power supply (Vout) is output from the output terminal (Tout), and is turned off when the output of the power supply is stopped from the output terminal (Tout).

  The switch means (Q11) is composed of a MOS transistor.

  In addition, the said reference code is a reference to the last, This does not limit a claim.

  According to the present invention, a coil having an input terminal connected to one end, a first MOS transistor having a drain-source connected between the other end of the coil and an output terminal, and an output voltage output from the output terminal Is connected between the substrate of the first MOS transistor and the output terminal in a power supply circuit having a control circuit unit for controlling connection of the other end of the coil so that the voltage of the output terminal becomes a predetermined voltage. The second MOS transistor, the first resistor connected between the substrate of the first MOS transistor and the coil, and the substrate of the first MOS transistor and the gate of the second MOS transistor. By providing the connected second resistor and the switch means connected between the connection point between the gate of the second MOS transistor and the second resistor and the reference potential, the electric power from the output terminal is provided. The first MOS transistor and a second MOS transistor when the output is stopped in can be reliably turned off. This can prevent leakage current from flowing from the output terminal to the load when power output from the output terminal is stopped.

  Further, according to the present invention, since the substrate potential of the first MOS transistor and the gate voltage of the second MOS transistor can be adjusted by the first resistor and the second resistor, the design can be easily performed.

〔Constitution〕
FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The power supply device 100 of this embodiment is a chopper type boosting switching regulator, and includes a coil L, MOS transistors Q1, Q2, Q11, Q12, resistors R1, R2, R11, R12, a capacitor C1, a control circuit 112, and an inverter 113. It is composed of The diodes D1 and D2 are parasitic diodes formed between the substrate of the MOS transistor Q2 and the source and drain. The diode D13 is a parasitic diode formed between the substrate and the drain of the transistor Q12.

  One end of the coil L is applied with a positive potential of a DC power source 11 formed of a battery or the like. The other end of the coil L is connected to the drain of the N-channel MOS transistor Q1 and the drain of the P-channel MOS transistor Q2. The source of the MOS transistor Q1 is connected to the ground terminal Tgnd. The source of the MOS transistor Q2 is connected to the output terminal Tout. Here, a connection point between the other end of the coil L and the drain ends of the MOS transistors Q1 and Q2 is A. Note that parasitic diodes D1 and D2 are parasitic between the source and drain of the MOS transistor Q2 and the substrate, as shown in FIG.

  The gate of the MOS transistor Q1 and the gate of the MOS transistor Q2 are connected to the control circuit 112. The MOS transistor Q1 and the MOS transistor Q2 are switched so as to be alternately turned on by a drive pulse from the control circuit 112. By such an operation, a so-called synchronous rectifier regulator is configured.

  The n-channel MOS transistor Q11 has a source-drain connected between the ground terminal Tgnd and the gate of the MOS transistor Q12. A control terminal Tcnt is connected to the gate of the MOS transistor Q11 via an inverter 113, and an inverted control signal obtained by inverting the control signal supplied to the control terminal Tcnt is supplied.

  Further, the p-channel MOS transistor Q12 has a source-drain connected between the substrate of the MOS transistor Q2 and the output terminal Tout. The gate of the MOS transistor Q12 is connected to the ground terminal Tgnd through the MOS transistor Q11 and is connected to the substrate of the MOS transistor Q2 through the resistor R12.

  The resistor R11 is connected between the substrate of the MOS transistor Q2 and the connection point A. The resistor R12 is connected between the substrate of the MOS transistor Q2 and the gate of the MOS transistor Q11.

  The control circuit 112 is supplied with a voltage at a connection point between the resistors R1 and R2, that is, a voltage Vs corresponding to the output voltage Vout output from the output terminal Tout. The control circuit 112 generates a pulse having a pulse width corresponding to the voltage Vs at the connection point between the resistor R1 and the resistor R2, and supplies the pulse to the gates of the MOS transistors Q1 and Q2. At this time, the control circuit 112 controls the pulse width of the pulses supplied to the gates of the MOS transistors Q1 and Q2 so that the output voltage Vout output from the output terminal Tout becomes a constant voltage.

  In addition, a control terminal Tcnt is connected to the control circuit 112 via an inverter 113. A control signal is supplied to the control terminal Tcnt from the outside. The control signal is a signal for controlling an operation for outputting the output voltage Vout from the output terminal Tout and an operation for stopping the output voltage Vout.

  The control signal supplied to the control terminal Tcnt is at a low level when the output voltage Vout is output from the output terminal Tout, and is at a high level when the output of the output voltage Vout from the output terminal Tout is stopped. The control signal supplied to the control terminal Tcnt is supplied to the inverter 113. The inverter 113 inverts the control signal from the control terminal Tcnt. The inversion control signal is supplied to the control circuit 112 and the gate of the MOS transistor Q11.

  When the control signal supplied to the control terminal Tcnt is at a low level and the output signal of the inverter 113 is at a high level, the control circuit 112 has a pulse with a pulse width corresponding to the voltage Vs at the connection point between the resistor R1 and the resistor R2. By generating a signal and supplying the signal to the gates of the MOS transistors Q1 and Q2, the MOS transistor Q1 and the MOS transistor Q2 are alternately turned on, and the output voltage Vout is output from the output terminal Tout. The control circuit 112 sets the gate potential of the MOS transistor Q1 to low level and sets the gate potential of the MOS transistor Q2 when the control signal supplied to the control terminal Tcnt is high level and the output signal of the inverter 113 is low level. Is set to the high level, both the MOS transistors Q1 and Q2 are turned off, and the output voltage Vout from the output terminal Tout is stopped.

  At this time, since the inverted control signal is supplied to the gate of the MOS transistor Q11, when the output signal of the inverter 113 is at the high level, the gate potential is at the high level, and the MOS transistor Q11 is turned on. When the MOS transistor Q11 is turned on, the gate potential of the MOS transistor Q12 becomes low level. The MOS transistor Q12 is turned on when the gate potential becomes low level.

  When the output signal of the inverter 113 is at a low level, the MOS transistor Q11 is turned off because the gate potential is at a low level. When the MOS transistor Q11 is turned off, the gate potential of the MOS transistor Q12 becomes high level, so that the MOS transistor Q12 is turned off.

[Operation]
FIG. 2 is a diagram for explaining the operation of one embodiment of the present invention. FIG. 2A shows an equivalent circuit diagram of the main part during the boosting operation, and FIG.

(A) During boosting operation During the boosting operation, the control signal supplied to the control terminal Tcnt is set to the low level. The low level control signal is inverted to high level by the inverter 113 and supplied to the control circuit 112 and the gate of the MOS transistor Q11.

  The control circuit 112 turns on the MOS transistor Q1 and the MOS transistor Q2 alternately. Further, the MOS transistor Q11 maintains the ON state because the gate is at the high level. When the MOS transistor Q11 is turned on, the gate potential of the MOS transistor Q12 becomes low level, so that the MOS transistor Q12 is turned on.

  Therefore, the peripheral circuits of the MOS transistors Q2, Q11, and Q12 can be represented by an equivalent circuit as shown in FIG.

    (A) When the MOS transistor Q1 is in the on state and the MOS transistor Q2 is in the off state, the current from the power source 11 flows to the ground potential via the coil L and the MOS transistor Q1, and energy is stored in the coil L. At this time, the connection point A becomes the ground potential, and the substrate of the MOS transistor Q2 is connected to the ground terminal Tgnd via the resistor R12 and the MOS transistor Q11, and thus is maintained at the ground potential.

    (B) When the MOS transistor Q1 is off and the MOS transistor Q2 is on, the energy stored in the coil L is output to the output terminal Tout via the MOS transistor Q2.

  At this time, since the potential at the connection point A rises, the potential at the substrate of the MOS transistor Q2 is obtained by dividing the potential at the connection point A by the resistor R11 and the resistor R12.

(B) When boosting is stopped When boosting is stopped, the control signal supplied to the control terminal Tcnt is set to the high level. When the control signal supplied to the control terminal Tcnt becomes high level, the output of the inverter 113 becomes low level.

  When the output of the inverter 113 becomes low level, the control circuit 112 maintains both the MOS transistors Q1 and Q2 in the off state. Further, when the output of the inverter 113 becomes low level, the MOS transistor Q11 is turned off. When the MOS transistor Q11 is turned off, the transistor Q12 is set to the high level via the resistors R11 and R12, so that the transistor Q12 is turned on. At this time, the substrate of the MOS transistor Q2 is maintained at the power supply voltage VDD.

  Therefore, the peripheral circuits of the MOS transistors Q2, Q11, and Q12 can be represented by an equivalent circuit as shown in FIG.

  At this time, all the MOS transistors Q1, Q2, Q11, and Q12 are turned off, so that a resistor R11 and parasitic diodes D1, D2, and D13 appear on the circuit as shown in FIG. The parasitic diodes D2 and D13 are both connected in the opposite direction between the output terminal Tout and the substrate of the transistor Q2. As a result, no current flows from the connection point A to the output terminal Tout.

  According to this embodiment, when the output of the power supply from the output terminal is stopped, the MOS transistor Q2 and the MOS transistor Q11 can be surely turned off. At this time, the parasitic diodes D2 and D13 are also in the reverse direction. Therefore, leakage current can be prevented from flowing from the power supply 11 to the output terminal Tout.

  Further, according to the present embodiment, the substrate potential of the MOS transistor Q2 and the gate voltage of the MOS transistor Q12 can be adjusted by the resistors R11 and R12, so that the design can be facilitated.

It is a circuit block diagram of one Example of this invention. It is an equivalent circuit schematic of the principal part of one Example of this invention. It is a circuit block diagram of an example of the conventional power supply device. It is sectional drawing of MOS transistor Q2.

Explanation of symbols

11 DC power supply L coil, R1, R2, R11, R12 resistance, C1 capacitor Q1, Q2, Q11, Q12 MOS transistor, D1, D2, D13 parasitic diode 100 power supply device, 112 control circuit, 113 inverter

Claims (5)

A coil having an input terminal connected to one end, a first MOS transistor having a drain-source connected between the other end of the coil and the output terminal, and an output voltage output from the output terminal; In a power supply circuit having a control circuit unit for controlling connection of the other end of the coil so that the voltage of the output terminal becomes a predetermined voltage,
A second MOS transistor connected between the substrate of the first MOS transistor and the output terminal;
A first resistor connected between the substrate of the first MOS transistor and the coil;
A second resistor connected between the substrate of the first MOS transistor and the gate of the second MOS transistor;
A power supply device comprising switch means connected between a connection point between the gate of the second MOS transistor and the second resistor and a reference potential. 2. The parasitic diode is formed in the second MOS transistor so as to be in a forward direction from the output terminal side toward the substrate side of the first MOS transistor. Power supply. 3. The power supply device according to claim 2, wherein the second MOS transistor is composed of a P-channel MOS transistor, and a substrate is connected to a substrate of the first MOS transistor. 4. The power supply according to claim 1, wherein the switch means is turned on when power is output from the output terminal, and is turned off when output of power is stopped from the output terminal. apparatus. 5. The power supply device according to claim 1, wherein the switch means is composed of a MOS transistor.

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