JP4274212B2 - Integrated circuit device and electronic device - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  There is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. This display driver is required to reduce the chip size in order to reduce the cost.

  However, the size of a display panel incorporated in a mobile phone or the like is almost constant. Therefore, if a fine process is adopted and the integrated circuit device of the display driver is simply shrunk to reduce the chip size, problems such as difficulty in mounting are caused.

  Some display drivers have a built-in memory (SRAM) for storing image data supplied to the data driver.

Such a display driver with a built-in memory has a problem that the yield of the display driver itself is lowered due to defective cells (defective memory cells, defective bits) existing in the memory cell array. Particularly, in recent years, the number of pixels of the display panel tends to increase, and the number of bits of the memory built in the display driver also tends to increase. If the number of bits of the memory increases in this way, a decrease in yield due to defective cells in the memory cell array becomes a serious problem.
JP 2001-222249 A JP-A-5-36297

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide an integrated circuit device capable of reducing the circuit area and an electronic apparatus including the integrated circuit device.

  In the present invention, the direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is the first direction, and the second side, which is the long side of the integrated circuit device, faces the second side. 1 to Nth circuit blocks (N is an integer greater than or equal to 2) arranged along the first direction, where the direction toward the four sides is the second direction, and the integrated circuit device And an information storage block in which initial adjustment information for initial adjustment of the circuit block is programmed and stored, and the first to Nth circuit blocks include at least one data driver block for driving a data line. And a logic circuit block that controls the data driver block, and the logic circuit block relates to an integrated circuit device disposed between the data driver block and the information storage block.

  According to the present invention, since the first to Nth circuit blocks are arranged along the first direction, the width of the integrated circuit device in the second direction can be reduced, and the integrated circuit device can be reduced. The area can be reduced. In the present invention, initial adjustment information of the circuit block of the integrated circuit device is programmed and stored in the information storage block. Therefore, the integrated circuit device can be operated in an optimum state using this initial adjustment information. In the present invention, the logic circuit block is arranged between the data driver block and the information storage block. Therefore, a signal line wired in a region opposite to the information storage block with respect to the logic circuit block does not overlap with a signal line between the logic circuit block and the information storage block. For this reason, the wiring area of the signal line can be afforded, the wiring efficiency can be improved, and the area of the integrated circuit device can be reduced.

  In the present invention, the information storage block may be arranged adjacent to the logic circuit block.

  According to the present invention, the direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is the first direction, and the second side is the long side of the integrated circuit device. When the direction toward the fourth side is the second direction, the first to Nth circuit blocks (N is an integer of 2 or more) arranged along the first direction, and the integrated circuit device And an information storage block in which initial adjustment information for initial adjustment of the circuit block is programmed and stored, and the first to Nth circuit blocks include at least one data driver for driving a data line The information storage block is related to an integrated circuit device disposed adjacent to the logic circuit block. The information storage block includes a block and a logic circuit block that controls the data driver block.

  According to the present invention, since the first to Nth circuit blocks are arranged along the first direction, the width of the integrated circuit device in the second direction can be reduced, and the integrated circuit device can be reduced. The area can be reduced. In the present invention, initial adjustment information of the circuit block of the integrated circuit device is programmed and stored in the information storage block. Therefore, the integrated circuit device can be operated in an optimum state using this initial adjustment information. In the present invention, the logic circuit block and the information storage block are arranged adjacent to each other. Accordingly, the signal lines between the logic circuit block and the information storage block can be connected by a short path, the wiring efficiency can be improved, and the area of the integrated circuit device can be reduced.

  In the present invention, the first to Nth circuit blocks include at least one scan driver block for driving a scan line, and when a direction opposite to the second direction is a fourth direction, The information storage block may be arranged on the fourth direction side of the scan driver block.

  In this way, the information storage block can be arranged in a region where there is a margin in the wiring of the signal line, so that an increase in chip area due to the wiring region can be minimized.

  The present invention further includes an oscillation circuit block for generating a clock of the integrated circuit device, and in the information storage block, adjustment information of the oscillation frequency of the oscillation circuit block is programmed and stored as the initial adjustment information, The oscillation circuit block may be arranged between the scan driver block and the information storage block.

  In this way, the adjustment information signal lines between the oscillation circuit block and the information storage block can be connected by a short path, thereby preventing an increase in chip area due to the wiring area of these signal lines. it can.

  In the present invention, the information storage block includes first to m-th storage blocks in which first to m-th (m is an integer of 2 or more) initial adjustment information is programmed and stored. May be.

  If the plurality of first to m-th storage blocks are arranged in one place in this way, programming in the initial adjustment information programming step can be facilitated.

  According to the present invention, the information storage block includes a first storage block in which an address of a defective cell in the memory block is programmed and stored as the initial adjustment information, and adjustment information of the oscillation frequency of the oscillation circuit block is the initial storage information. At least two of a second storage block programmed and stored as adjustment information and a third storage block in which reference voltage adjustment information generated by a reference voltage generation circuit is programmed and stored as the initial adjustment information It may be arranged.

  However, the storage block arranged in the information storage block is not limited to such first to third storage blocks.

  In the present invention, the first to Nth circuit blocks include a plurality of memory cells and redundant cells for repairing defective cells, and store at least image data supplied to the data driver block. One memory block may be included, and the address of a defective cell in the memory block may be programmed and stored as the initial adjustment information in the information storage block.

  In this way, it is possible to reduce the deterioration of yield due to the presence of defective cells.

  The present invention also includes a switching control circuit that performs control to switch access to a defective cell to access to a redundant cell, and the switching control circuit is formed in the logic circuit block by automatic placement and wiring. Good.

  In this way, design and layout efficiency can be improved.

  The present invention further includes a switching control circuit that performs control to switch access to a defective cell to access to a redundant cell. In the information storage block, a row address of a defective cell row address and a column address is the defective address. The switching control circuit compares the row address of the display panel access with the defective address stored in the information storage block at the time of display panel access, which is an access for display operation of the display panel, During host access, which is an access to the memory block from the host, the row address of the host access and the row address of the column address are compared with the defective address stored in the information storage block, and a defective cell is obtained. Control to switch access to redundant cell access Unishi may be.

  In this way, focusing on the peculiarity of display panel access, if the address programmed in the information storage block is limited to the row address of the defective cell, the information storage block and the switching control circuit can be reduced in size, and the integrated circuit The yield can be improved while minimizing the increase in the area of the apparatus. In addition, the time required for programming the information storage block can be shortened.

  According to the present invention, the memory block includes a memory cell array in which a plurality of memory cells and redundant cells are arranged, a row address decoder that decodes a row address and selects a word line of the memory cell array, and a column address And a column address decoder for selecting a bit line of the memory cell array.

  In this way, it is possible to realize display panel access and host access that are optimal for the display operation of the display panel.

  According to the present invention, a row address for display panel access is input to the row address decoder during display panel access, and a row address for host access is input to the row address decoder during host access. The column address for host access may be input.

  In this way, switching control to a redundant cell can be realized using the row address input to the row address decoder at the time of display panel access or host access.

  In the present invention, the switching control circuit outputs a switching signal for switching access to a defective cell to access to a redundant cell to the row address decoder. In some cases, the word line of the redundant cell may be selected when the switching signal from the switching control circuit is active.

  In this way, the switching to the redundant cell can be realized by simple control using the switching signal from the switching control circuit.

  In the present invention, the data driver block and the memory block may be arranged adjacent to each other in the first direction.

  In this way, the width of the integrated circuit device in the second direction can be reduced compared with the method of arranging the memory block and the data driver block along the second direction, and a slim and slender integrated circuit device can be obtained. Can be provided.

  In the present invention, image data stored in the memory block is read from the memory block to the data driver block RN times (RN ≧ 2) in one horizontal scanning period, and the memory block includes at least Redundant cells for RN word lines may be provided.

  Thus, if image data is read RN times in one horizontal scanning period, for example, the number of memory cells in the second direction of the memory block can be reduced, and the width of the memory block in the second direction can be reduced. Can be small. If at least RN word line redundant cells are provided, switching from a defective cell to a redundant cell can be properly realized even when a method of reading image data multiple times in one horizontal period is adopted. .

  In the present invention, the information storage block may be a fuse block.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. FIG. 1 shows an example of the circuit configuration of an integrated circuit device (display driver) according to this embodiment. Note that the integrated circuit device of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The display panel includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel can be constituted by an active matrix type panel using switching elements such as TFT and TFD. The display panel may be a panel other than the active matrix system, or a panel other than the liquid crystal panel (organic EL panel or the like).

  The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22.

  The logic circuit 40 (driver logic circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A).

  The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation adjustment data (γ correction data) for adjusting gradation characteristics (γ characteristics) is output to the gradation voltage generation circuit 110, or the power supply voltage is supplied to the power supply circuit 90. Outputs power adjustment data for adjustment. In addition, a write / read process to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28 is controlled. The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory 20 to the display panel side. The host (MPU) interface circuit 46 implements a host interface that accesses the memory 20 by generating an internal pulse for each access from the host. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to the memory 20 using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  The data driver 50 is a circuit that generates a data signal for driving the data lines of the display panel. Specifically, the data driver 50 receives image data (gradation data) from the memory 20, and receives a plurality (for example, 256 levels) of gradation voltages (reference voltages) from the gradation voltage generation circuit 110. Then, a voltage corresponding to the image data is selected from the plurality of gradation voltages and is output to the data line of the display panel as a data signal (data voltage).

  The scan driver 70 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output as a scanning signal (scanning voltage) to each scanning line of the display panel. . The scan driver 70 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 90 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. Then, the voltage obtained by the boosting is supplied to the data driver 50, the scan driver 70, the gradation voltage generation circuit 110, and the like.

  The gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage and supplies it to the data driver 50. Specifically, the gradation voltage generation circuit 110 can include a ladder resistor circuit that divides resistance between the high potential side power source and the low potential side power source and outputs the gradation voltage to the resistance division node. In addition, a gradation register unit in which gradation adjustment data is written, a gradation voltage setting circuit that variably sets (controls) the gradation voltage output to the resistance division node based on the written gradation adjustment data, and the like. Can be included.

2. Elongated Integrated Circuit Device FIG. 2 shows an arrangement example of the integrated circuit device 10. In FIG. 2, the direction from the first side SD1 which is the short side of the integrated circuit device 10 to the third side SD3 facing the first direction D1 is a first direction D1, and the opposite direction of D1 is a third direction D3. . The direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and the opposite direction of D2 is a fourth direction D4. In FIG. 2, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3, but the left side is the third side SD3 and the right side is the first side SD1. May be.

  The integrated circuit device 10 includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F area 12 is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. When the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, the output-side I / F region, the input-side I / F region (first and second I / Os) It is also possible to adopt a configuration in which at least one of (region) 12 and 14 is not provided.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and can include various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, an output transistor for outputting a data signal to the data line or a scanning signal to the scanning line can be included. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like can be included.

  Note that an output-side I / F region or an input-side I / F region along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to. More specifically, the circuit blocks CB1 to CBN can include at least a data driver block and a logic circuit block, and can further include a grayscale voltage generation circuit block. In the case of a built-in memory type, a memory block can be included.

  3A and 3B show detailed examples of the planar layout of the integrated circuit device 10. 3A and 3B, the first to Nth circuit blocks CB1 to CBN are first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense). I is an integer of 2 or more. The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  3A and 3B, scan driver blocks SB1 and SB2 are arranged at both ends of the integrated circuit device 10. It should be noted that only one of these scan driver blocks SB1 and SB2 can be provided, or a modification can be made without providing SB1 and SB2.

  In FIG. 3A, data driver blocks DB1 to DB4 (memory blocks MB1 to MB4) are arranged between the gradation voltage generation circuit block GB and the logic circuit block LB. Further, the gradation voltage generation circuit block GB is arranged between the power supply circuit block PB2 (PB1) and the data driver blocks DB1 to DB4 (memory blocks MB1 to MB4).

  On the other hand, in FIG. 3B, the elongated first power supply circuit block PB1 includes circuit blocks CB1 to CBN (data driver blocks DB1 to DB4) and an input side I / F area 14 (second interface area). In between, it is arranged along the direction D1. The power supply circuit block PB1 is a circuit block having a long side in the D1 direction, a short side in the D2 direction, and a very narrow width in the D2 direction (an elongated circuit block having a width of WB or less). The power supply circuit block PB1 can include a boosting transistor of a boosting circuit that boosts a voltage by a charge pump, a boosting control circuit, and the like.

  3A and 3B, the second power supply circuit block PB2 includes a power supply register portion in which power supply adjustment data for adjusting the power supply voltage is written, and a booster circuit that boosts the voltage by a charge pump. For example, a regulator that adjusts the voltage boosted by the voltage can be included.

  In FIG. 3B, the gradation voltage generation circuit block GB and the logic circuit block LB are not adjacent to each other, and data driver blocks DB1 to DB4 (memory blocks MB1 to MB4) are arranged between GB and LB. Data driver blocks DB1 to DB4 (memory blocks MB1 to MB4) are arranged between the power supply circuit block PB2 and the logic circuit block LB. A gradation voltage generation circuit block GB is arranged between the power supply circuit block PB2 and the data driver blocks DB1 to DB4. It is also possible to modify the grayscale voltage generation circuit block GB and the logic circuit block LB adjacent to each other along the direction D1.

  In FIGS. 3A and 3B, an information storage block ISB such as a fuse block is provided. The logic circuit block LB is arranged between the data driver blocks DB1 to DB4 (memory blocks MB1 to MB4) and the information storage block ISB. In other words, the information storage block ISB is arranged adjacent to the logic circuit block LB, for example, arranged adjacent to the direction D1. It is also possible to perform a modification in which the information storage block ISB is arranged adjacent to the D3 direction side of the logic circuit block LB, or a modification in which the information storage block ISB and the logic circuit block LB are not arranged adjacent to each other.

  In FIG. 3B, the information storage block ISB is arranged on the D4 direction side of the scan driver block SB2. Specifically, the information storage block ISB is arranged in the area on the D1 direction side of the logic circuit block LB and on the D4 direction side of the scan driver block SB2.

  Note that the layout arrangement of the integrated circuit device 10 of the present embodiment is not limited to FIGS. 3 (A) and 3 (B). For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. Further, the memory block, the scan driver block, the power supply circuit block, the gradation voltage generation circuit block, or the like may be omitted. For example, when the memory is not built in, the memory block can be omitted, and when the scan driver can be formed on the glass substrate of the display panel, the scan driver block can be omitted. Further, the gradation voltage generating circuit block can be omitted for a color super twisted nematic (CSTN) panel and a thin film diode (TFD) panel. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  FIG. 4A shows an example of a cross-sectional view of the integrated circuit device 10 along the direction D2. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. The widths W1, WB, and W2 are the widths (maximum widths) of the transistor formation regions (bulk region and active region) in the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14, respectively. Yes, it does not include the bump formation area. W is the width of the integrated circuit device 10 in the direction D2. In this case, for example, a relationship of W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 is established. Alternatively, since W1 + W2 <WB holds, the relationship of W <2 × WB holds.

  In the arrangement method of FIG. 4B, two or more circuit blocks having a wide width in the D2 direction are arranged along the D2 direction. Specifically, the data driver block and the memory block are arranged along the direction D2.

  For example, in FIG. 4B, image data from the host side is written into the memory block. The data driver block converts the digital image data written in the memory block into an analog data voltage, and drives the data lines of the display panel. Accordingly, the signal flow of the image data is in the direction D2. For this reason, in FIG. 4B, the memory block and the data driver block are arranged along the direction D2 in accordance with the flow of this signal.

  Here, the arrangement method of FIG. 4B has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, if a fine process is employed and the integrated circuit device is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced, and mounting becomes difficult due to the narrow pitch.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the arrangement method of FIG. 4B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match in a certain product, these pitches do not match if the configuration of the memory or data driver changes. . If the pitches do not match, it becomes necessary to form a useless wiring region for absorbing the pitch mismatch between the circuit blocks. As a result, the width of the integrated circuit device in the direction D2 is increased, the chip area is increased, and the cost is increased. On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost.

  On the other hand, in the arrangement method shown in FIGS. 2 to 3B, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. In FIG. 4A, a transistor (circuit element) can be disposed under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, the width W in the D2 direction can be narrowed while maintaining the length of the integrated circuit device 10 in the D1 direction, and a slim elongated chip can be realized.

  2 to 3B, the circuit blocks CB1 to CBN are arranged along the direction D1, so that it is possible to easily cope with a change in product specifications. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, even when the number of pixels and the number of gradations of the display panel increase / decrease, it can be dealt with only by increasing / decreasing the number of blocks of the memory blocks and data driver blocks, the number of times of reading out image data in one horizontal scanning period, and the like. For example, when the scan driver can be formed on the display panel side, such as a low-temperature polysilicon TFT panel, it is only necessary to remove the scan driver block from the circuit blocks CB1 to CBN. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, the influence of the circuit block on other circuit blocks can be minimized, so that the design efficiency can be improved.

  2 to 3B, the width (height) of each circuit block CB1 to CBN in the D2 direction can be unified to, for example, the width (height) of the data driver block or the memory block. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, even when the configuration of the gradation voltage generation circuit block or the logic circuit block is changed and the number of transistors is increased or decreased, the length in the D1 direction of the gradation voltage generation circuit block or the logic circuit block is increased or decreased. Yes.

3. Arrangement of Information Storage Block In this embodiment, as shown in FIG. 5A, the integrated circuit device includes first to Nth circuit blocks CB1 to CBN and an information storage block ISB. The circuit blocks CB1 to CBN include data driver blocks DB1 to DBI (at least one data driver block in a broad sense) and a logic circuit block LB.

  Here, the data driver blocks DB1 to DBI are circuits for driving the data lines of the display panel, and the logic circuit block LB is a circuit for controlling these data driver blocks DB1 to DBI. For example, the logic circuit block LB generates various driver control signals for controlling the data driver blocks DB1 to DBI and outputs them to the data driver blocks DB1 to DBI.

  In the information storage block ISB, initial adjustment information (initial setting information) for initial adjustment of circuit blocks (for example, a memory, a data driver, a scan driver, a power supply circuit, a gradation voltage generation circuit, or an oscillation circuit) of the integrated circuit device. , Initial programming information) is programmed and stored. For example, initial adjustment information of various elements (resistance, capacitor, fuse element, etc.) used in the circuit block of the integrated circuit device, initial adjustment information of voltage (reference voltage) and current (reference current) generated in the circuit block, The initial adjustment information of the operation of the circuit block is stored.

  For example, in an inspection process in manufacturing an integrated circuit device, various characteristic information (existence of defective cells, oscillation frequency, reference voltage, AC timing) of the integrated circuit device is measured. Next, initial adjustment information is determined based on the measurement result, and the determined initial adjustment information is programmed and stored in the information storage block ISB. Then, the integrated circuit device operates based on the initial adjustment information programmed in the information storage block ISB, and the integrated circuit device can be operated in an optimum state.

  For example, when a defective cell (defective memory cell) is found in the memory block of the integrated circuit device in the inspection process, the address of the defective cell is programmed in the information storage block ISB as initial adjustment information.

  In the inspection process, the oscillation frequency of the oscillation circuit for generating the clock of the integrated circuit device is measured. Then, adjustment information for adjusting the oscillation frequency to an optimum frequency conforming to the specification is programmed in the information storage block ISB as initial adjustment information.

  In the inspection process, a reference voltage (synonymous with a reference current) generated by a reference voltage generation circuit of the integrated circuit device is measured. Then, adjustment information for adjusting the reference voltage to an optimum voltage (current) conforming to the specification is programmed in the information storage block ISB as initial adjustment information.

  In the inspection process, the AC timing of various signals of the integrated circuit device is measured. Then, adjustment information for adjusting the AC timing of the signal to an optimal timing conforming to the specification is programmed in the information storage block ISB as initial adjustment information.

  For example, a fuse block can be used as the information storage block ISB. The fuse block includes a fuse element, and the initial adjustment information can be programmed by setting the cut or non-cut state of the fuse element. For example, a non-volatile memory such as OTP (One Time PROM) can be used as the information storage block ISB. For example, the initial adjustment information that can be determined at the time of manufacturing the integrated circuit device is programmed in the information storage block ISB configured by a fuse block, OTP, or the like. On the other hand, adjustment information (for example, VCOM voltage) that cannot be determined at the time of manufacturing an integrated circuit device and needs to be adjusted by a manufacturer or the like using the integrated circuit device is stored in an MTP (Multi Time PROM) or the like. You may let them.

  In the present embodiment, as shown in FIG. 5A, the logic circuit block LB is arranged between the data driver blocks DB1 to DBI and the information storage block ISB. Specifically, for example, the data driver blocks DB1 to DBI (memory blocks) are arranged on the D3 direction side of the logic circuit block LB, and the information storage block ISB is arranged on the D1 direction side of the logic circuit block LB.

  For example, in FIG. 5A, the logic circuit block LB needs to output a driver control signal for controlling DB1 to DBI to the data driver blocks DB1 to DBI arranged on the D3 direction side of LB. . Further, when the circuit blocks CB1 to CBN are arranged along the D1 direction as shown in FIG. 5A, it is necessary to wire a large number of global lines along the D1 direction for connecting non-adjacent circuit blocks. There is. Therefore, a large number of signal lines (power supply lines) are wired on the D3 direction side of the logic circuit block LB, and there is no room for wiring.

  On the other hand, the initial adjustment information stored in the information storage block ISB is mainly used by the logic circuit block LB. Therefore, a large number of signal lines are also wired between the logic circuit block LB and the information storage block ISB.

  Therefore, for example, if the information storage block ISB is arranged on the D3 direction side of the LB without arranging the information storage block ISB on the D1 direction side of the logic circuit block LB, the number of signal lines wired on the ISB is very large. turn into. That is, if the information storage block ISB is arranged between the data driver blocks DB1 to DBI and the logic circuit block LB, the number of wirings such as global lines that need to be wired along the direction D1 increases, and there is a margin in the wiring area. Disappear. As a result, the wiring efficiency deteriorates due to the increase in the number of signal lines wired along the direction D1, and the width W in the direction D2 of the integrated circuit device may increase.

  5A, the logic circuit block LB is arranged between the data driver blocks DB1 to DBI and the information storage block ISB, and the information storage block ISB is arranged on the D1 direction side of the logic circuit block LB. Is done. Accordingly, a global line or the like wired on the D3 direction side of the logic circuit block LB does not overlap with a signal line between the logic circuit block LB and the information storage block ISB. For this reason, a wiring area such as a global line can be afforded and wiring efficiency can be improved. As a result, the width W in the direction D2 of the integrated circuit device can be reduced, and a slim and slender chip can be realized.

  If the information storage block ISB is arranged between the data driver blocks DB1 to DBI and the logic circuit block LB, it is necessary to wire a global line or the like on the information storage block ISB, and the initial adjustment information to the information storage block ISB is stored. There are situations where programming becomes difficult. For example, when a fuse block is adopted as the information storage block ISB, there is a problem that a signal line cannot be wired on the fuse element.

  In this regard, in the arrangement method of FIG. 5A, the information storage block ISB is arranged in a region on the D1 direction side of the logic circuit block LB, which is a region where signal lines are not densely packed. Therefore, it is not necessary to wire a global line or the like on the information storage block ISB. Therefore, even when a fuse block is employed as the information storage block ISB, it is possible to easily comply with the restriction of prohibiting wiring of signal lines on the fuse element.

  In addition, when the circuit blocks CB1 to CBN are arranged along the direction D1 as shown in FIGS. 3A and 3B, there is no room in the arrangement area of the data driver block and the memory block. Therefore, when the information storage block ISB is arranged in the arrangement area of the data driver block or the memory block, the width W in the D2 direction of the integrated circuit device is increased, and it is difficult to realize a slim and slender chip. On the other hand, when the information storage block ISB is arranged in the area on the D3 direction side of the data driver block or the memory block (block area of the power supply circuit or the gradation voltage generation circuit), it is between the information storage block ISB and the logic circuit block LB. This signal line must be routed along the direction D1 over a long distance. For this reason, the wiring efficiency of the signal lines along the direction D1 is deteriorated, and the width W of the integrated circuit device in the direction D2 is increased.

  In this regard, according to the arrangement method of FIG. 5A, since the distance of the signal line between the information storage block ISB and the logic circuit block LB can be shortened, the wiring efficiency can be improved and a slim and slender chip can be realized. It becomes possible.

  As shown in FIG. 5B, the information storage block ISB may be arranged adjacent to the logic circuit block LB. Specifically, the information storage block ISB and the logic circuit block LB are adjacently arranged along the direction D1.

  According to the arrangement method of FIG. 5B, the signal line between the information storage block ISB and the logic circuit block LB can be connected by a short path, and the length of the signal line can be minimized. Therefore, it is possible to prevent an increase in chip area due to the wiring area of these signal lines, and to reduce the area of the integrated circuit device.

  Further, when the address of the defective cell is programmed as the initial adjustment information in the information storage block ISB, the switching control circuit SC for performing control for switching the access to the defective cell to the access to the redundant cell is required. According to the arrangement method shown in FIG. 5A, the switching control circuit SC can be easily formed in the logic circuit block LB by automatic arrangement / wiring. That is, the switching control circuit SC can be formed as a part of the gate array of the logic circuit block LB. In this way, there is no need to manually place and wire the switching control circuit SC, and the design and layout can be made more efficient. In addition, it is possible to easily cope with the case where the number of bits of the address of a defective cell changes due to a change in specifications.

  In FIG. 5B, the information storage block ISB is adjacently disposed on the D1 direction side of the logic circuit block LB. However, the information storage block ISB may be adjacently disposed on the D3 direction side of the logic circuit block LB. In this case, the signal line between the logic circuit block LB and the information storage block ISB (for example, the signal line of the defective address DFA) can be wired by a local line below the global line. Accordingly, it is possible to minimize the increase in chip area due to the wiring region.

  FIG. 6A shows a detailed layout example of the information storage block ISB. In FIG. 6A, the circuit blocks CB1 to CBN include at least one scan driver block SB2 for driving the scan lines of the display panel. When the direction opposite to the D2 direction is the D4 direction, the information storage block ISB is arranged on the D4 direction side of the scan driver block SB2. Specifically, the information storage block ISB is arranged in a region on the D1 direction side of the logic circuit block LB and on the D4 direction side of the scan driver block SB2.

  For example, in FIG. 6A, the scan driver (gate driver) pads are arranged using the empty space on the D2 direction side of the scan driver block SB2 and the logic circuit block LB as indicated by B1. Therefore, it is necessary to wire a large number of signal lines corresponding to the number of scanning lines (gate lines) of the display panel between the scanning driver pad arrangement region shown in B1 and the scanning driver block SB2. Therefore, there is no margin in the wiring area of the signal lines in the area on the D2 direction side of the scanning driver block SB2.

  Further, as indicated by B2 in FIG. 6A, it is necessary to wire and input a large number of signal lines from pads arranged in the input-side I / F region 14 to the logic circuit block LB. Therefore, there is no margin in the signal line wiring region even in the region on the D4 direction side of the logic circuit block LB.

  Further, as indicated by B3 in FIG. 6A, in the region on the D3 direction side of the logic circuit block LB, it is necessary to wire a large number of global lines along the D1 direction. Accordingly, there is no margin in the wiring area of the signal lines even in the area on the D3 direction side of the logic circuit block LB.

  Therefore, in FIG. 6A, not the area indicated by B1, B2, and B3 where there is no margin in the signal line wiring, but the area on the D4 direction side of the scan driver block SB2 (area on the D1 direction side of the logic circuit block LB). In addition, an information storage block ISB is arranged. Thereby, the information storage block ISB can be arranged in an area where there is a margin in the wiring of the signal line. Therefore, an increase in chip area due to the wiring region can be minimized. In addition, it is not necessary to wire global lines or the like on the information storage block ISB. For example, even when a fuse block is used as the ISB, the restriction of prohibition of signal line wiring on the fuse element can be easily observed. .

  FIG. 6B shows a more detailed layout example of the information storage block ISB. In FIG. 6B, the integrated circuit device includes an oscillation circuit block OSC for generating a clock. In the information storage block ISB, the adjustment information of the oscillation frequency of the oscillation circuit block OSC is programmed and stored as initial adjustment information. An oscillation circuit block OSC is arranged between the scan driver block SB2 and the information storage block ISB.

  For example, FIG. 7 shows a circuit configuration of the oscillation circuit block OSC. The oscillation circuit block OSC includes an NAND circuit NAC1, inverter circuits INVC1, INVC2, a variable resistor RC1, and a capacitor CC1, and constitutes an oscillation loop. The oscillation starts when the enable signal ENB input to the NAND circuit NAC1 is set to the H level.

  In FIG. 7, for example, the oscillation frequency changes by adjusting the resistance value of the variable resistor RC1. In this case, adjustment information for obtaining an optimum oscillation frequency is programmed and stored in the information storage block ISB. As a result, variations in the oscillation frequency due to variations in the manufacturing process can be minimized.

  When the oscillation circuit block OSC is arranged as shown in FIG. 6B, the adjustment information signal line between the oscillation circuit block OSC and the information storage block ISB can be connected by a short path. Therefore, it is possible to prevent an increase in chip area due to the wiring region of these signal lines. Further, the clock generated by the oscillation circuit block OSC can be supplied to the logic circuit block LB through a short path, and the layout efficiency can be improved.

  In FIG. 6B, the information storage block ISB is programmed and stored with first to third initial adjustment information (first to mth initial adjustment information in a broad sense; m is an integer of 2 or more). First to third storage blocks ISB1 to ISB3 (first to mth storage blocks in a broad sense) are arranged.

  Here, in the first storage block ISB1, the address DFA of the defective cell in the memory block is programmed and stored as initial adjustment information. In the second storage block ISB2, adjustment information of the oscillation frequency of the oscillation circuit block OSC is programmed and stored as initial adjustment information. In the third storage block ISB3, the adjustment information of the reference voltage (VREF) generated by the reference voltage generation circuit is programmed and stored as initial adjustment information. In FIG. 6B, at least two storage blocks ISB1 to ISB3 are arranged in the information storage block ISB.

  If the plurality of storage blocks ISB1 to ISB3 are arranged in one place in this way, programming in the initial adjustment information programming step is facilitated. As a result, the programming process time can be shortened, and the cost of the integrated circuit device can be reduced. Taking the case where the information storage block ISB is a fuse block as an example, when the storage blocks of a plurality of fuse elements are distributed and arranged in different locations on the integrated circuit device, the location of the fuse elements is specified by the inspection device There is a problem that becomes difficult. According to the arrangement method of FIG. 6B, such a problem can be solved. For example, in the case of a method of cutting a fuse element with a laser, according to the arrangement method of FIG. 15B, the distance that the laser device must move (scan) in the chip for cutting the fuse element is set. Since it can be shortened, the time required for cutting the fuse element can be shortened.

  FIG. 8 shows a configuration example of a power supply circuit (power supply circuit block). This power supply circuit includes primary to quaternary boost circuits 31 to 34 (primary to K order boost circuits in a broad sense, K is an integer of 2 or more), regulator 35, VCOM generation circuit 36, control circuit 37, and reference voltage generation. A circuit 41 is included. Here, the primary to quaternary booster circuits 31 to 34 (primary to Kth booster circuit in a broad sense) are respectively a primary to quaternary booster transistor (primary to Kth booster transistor in a broad sense) and a primary. Including primary to quaternary boost control circuits CT1 to CT4 (primary to K-order boost control circuits in a broad sense), primary to quartic boost operations are performed. The primary to quaternary boost control circuits CT1 to CT4 are circuits for controlling the primary to quaternary boost circuits 31 to 34, and supply boost clocks to the primary to quaternary boost transistors. The VCOM generation circuit 36 generates and outputs a VCOM voltage supplied to the counter electrode of the display panel. The control circuit 37 controls the power supply circuit.

  The control circuit 37 includes a power supply register unit 38 (index register) and an address decoder 39. The power supply register unit 38 has a plurality of registers. Then, the power supply adjustment data set by the data signal from the logic circuit is written into the register specified by the register address of the address signal from the logic circuit (logic circuit block). The address decoder 39 decodes the address signal from the logic circuit and outputs a register address signal corresponding to the address signal.

  The reference voltage generation circuit 41 generates a reference voltage (reference current) for generating a power supply voltage for the logic circuit and the gradation voltage generation circuit. In this case, adjustment information for obtaining an optimum reference voltage is programmed and stored in the information storage block ISB. This makes it possible to minimize variations in the reference voltage due to variations in the manufacturing process.

4). 4.1 Switching Control to Redundant Cell 4.1 Storing Row Address of Defective Cell FIG. 9 shows a circuit configuration example of the integrated circuit device (display driver) of this embodiment. The integrated circuit device of this embodiment includes a data driver block DB, a memory block MB, a switching control circuit SC, and an information storage block ISB. The integrated circuit device according to the present embodiment is not limited to the configuration shown in FIG. 9, and various modifications such as omitting some of the components or adding other components are possible.

  The data driver block DB is a circuit for driving data lines of a display panel such as an LCD (Liquid Crystal Display). The memory block MB stores image data supplied to the data driver block DB. In FIG. 9, the number of data driver blocks DB and memory blocks MB is one, but a plurality of data driver blocks DB and memory blocks MB may be provided.

  The memory cell array MA of the memory block MB is provided with a plurality of memory cell arrays and redundant cells (redundant memory cells, redundant bits) for repairing the defective cell DFM. For example, in FIG. 9, a defective cell DFM exists in the word line WLM (Mth word line, where M is a natural number). That is, the memory cell connected to the word line WLM is a defective cell. In FIG. 9, redundant cells are provided on the word line WLJ (Jth word line, J is a natural number). That is, the memory cell connected to the word line WLJ is a redundant cell. If a defective cell DFM such as that shown in FIG. 9 occurs due to a defect in the manufacturing process, the yield can be improved by replacing the defective cell DFM with a spare redundant cell.

  In the information storage block ISB, the address of the defective cell DFM of the memory block MB is programmed and stored as a defective address DFA. That is, when a defective cell is detected by the tester during the manufacture of the integrated circuit device, the defective address DFA is stored in a storage device such as a tester. The stored defective address DFA is programmed and stored in the information storage block ISB.

  For example, a fuse block can be used as the information storage block ISB. The fuse block is provided with a plurality of fuse elements. Then, the defective address DFA is programmed depending on whether the fuse element is cut or not. That is, the defective address DFA is programmed by cutting or not cutting the fuse element based on the defective address DFA obtained in the inspection at the time of manufacturing the integrated circuit device. As this fuse element, for example, an element cut (fused) by laser or high voltage application can be adopted. The information storage block ISB only needs to be programmed and stored with initial adjustment information for initial adjustment of the circuit block of the integrated circuit device, and a storage block other than the fuse block can also be adopted.

  The switching control circuit SC performs control for switching access to the defective cell DFM (access to the word line of the defective cell) to access to the redundant cell (access to the word line of the redundant cell). Specifically, the switching control circuit SC outputs a switching signal JX for switching access to the defective cell DFM to access to the redundant cell to the memory block MB (row address decoder). Then, for example, when the memory block MB is accessed to select the word line WLM of the defective cell DFM and the switching signal JX becomes active, this access is replaced with an access to select the word line WLJ of the redundant cell. By doing so, not the defective cell DFM but the redundant cell is selected, and the yield can be improved.

  In the present embodiment, the information storage block ISB has a row address (first address) of a row address (first address in a broad sense) and a column address (second address in a broad sense) of a defective cell. It is programmed and stored as a defective address DFA. That is, not all addresses of defective cells are stored, but only row addresses (addresses for selecting word lines of defective cells) that are part of the addresses are stored.

  Then, the switching control circuit SC receives the defective address DFA stored in the information storage block ISB. At the time of LCD access (display panel access in a broad sense), the LCD row address RAL for LCD access is compared with the defective address DFA stored in the information storage block ISB. Then, for example, it is detected whether or not the LCD row address RAL matches the defective address DFA.

  On the other hand, during MPU access (host access in a broad sense), MPU access MPU row address RAC (first address) and MPU column address CAC (second address) of row address RAC (first address), The defective address DFA stored in the information storage block ISB is compared. Then, for example, it is detected whether the MPU row address RAC matches the defective address DFA. Then, the switching control circuit SC performs control to switch the access to the defective cell DFM to the access to the redundant cell according to the comparison result (match detection result). For example, when the LCD row address RAL or MPU row address RAC matches the defective address DFA, the switching signal JX is activated.

  The LCD access (LCD read) is an access for a display operation of a display panel such as an LCD. That is, it is an access for reading the image data stored in the memory block MB and supplying it to the data driver block DB and displaying the image on the display panel by driving the data line of the data driver block DB.

  On the other hand, MPU access (host access) is an access to the memory block MB from a host such as an MPU (CPU, application processor, baseband engine). Examples of the MPU access include an access for writing image data displayed on the display panel to the memory block MB, and an access for reading image data written in the memory block MB to the MPU side.

  Next, the operation of this embodiment will be described with reference to FIGS. 10 (A) and 10 (B). When the LCD is accessed in FIG. 10A, the switching control circuit SC compares the defective address DFA from the information storage block ISB with the LCD row address RAL. When the defective address DFA matches the LCD row address RAL, the switching signal JX is made active (asserted).

  During this LCD access, the LCD row address RAL is input to the memory block MB. In the memory block MB, word lines corresponding to the LCD row address RAL are sequentially selected, and image data is sequentially read from the memory cells corresponding to the selected word line. The read image data is input to the data driver block DB. The data driver block DB performs D / A conversion of the image data input from the memory block MB, and outputs a data voltage (grayscale voltage) obtained by the D / A conversion to the data line, thereby displaying the display panel. Drive the data line.

  At this time, when the switching signal JX from the switching control circuit SC becomes active, the memory block MB reads the image data from the redundant cell instead of the defective cell DFM. Specifically, instead of selecting the word line WLM (Mth word line) of the defective cell DFM, the word line WLJ (Jth word line) of the redundant cell is selected, and the image data stored in the redundant cell Is read. That is, the memory block MB (row address decoder) selects a normal word line corresponding to the LCD row address RAL when the switching signal JX is inactive. On the other hand, when the switching signal JX becomes active, the word line WLJ of the redundant cell is selected instead of the word line WLM corresponding to the LCD row address RAL.

  At the MPU access in FIG. 10B, the switching control circuit SC compares the defective address DFA from the information storage block ISB with the MPU row address RAC. When the defective address DFA matches the MPU row address RAC, the switching signal JX is activated.

  During this MPU access, the MPU row address RAC and the MPU column address CAC are input to the memory block MB. In the memory block MB, a word line corresponding to the MPU row address RAC and a bit line corresponding to the MPU column address CAC are selected. Then, image data from the MPU side (logic circuit) is written into the memory cells corresponding to the selected word line and bit line. Alternatively, the image data stored in the memory cell corresponding to the selected word line and bit line is read out to the MPU side (logic circuit).

  At this time, when the switching signal JX from the switching control circuit SC becomes active, in the memory block MB, image data is written to or read from the redundant cell instead of the defective cell DFM. Specifically, instead of selecting the word line WLM of the defective cell DFM, the word line WLJ of the redundant cell is selected, and image data is written to or read from the redundant cell. That is, when the switching signal JX is inactive, the memory block MB selects a normal word line corresponding to the MPU row address RAC and a bit line corresponding to the MPU column address CAC. On the other hand, when the switching signal JX becomes active, the word line WLJ of the redundant cell is selected instead of the word line corresponding to the MPU row address RAC, and the image of the redundant cell corresponding to the selected word line WLJ and bit line is selected. Write data and read image data.

  According to the above embodiment, only the row address of the defective cell DFM is stored in the information storage block ISB, and the column address need not be stored. In other words, the information storage block ISB stores an address (first address) commonly used for both the LCD access and the MPU access, and an address (not commonly used for the LCD access and the MPU access). The second address is not stored. Accordingly, since the amount of information stored in the information storage block ISB is reduced, the information storage block ISB can be reduced in size. Further, since the switching control circuit SC performs only the row address comparison processing and does not need to perform the column address comparison processing, the switching control circuit SC can be reduced in size.

  Further, only the row address needs to be programmed in the information storage block ISB, and the column address need not be programmed. Therefore, it is possible to reduce the time of the programming process at the time of manufacturing the integrated circuit device and to reduce the cost of the integrated circuit device. For example, when the information storage block ISB is a fuse block, the number of fuse elements to be cut is reduced, so that the time for the fuse cutting process can be shortened and the manufacturing cost of the integrated circuit device can be reduced.

  In particular, this embodiment pays attention to the fact that the address commonly used for LCD access and MPU access is a row address, and realizes switching from a defective cell to a redundant cell by storing and comparing the row address. There is a feature. That is, it is not necessary to specify a column address when accessing the LCD where the display operation of the display panel is performed. On the other hand, at the time of MPU access, both the row address and the column address are used. Therefore, in the present embodiment, by storing and comparing only row addresses that are commonly used for both LCD access and MPU access, the scale of the integrated circuit device and the lengthening of the programming process are minimized. The yield is improved while suppressing.

4.2 Memory Block FIG. 11 shows a configuration example of the memory block MB. Memory block MB includes a memory cell array MA, a row address decoder RD, and a column address decoder CD. Furthermore, a sense amplifier block SAB, a write / read circuit WRC, and a control circuit CC can be included.

  A plurality of memory cells are arranged in a matrix in the memory cell array MA. In addition, redundant cells for at least one word line are arranged.

  A row address decoder RD (MPU / LCD row address decoder) decodes a row address and selects a word line WL of the memory cell array MA. Specifically, the LCD row address RAL is input to the row address decoder RD when the LCD is accessed (data driver output). The row address decoder RD decodes the input LCD row address RAL and selects a word line. On the other hand, during MPU access, which is access by a host such as an MPU, CPU, or image processing controller, the MPU row address RAC is input to the row address decoder RD. The row address decoder RD decodes the input MPU row address RAC and selects a word line.

  A column address decoder CD (MPU column address decoder) decodes a column address and selects a bit line BL of the memory cell array. Specifically, at the time of MPU access, the MPU column address CAC is decoded and a bit line is selected.

  The sense amplifier block SAB amplifies the image data signal read from the memory cell array MA when accessing the LCD (when outputting the data driver block), and outputs the image data to the data driver block.

  A write / read circuit WRC (MPU write / read circuit) writes image data to a memory cell (memory cell to be accessed) in which a bit line is selected among memory cells of the memory cell array MA during MPU access. Control to read out image data. The write / read circuit WRC can include a sense amplifier for reading image data. The control circuit CC controls each circuit block in the memory block MB.

  As described above, the switching control circuit SC in FIG. 9 outputs the switching signal JX (JXL, JXC) for switching the access to the defective cell DFM to the access to the redundant cell to the row address decoder RD in FIG. . The row address decoder RD selects the redundant cell word line WLJ instead of the defective cell DFM word line WLM when the switching signal JX from the switching control circuit SC is active during LCD access or MPU access. .

  12A and 12B show signal waveform examples at the time of LCD access and MPU access. At the time of LCD access in FIG. 12A, after setting the LCD row address RAL, the signal RLINE which is the LCD read signal is raised from L level to H level. Thereby, the read operation of the LCD is performed, and for example, image data RDL for one line (one word line) is read from the memory cell array MA and output to the data driver block.

  At the time of writing MPU access in FIG. 12B, write data WD, bank signal BANK, MPU column address CAC and MPU row address RAC are set, and read / write switching signal RXW is kept at L level. In this state, by raising the MPU enable signal CEN from the L level to the H level, the image data WD (for example, 24-bit data) is written into the memory cell array MA. On the other hand, when reading MPU access, the read / write switching signal RXW is kept at H level and the same operation as that at the time of writing is performed, whereby the image data RD is read from the memory cell array MA.

4.3 Memory Block Division In FIG. 13, the memory of the display driver is divided into a plurality of memory blocks MB1, MB2, MB3, MB4 (first to Ith memory blocks in a broad sense; I is an integer of 2 or more). It is divided. Each of these memory blocks MB1, MB2, MB3, and MB4 is provided with a plurality of memory cells and redundant cells for repairing a defective cell.

  Memory blocks MB1 to MB4 include row address decoders RD1 to RD4 (first to I-th row address decoders in a broad sense). Further, it includes column address decoders CD1 to CD4 and memory cell arrays MA1 to MA4 (first to Ith memory cell arrays in a broad sense). Each of these memory cell arrays MA1 to MA4 is provided with a plurality of memory cells and redundant cells for at least one word line.

  In FIG. 13, a defective cell DFM is present in the memory block MB2 (Kth memory block in a broad sense, 1 ≦ K ≦ I) among the memory blocks MB1 to MB4 (first to Ith memory blocks). Yes. The defective address (row address) of the defective cell DFM is programmed in the information storage block ISB of FIG.

  In FIG. 13, not only the row address decoder RD2 (Kth row address decoder in a broad sense) of the memory block MB2 in which the defective cell DFM exists but also a row address decoder other than RD2 at the time of LCD access (LCD read). RD1, RD3, and RD4 also select the word line WLJ of the redundant cell. That is, when the LCD row address RAL corresponding to the defective address is input and the switching signal JX becomes active, not only the row address decoder RD2, but also the other row address decoders RD1, RD3, and RD4 select the word line WLJ of the redundant cell. To do.

  In this way, when switching from the defective cell to the redundant cell, the word line WLJ of the redundant cell is selected in all the memory blocks MB1 to MB4 divided into blocks, and in the switching process to the redundant cell, The word line selection control can be simplified.

  FIGS. 14A and 14B are diagrams for explaining the operation of the memory blocks MB1 to MB4 during MPU access. In the row address decoders RD1 to RD4 of the memory blocks MB1 to MB4, bank signals BANK1, BANK2, BANK3, BANK4 (first to first bank signals in a broad sense; BANK3 and BANK4 are illustrated) for selecting a memory block. Is omitted).

  In FIG. 14A, the bank signal BANK1 (Lth bank signal in a broad sense; 1 ≦ L ≦ I) becomes active and the memory block MB1 (Lth memory block in a broad sense) is selected during host access. Has been. In this case, the row address decoder RD1 (Lth row address decoder) selects the word line WLJ of the redundant cell. That is, when the MPU row address RAC corresponding to the defective address is input and the switching signal JX becomes active, the row address decoder RD1 selects the word line WLJ of the redundant cell. The column address decoder CD1 selects a bit line BL corresponding to the MPU column address CAC.

  On the other hand, the row address decoders RD2, RD3, and RD4 other than the row address decoder RD1 do not select any of the word lines of the memory cells and the redundant cells. That is, when the LCD is accessed in FIG. 13, all the row address decoders RD1 to RD4 select the word line WLJ, but in FIG. 14A, the bank signal BANK1 becomes active and the selected memory block MB1 is selected. Only the row address decoder RD1 selects a word line.

  In FIG. 14B, during host access, the bank signal BANK2 (Lth bank signal) becomes active, and the memory block MB2 (Lth memory block) is selected. In this case, the row address decoder RD2 (Lth row address decoder) selects the word line WLJ of the redundant cell. That is, when the MPU row address RAC corresponding to the defective address is input and the switching signal JX becomes active, the row address decoder RD2 selects the word line WLJ of the redundant cell. The column address decoder CD2 selects the bit line BL corresponding to the MPU column address CAC.

  On the other hand, the row address decoders RD1, RD3, and RD4 other than the row address decoder RD2 do not select any of the word lines of the memory cells and the redundant cells. That is, in FIG. 14B as well, as in FIG. 14A, only the row address decoder RD2 of the memory block MB2 selected by the bank signal BANK2 being active selects the word line.

  14A and 14B, when a defective cell DFM exists in the word line WLM of the memory block MB2, the memory cells of the word line WLM are stored in all the memory blocks MB1 to MB4. The image data to be written can be correctly written in the redundant cell of the word line WLJ. That is, when image data is written in the redundant cell of the word line WLJ in the memory block MB2 when the memory block MB1 in FIG. End up.

  If writing is performed by the method shown in FIGS. 14A and 14B during MPU access, the correct image data is stored in the memory block MB1 even when word lines are selected by the method shown in FIG. ~ Read from MB4 and output to data driver block. Therefore, the word line selection control in the switching process to the redundant cell can be simplified.

4.4 Information Storage Block and Switching Control Circuit FIGS. 15 and 16 show configuration examples of the information storage block ISB and the switching control circuit SC. The information storage block ISB and the switching control circuit SC are not limited to the configurations shown in FIGS. 15 and 16, and various modifications such as omitting some of the components or adding other components are possible. is there.

  The switching control circuit SC in FIG. 15 includes a first coincidence detection circuit DET1 and a second coincidence detection circuit DET2. Here, the coincidence detection circuit DET1 receives the LCD row address RAL and the defective address DFA from the information storage block ISB. Then, coincidence detection between the LCD row address RAL and the defective address DFA is performed, and when they coincide, the first switching signal JXL is activated.

  The coincidence detection circuit DET2 receives the MPU row address RAC and the defective address DFA from the information storage block ISB. Then, coincidence detection between the MPU row address RAC and the defective address DFA is performed, and when they coincide, the second switching signal JXC is activated.

  In FIG. 15, the LCD row address RAL, MPU row address RAC, and defective address DFA are 9 bits, but the number of bits of these addresses is arbitrary.

  In FIG. 15, in the information storage block ISB, use instruction information for instructing whether or not to use a redundant cell (redundant cell switching control) is programmed and stored. The coincidence detection circuit DET1 receives the instruction signal UD corresponding to the use instruction information stored in the information storage block ISB. When the instruction signal UD does not instruct the use of the redundant cell, the coincidence detection circuit DET1 outputs the switching signal JXL. Activate. That is, the switching signal JXL is fixed to an inactive level regardless of whether the LCD row address RAL and the defective address DFA match.

  The coincidence detection circuit DET2 receives the instruction signal UD from the information storage block ISB, and deactivates the switching signal JXC when the instruction signal UD does not instruct the use of the redundant cell. That is, the switching signal JXC is fixed to an inactive level regardless of whether the MPU row address RAC and the defective address DFA match.

  By using such an instruction signal UD, whether or not to perform switching control to a redundant cell can be programmed, for example, in the information storage block ISB at the time of manufacturing the integrated circuit device, and convenience can be improved.

  FIG. 16 is a detailed configuration example of the information storage block ISB and the switching control circuit SC. The information storage block ISB includes fuse elements FH0 to FH8 and FL0 to FL8 for generating defective addresses DFA0 to DFA8. Further, it includes a fuse element FU for generating the instruction signal UD and a high-resistance resistor RU. The information storage block ISB can include a protective element such as a diode in addition to these fuse elements.

  When fuse element FU is cut (melted), node NV of instruction signal UD is set to the H level which is the VDD level. As a result, the operations of the coincidence detection circuits DET1 and DET2 and the switching process to the redundant cell are enabled. On the other hand, when fuse element FU is not cut, node NV of instruction signal UD is set to the L level which is the VSS level. As a result, the operations of the coincidence detection circuits DET1 and DET2 and the switching process to the redundant cell are disabled. For example, when the instruction signal UD becomes L level, the switching signals JXL and JXC, which are the outputs of the AND circuits ANA2 and ANA4 of the coincidence detection circuits DET1 and DET2, are fixed at the L level and become inactive regardless of the coincidence detection result. Is set.

  When the node NV is set to the H level, the fuse elements FH0 to FH8 and FL0 to FL8 are cut or not cut, so that the signal levels of the defective addresses DFA0 to DFA8 are set, and the defective address is programmed. . For example, when fuse elements FH0 to FH8 are cut, defective addresses DFA0 to DFA8 are set to L level. On the other hand, when fuse elements FL0-FL8 are cut, defective addresses DFA0-DFA8 are set to the H level.

  The coincidence detection circuit DET1 includes transfer gates (switching elements in a broad sense) T0A to T8A, T0B to T8B, and AND circuits ANA1 and ANA2. The transfer gates T0A to T8A are turned on when the signals of the defective addresses DFA0 to DFA8 are at the H level. On the other hand, the transfer gates T0B to T8B are turned on when the signals of the defective addresses DFA0 to DFA8 are at the L level. The signals of the LCD row addresses RAL0 to RAL8 are input to the sources of the transfer gates T0A to T8A, and the inverted signals of the LCD row addresses RAL0 to RAL8 are input to the sources of the transfer gates T0B to T8B.

  The drains of the transfer gates T0A and T0B are commonly connected to the node NAB0, the drains of the transfer gates T1A and T1B are commonly connected to the node NAB1, and the drains of the transfer gates T8A and T8B are commonly connected to the node NAB8. The nodes NAB0 to NAB8 are connected to the input of the AND circuit ANA1, the output of the ANA1 is connected to the input of the AND circuit ANA2, and the ANA2 outputs the switching signal JXL for LCD access.

  The coincidence detection circuit DET2 includes transfer gates T0C to T8C, T0D to T8D, and AND circuits ANA3 and ANA4. The transfer gates T0C to T8C are turned on when the signals of the defective addresses DFA0 to DFA8 are at the H level. On the other hand, the transfer gates T0B to T8B are turned on when the signals of the defective addresses DFA0 to DFA8 are at the L level. The signals of MPU row addresses RAC0 to RAC8 are input to the sources of transfer gates T0C to T8C, and the inverted signals of MPU row addresses RAC0 to RAC8 are input to the sources of transfer gates T0D to T8D. The drains of transfer gates T0C and T0D are commonly connected to node NCD0, the drains of transfer gates T1C and T1D are commonly connected to node NCD1,..., And the drains of transfer gates T8C and T8D are commonly connected to node NCD8. The nodes NCD0 to NCD8 are connected to the input of the AND circuit ANA3, the output of the ANA3 is connected to the input of the AND circuit ANA4, and the ANA4 outputs the switching signal JXC for MPU access.

  For example, it is assumed that the defective addresses DFA0 to DFA8 programmed in the information storage block ISB are (101111110) = (HLHHHHHHL). This is realized by cutting the fuse elements FL0, FH1, FL2 to FL7, FH8.

  Thus, when the defective addresses are DFA0 to DFA8 = (HLHHHHHHL), the transfer gates T0A, T1B, T2A to T7A, and T8B are turned on in the coincidence detection circuit DET1. Therefore, when the LCD row address is RAL0 to RAL8 = (HLHHHHHHL) and coincides with the defective address DFA0 to DFA8, the nodes NAB0 to NAB8 are at the H level. As a result, the output node NAB of the AND circuit ANA1 becomes H level, and when the instruction signal UD is H level, the switching signal JXL becomes H level (active).

  When the defective addresses are DFA0 to DFA8 = (HLHHHHHHL), the transfer gates T0C, T1D, T2C to T7C, and T8D are turned on in the coincidence detection circuit DET2. Accordingly, when the MPU row address is RAC0 to RAC8 = (HLHHHHHHL) and coincides with the defective addresses DFA0 to DFA8, the nodes NCD0 to NCD8 are at the H level. As a result, the output node NCD of the AND circuit ANA3 becomes H level, and when the instruction signal UD is H level, the switching signal JXC becomes H level (active).

4.5 Row Address Decoder FIG. 17 shows a configuration example of the row address decoder RD of FIG. The row address decoder RD includes an LCD pre-row decoder PRL, an MPU pre-row decoder PRC, and a row decoder RDEC. Also included are NAND circuits NAB1, NAB2, NOR circuit NOB1, inverter circuits INVB1, INVB2, INVB3, INVB4, INVB5, and the like.

  The LCD pre-row decoder PRL receives the LCD row address RAL, performs pre-decoding processing, and outputs a pre-decode signal PDL to the row decoder RDEC. The MPU pre-row decoder PRC receives the MPU row address RAC, performs pre-decoding processing, and outputs a pre-decode signal PDC to the row decoder RDEC. The row decoder RDEC receives the predecode signals PDL and PDC and the switching signal JXLC, performs decoding processing, and performs normal memory cell word lines WL1 to WLP (first to Pth word lines) and redundant cell word lines WLJ. Make a selection.

  If the first switching signal JXL for LCD access becomes active (H level) during LCD access, the predecode processing of the LCD pre-row decoder PRL is disabled. When the switching signal JXL becomes active, the switching signal JXLC input to the row decoder RDEC becomes active. When the predecode processing of the LCD prerow decoder PRL is thus disabled and the switching signal JXLC becomes active, the row decoder RDEC selects the word line WLJ of the redundant cell. Thereby, the word line selection method at the time of LCD access explained in FIG. 13 is realized.

  When the MPU access second switching signal JXC is active (H level) and the bank signal BANK for memory block selection is active (H level), the MPU pre-row decoder PRC predecode processing Is set to disabled. Even when the bank signal BANK is inactive (L level), the predecode processing of the MPU prerow decoder PRC is set to disable. When the switching signal JXC and the bank signal BANK are activated, the switching signal JXLC input to the row decoder RDEC is activated. When the predecode processing of the MPU prerow decoder PRC is set to disable and the switching signal JXLC becomes active as described above, the row decoder RDEC selects the word line WLJ of the redundant cell. Thereby, the word line selection method at the time of MPU access described with reference to FIGS. 14A and 14B is realized.

5. Global Wiring Method In order to reduce the width of the integrated circuit device in the D2 direction, it is necessary to efficiently wire signal lines and power supply lines between circuit blocks arranged along the D1 direction. For this reason, it is desirable to wire signal lines and power supply lines between circuit blocks by a global wiring method.

  Specifically, in this global wiring method, between adjacent circuit blocks of the first to Nth circuit blocks CB1 to CBN, a wiring layer (I is an integer of 3 or more) lower than the wiring layer (I is an integer of 3 or more). For example, local lines formed of first to fourth aluminum wiring layers ALA, ALB, ALC, ALD) are wired. On the other hand, between non-adjacent circuit blocks among the first to Nth circuit blocks CB1 to CBN, a global line formed of a wiring layer (for example, the fifth aluminum wiring layer ALE) of the Ith layer or higher is adjacent. Wiring is performed along the direction D1 on the circuit blocks interposed between the circuit blocks that are not.

  FIG. 18 shows an example of global line wiring. In FIG. 18, driver global lines GLD for supplying driver control signals from the logic circuit block LB to the data driver blocks DB1 to DB3 are wired on the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3. That is, the driver global line GLD formed by the fifth aluminum wiring layer ALE, which is the top metal, is substantially straight along the D1 direction from the logic circuit block LB to the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3. Wired to The driver control signals supplied by these driver global lines GLD are buffered by the buffer circuits BF1 to BF3 and input to the data drivers DR1 to DR3 arranged on the D2 direction side of the buffer circuits BF1 to BF3. The

  In FIG. 18, a memory global line GLM for supplying at least a write data signal (or an address signal and a memory control signal) from the logic circuit block LB to the memory blocks MB1 to MB3 is wired along the direction D1. The That is, the memory global line GLM formed of the fifth aluminum wiring layer ALE is wired from the logic circuit block LB along the direction D1.

  More specifically, in FIG. 18, repeater blocks RP1 to RP3 are arranged corresponding to the memory blocks MB1 to MB3. These repeater blocks RP1 to RP3 include a buffer that buffers at least a write data signal (or an address signal or a memory control signal) from the logic circuit block LB and outputs the buffered data to the memory blocks MB1 to MB3. As shown in FIG. 18, the memory blocks MB1 to MB3 and the repeater blocks RP1 to RP3 are adjacently disposed along the direction D1.

  For example, when a write data signal, an address signal, and a memory control signal from the logic circuit block LB are supplied to the memory blocks MB1 to MB3 using the memory global line GLM, if these signals are not buffered, the signal rises. Waveform and falling waveform are dull. As a result, there is a possibility that the data writing time to the memory blocks MB1 to MB3 becomes long or a writing error occurs.

  In this regard, if repeater blocks RP1 to RP3 as shown in FIG. 18 are arranged adjacent to each memory block MB1 to MB3, for example, on the D1 direction side, these write data signals, address signals, and memory control signals are transmitted to the repeater blocks RP1 to RP1. The data is buffered by RP3 and input to each of the memory blocks MB1 to MB3. As a result, it is possible to reduce the dullness of the rising waveform and falling waveform of the signal, and it is possible to realize proper data writing to the memory blocks MB1 to MB3.

  In FIG. 18, the integrated circuit device includes a gradation voltage generation circuit block GB for generating gradation voltages. A gradation global line GLG for supplying the gradation voltage from the gradation voltage generation circuit block GB to the data driver blocks DB1 to DB3 is wired along the direction D1. That is, the gradation global line GLG formed by the fifth aluminum wiring layer ALE is wired from the gradation voltage generation circuit block GB along the direction D1. The gradation voltage supply lines GSL1 to GSL3 for supplying the gradation voltages from the gradation global line GLG to the data drivers DR1 to DR3 are wired along the direction D2 in each of the data drivers DR1 to DR3.

  Further, in FIG. 18, the memory global line GLM is wired along the direction D1 between the gradation global line GLG and the driver global line GLD.

  That is, in FIG. 18, the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3 are arranged along the direction D1. By wiring the driver global line GLD along the D1 direction from the logic circuit block LB through the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3, the wiring efficiency can be greatly improved.

  Further, it is necessary to supply the grayscale voltage from the grayscale voltage generation circuit block GB to the data drivers DR1 to DR3. For this purpose, the grayscale global line GLG is wired along the direction D1.

  On the other hand, address signals, memory control signals, and the like are supplied to the row address decoders RD1 to RD3 through the memory global line GLM. Therefore, the memory global line GLM is preferably wired near the row address decoders RD1 to RD3.

  In this regard, in FIG. 18, the memory global line GLM is wired between the gradation global line GLG and the driver global line GLD. Accordingly, an address signal, a memory control signal, and the like from the memory global line GLM can be supplied to the row address decoders RD1 to RD3 through a short path. Further, the gradation global line GLG can be arranged substantially straight along the direction D1 above the memory global line GLM. Accordingly, it is possible to perform wiring without crossing the global lines GLG, GLM, and GLD by using a single aluminum wiring layer ALE, and wiring efficiency can be improved.

  In FIG. 18, the gradation transfer line GTL is wired along the D1 direction on the data driver blocks DB1 to DB3 by the global line. In this case, the gradation adjustment data is transferred in a time division manner on the gradation transfer line GTL. Therefore, the number of gradation transfer lines GTL, which are global lines, can be reduced as compared with a method in which gradation adjustment data is transferred at a time using a parallel transfer line. Therefore, it is possible to cope with a case where the number of global lines GLD, GLM, and GLG for drivers, memories, and gradations increases and there is no room for global line wiring. Therefore, it is possible to prevent a situation in which the width of the integrated circuit device in the direction D2 increases due to the number of gradation transfer lines GTL, and the area of the integrated circuit device can be reduced.

  In FIG. 18, the power supply transfer line PTL is wired along the D1 direction on the data driver blocks DB1 to DB3 by a global line. The logic circuit block LB transfers the power supply adjustment data to the power supply circuit block PB in a time division manner via the power supply transfer line PTL.

6). Block Division As shown in FIG. 19A, the display panel has a number of pixels in the vertical scanning direction (data line direction) of VPN = 320, and a number of pixels in the horizontal scanning direction (scanning line direction) of HPN = 240. Is a QVGA panel. Further, it is assumed that the bit number PDB of image (display) data for one pixel is 8 bits for each of R, G, and B, and PDB = 24 bits. In this case, the number of bits of image data necessary for displaying one frame of the display panel is VPN × HPN × PDB = 320 × 240 × 24 bits. Therefore, the memory of the integrated circuit device stores image data for at least 320 × 240 × 24 bits. The data driver also displays HPN = 240 data signals (data signals corresponding to 240 × 24 bits of image data) every horizontal scanning period (each scanning period of one scanning line). Output to the panel.

  In FIG. 19B, the data driver is divided into DBN = 4 data driver blocks DB1 to DB4. The memory is also divided into MBN = DBN = 4 memory blocks MB1 to MB4. That is, for example, four driver macro cells DMC1, DMC2, DMC3, and DMC4 in which a data driver block, a memory block, and a pad block are converted into macro cells are arranged along the direction D1. Accordingly, each data driver block DB1 to DB4 outputs HPN / DBN = 240/4 = 60 data signals to the display panel every horizontal scanning period. Each of the memory blocks MB1 to MB4 stores (VPN × HPN × PDB) / MBN = (320 × 240 × 24) / 4 bits of image data.

7). Reading multiple times in one horizontal scanning period In FIG. 19B, each of the data driver blocks DB1 to DB4 is 60 lines in one horizontal scanning period (60 × 3 = 180 assuming that R, G, and B are three lines). Output data signal. Therefore, it is necessary to read image data corresponding to 240 data signals for each horizontal scanning period from the memory blocks MB1 to MB4 corresponding to DB1 to DB4.

  However, if the number of bits of image data to be read for each horizontal scanning period increases, it is necessary to increase the number of memory cells (sense amplifiers) arranged in the D2 direction. As a result, the width W in the direction D2 of the integrated circuit device is increased, and the slimming of the chip is prevented. In addition, the word line WL becomes long, which causes a problem of WL signal delay.

  In order to solve such a problem, the image data stored in each of the memory blocks MB1 to MB4 is transferred from the memory blocks MB1 to MB4 to the data driver blocks DB1 to DB4 a plurality of times in one horizontal scanning period ( It is desirable to adopt a method of reading (RN times).

  For example, in FIG. 20, as indicated by A1 and A2, the memory access signal MACS (word selection signal) becomes active (high level) only RN = 2 times in one horizontal scanning period. Thus, image data is read from each memory block to each data driver block RN = 2 times in one horizontal scanning period. Then, the latch circuits of the data drivers DRa and DRb provided in the data driver block in FIG. 21 latch the read image data based on the latch signals LATa and LATb indicated by A3 and A4. The multiplexers of the data drivers DRa and DRb multiplex the latched image data, and the DRa and DRb D / A converters perform D / A conversion of the multiplexed image data. Then, the output circuits of the data drivers DRa and DRb output the data signals DATAa and DATAb obtained by the D / A conversion as indicated by A5 and A6. Thereafter, as shown at A7, the scanning signal SCSEL inputted to the gate of the TFT of each pixel of the display panel becomes active, and the data signal is inputted and held in each pixel of the display panel.

  In FIG. 20, the image data is read twice in the first horizontal scanning period, and the data signals DATAa and DATAb are output to the data signal output line in the same first horizontal scanning period. However, the image data is read and latched twice in the first horizontal scanning period, and the data signals DATAa and DATAb corresponding to the latched image data are supplied to the data signal output lines in the next second horizontal scanning period. It may be output. FIG. 20 shows the case where the number of times of reading RN = 2, but RN ≧ 3 may be possible.

  According to the method shown in FIG. 20, as shown in FIG. 21, image data corresponding to 30 data signals is read from each memory block, and each data driver DRa, DRb outputs 30 data signals. To do. As a result, 60 data signals are output from each data driver block. As described above, in FIG. 20, it is only necessary to read image data corresponding to 30 data signals from each memory block in one reading. Therefore, the number of memory cells and sense amplifiers in the direction D2 in FIG. 21 can be reduced as compared with the method of reading only once in one horizontal scanning period. As a result, the width of the integrated circuit device in the direction D2 can be reduced, and a slim and slender chip can be realized. In particular, the length of one horizontal scanning period is about 52 μsec in the case of QVGA. On the other hand, the memory read time is, for example, about 40 nsec, which is sufficiently shorter than 52 μsec. Therefore, even if the number of readings in one horizontal scanning period is increased from one to a plurality of times, the influence on the display characteristics is not so great.

  FIG. 19A shows a display panel of QVGA (320 × 240). If the number of readings in one horizontal scanning period is set to RN = 4, for example, it corresponds to a display panel of VGA (640 × 480). It is also possible to increase the degree of design freedom.

  The plurality of readings in one horizontal scanning period may be realized by a first method in which a row address decoder (word line selection circuit) selects a plurality of different word lines in each memory block in one horizontal scanning period. Alternatively, the same word line in each memory block may be realized by a second method in which a row address decoder (word line selection circuit) selects a plurality of times in one horizontal scanning period. Alternatively, it may be realized by a combination of both the first and second methods.

  In FIG. 21, the data driver block includes a plurality of data drivers DRa and DRb arranged side by side along the direction D1. Each data driver DRa, DRb includes a plurality of driver cells.

  When the word line WL1a of the memory block is selected and the first image data is read from the memory block as shown by A1 in FIG. 20, the data driver DRa is read based on the latch signal LATa shown by A3. The image data is latched, and the latched image data is multiplexed. Then, D / A conversion of the multiplexed image data is performed, and a data signal DATAa corresponding to the first read image data is output as indicated by A5.

  On the other hand, when the word line WL1b of the memory block is selected and the second image data is read from the memory block as shown by A2 in FIG. 20, the data driver DRb reads based on the latch signal LATb shown by A4. The latched image data is latched, and the latched image data is multiplexed. Then, D / A conversion of the multiplexed image data is performed, and a data signal DATAb corresponding to the second read image data is output as indicated by A6.

  In this way, each data driver DRa, DRb outputs 30 data signals corresponding to 30 pixels, so that 60 data signals corresponding to 60 pixels in total are output. It becomes like this.

  If a plurality of data drivers DRa and DRb are arranged (stacked) along the D1 direction as shown in FIG. 21, the width W in the D2 direction of the integrated circuit device is increased due to the size of the data driver. It can prevent the situation. The data driver has various configurations depending on the type of the display panel. Also in this case, according to the method of arranging a plurality of data drivers along the direction D1, data drivers having various configurations can be efficiently laid out. FIG. 21 shows a case where the number of data drivers arranged in the direction D1 is two, but the number of arranged data drivers may be three or more.

  In FIG. 21, each data driver DRa, DRb includes 30 (Q) driver cells arranged side by side along the direction D2. In FIG. 21, the number of pixels in the horizontal scanning direction of the display panel (when the data lines of the display panel are driven by sharing with a plurality of integrated circuit devices) It is assumed that HPN is used, the number of blocks of the data driver block (number of block divisions) is DBN, and the number of input image data input to the driver cell in one horizontal scanning period is IN. Note that IN is equal to the number of read times RN of the image data in one horizontal scanning period described with reference to FIG. In this case, the number Q of driver cells can be expressed as Q = HPN / (DBN × IN). In the case of FIG. 21, since HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30.

  Further, it is assumed that the number of subpixels in the horizontal scanning direction of the display panel is HPNS, and the multiplexing number of multiplexers of each driver cell is NDM. Then, the number Q of driver cells arranged along the direction D2 can be expressed as Q = HPNS / (DBN × IN × NDM). In the case of FIG. 21, since HPNS = 240 × 3 = 720, DBN = 4, IN = 2, and NDM = 3, Q = 720 / (4 × 2 × 3) = 30. For example, when the number of multiplexing increases and NDM = 6, Q = 720 / (4 × 2 × 6) = 15.

  Further, when the width (pitch) in the D2 direction of the driver cell is WD and the width in the D2 direction of the peripheral circuit portion (buffer circuit, wiring region, etc.) included in the data driver block is WPCB, the first to Nth The width WB (maximum width) of the circuit blocks CB1 to CBN in the D2 direction can be expressed as Q × WD ≦ WB <(Q + 1) × WD + WPCB. Further, when the width in the D2 direction of the peripheral circuit portion (row address decoder RD, wiring area, etc.) included in the memory block is WPC, it can be expressed as Q × WD ≦ WB <(Q + 1) × WD + WPC.

  Further, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN (= DBN), and data is read from the memory block in one horizontal scanning period. Assume that the number of times of reading image data is RN. In this case, the number P of sense amplifiers (sense amplifiers that output 1-bit image data) arranged in the direction D2 in the sense amplifier block SAB is expressed as P = (HPN × PDB) / (MBN × RN). be able to. In the case of FIG. 21, since HPN = 240, PDB = 24, MBN = 4, and RN = 2, P = (240 × 24) / (4 × 2) = 720. Note that the number P is the number of effective sense amplifiers corresponding to the number of effective memory cells, and does not include the number of ineffective sense amplifiers such as sense amplifiers for dummy memory cells.

  Further, it is assumed that the number of subpixels in the horizontal scanning direction of the display panel is HPNS, and the multiplexing number of multiplexers of each driver cell is NDM. Then, the number P of sense amplifiers arranged along the direction D2 can be expressed as P = (HPNS × PDB) / (MBN × RN × NDM). In the case of FIG. 21, since HPNS = 240 × 3 = 720, PDB = 24, MBN = 4, RN = 2, and NDM = 3, P = (720 × 24) / (4 × 2 × 3) = 720.

  When the width (pitch) in the D2 direction of each sense amplifier included in the sense amplifier block SAB is WS, the width WSAB in the D2 direction of the sense amplifier block SAB (memory block) is WSAB = P × WS. Can be represented. The width WB (maximum width) in the D2 direction of the circuit blocks CB1 to CBN is P × WS ≦ WB <(P + PDB) when the width in the D2 direction of the peripheral circuit portion included in the memory block is WPC. It can also be expressed as × WS + WPC.

8). Arrangement of Redundant Cells Corresponding to Multiple Readings When a method of reading image data RN times (RN ≧ 2) in one horizontal scanning period as shown in FIG. 20, at least RN word lines are included in the memory block. It is desirable to provide redundant cells for a minute.

  For example, in FIGS. 22A and 22B, the memory of the display driver is divided into a plurality of memory blocks MB1, MB2, MB3, and MB4. Each of these memory blocks MB1, MB2, MB3, and MB4 is provided with a plurality of memory cells and at least two (RN in a broad sense) word line (WLJa, WLJb) redundant cells.

  Then, at the time of the first reading (A1 in FIG. 20) in one horizontal scanning period in the LCD access in FIG. 22A, the word line WLMa is selected. In this case, in FIG. 22A, a defective cell DFM exists in the word line WLMa of the memory block MB2 among the memory blocks MB1 to MB4, and the defective address of the defective cell DFM is programmed in the information storage block ISB. Has been.

  Therefore, when the LCD row address RAL corresponding to the word line WLMa of the defective cell DFM is input and the switching signal JX becomes active, the row address decoders RD1 to RD4 do not select the word line WLMa, but instead select the word line WLMa. WLJa will be selected.

  On the other hand, the word line WLMb (for example, the word line adjacent to WLMa) is selected at the second reading (A2 in FIG. 20) in one horizontal scanning period in the LCD access in FIG. Also in this case, the switching signal JX becomes active in this embodiment. Therefore, the row address decoders RD1 to RD4 select the word line WLJb of the redundant cell instead of selecting the word line WLMb.

  As described above, if a plurality of (RN) word line redundant cells are provided in a memory block, even when a method of reading image data multiple times in one horizontal period is adopted, a defective cell is changed to a redundant cell. The switching control can be properly realized. Note that FIGS. 22A and 22B have been described by taking the case of RN = 2 as an example, but even when RN ≧ 3, the same method as in FIGS. 22A and 22B is used. Switching control from a defective cell to a redundant cell can be realized.

9. Electronic Device FIGS. 23A and 23B show examples of an electronic device (electro-optical device) including the integrated circuit device 10 of the present embodiment. Note that the electronic device may include components other than those illustrated in FIGS. 23A and 23B (for example, a camera, an operation unit, a power supply, or the like). The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  In FIGS. 23A and 23B, the host device 410 is, for example, an MPU or a baseband engine. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, the image processing controller 420 in FIG. 23B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 23A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 23B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, at least once, together with different terms having a broader meaning or the same meaning (first address, second address, display panel access, host access, first interface area, second interface area, etc.) The described terms (row address, column address, LCD access, MPU access, output side I / F area, input side I / F area, etc.) shall be replaced with the different terms in any part of the specification or drawings. Can do.

  Further, for example, the switching method to the redundant cell described in FIGS. 9 to 17 and the like is applied not only to the integrated circuit device having the configuration described with reference to FIGS. Applicable. For example, the present invention can also be applied to an integrated circuit device having the arrangement configuration shown in FIG. In this embodiment, the case where the first address is a row address and the second address is a column address has been described, but the present invention is not limited to this. For example, the first and second addresses may be addresses having substantially the same functions as the row address and the column address.

6 is a circuit configuration example of an integrated circuit device. 4 is an example of an arrangement configuration of an integrated circuit device. 3A and 3B are planar layout examples of the integrated circuit device. 4A and 4B are examples of cross-sectional views of the integrated circuit device. 5A and 5B are explanatory diagrams of an arrangement method of information storage blocks. 6A and 6B are explanatory diagrams of an arrangement method of information storage blocks. Configuration example of an oscillation circuit block. The structural example of a power supply circuit. 2 is a configuration example of an integrated circuit device including an information storage block and a switching control circuit. 10A and 10B are explanatory diagrams of the operation of the integrated circuit device of FIG. The structural example of a memory block. 12A and 12B show examples of signal waveforms for LCD access and MPU access. Explanatory drawing of the word line selection method at the time of LCD access. 14A and 14B are explanatory diagrams of a word line selection method at the time of MPU access. 2 shows a configuration example of a switching control circuit and an information storage block. 2 shows a detailed configuration example of a switching control circuit and an information storage block. 2 shows a configuration example of a row address decoder. Explanatory drawing of a global wiring method. 19A and 19B are explanatory diagrams of a block division method for a memory and a data driver. Explanatory drawing of the method of reading image data in multiple times in 1 horizontal scanning period. Data driver and driver cell arrangement example. 22A and 22B are explanatory diagrams of a method of providing redundant cells for a plurality of word lines. FIG. 23A and FIG. 23B are configuration examples of electronic devices.

Explanation of symbols

DB data driver block, MB memory block, SC switching control circuit,
ISB information storage block, MA memory cell array, RD row address decoder,
CD column address decoder, WLMa, WLJ word line, BL bit line,
DET1, DET2 coincidence detection circuit, CB1 to CBN, first to Nth circuit blocks,
LB logic circuit block, SB1, SB2 scan driver block,
OSC oscillation circuit block,
10 integrated circuit device, 12 output side I / F area, 14 input side I / F area, 20 memory,
22 memory cell array, 24 row address decoder,
26 column address decoder, 28 write / read circuit,
31 primary booster circuit, 32 secondary booster circuit, 33 tertiary booster circuit, 34 quaternary booster circuit,
35 regulator, 36 VCOM generation circuit, 37 control register,
38 power register, 39 address decoder, 40 logic circuit,
41 reference voltage generation circuit, 42 control circuit, 44 display timing control circuit,
46 host interface circuit, 48 RGB interface circuit,
50 data drivers, 70 scan drivers, 90 power supply circuits,
110 gradation voltage generation circuit, 400 display panel, 410 host device,
420 Image processing controller

Claims (17)

The direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is defined as the first direction, and the second side, which is the long side of the integrated circuit device, is directed to the fourth side facing the first side. The first direction to the Nth circuit block (N is an integer of 2 or more) arranged along the first direction,
An information storage block in which initial adjustment information for performing initial adjustment of the circuit block of the integrated circuit device is programmed and stored;
The first to Nth circuit blocks are:
At least one data driver block for driving the data lines;
A logic circuit block for controlling the data driver block,
The integrated circuit device, wherein the logic circuit block is arranged between the data driver block and the information storage block. In claim 1,
The integrated circuit device, wherein the information storage block is disposed adjacent to the logic circuit block. The direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is defined as the first direction, and the second side, which is the long side of the integrated circuit device, is directed to the fourth side facing the first side. The first direction to the Nth circuit block (N is an integer of 2 or more) arranged along the first direction,
An information storage block in which initial adjustment information for performing initial adjustment of the circuit block of the integrated circuit device is programmed and stored;
The first to Nth circuit blocks are:
At least one data driver block for driving the data lines;
A logic circuit block for controlling the data driver block,
The information storage block, an integrated circuit device characterized by being adjacently disposed along the first direction for the logic circuit block. In any one of Claims 1 thru | or 3,
The first to Nth circuit blocks are:
Including at least one scan driver block for driving the scan lines;
The integrated circuit device, wherein when the direction opposite to the second direction is a fourth direction, the information storage block is arranged on the fourth direction side of the scan driver block. In claim 4,
Including an oscillation circuit block for generating a clock of the integrated circuit device;
In the information storage block, the adjustment information of the oscillation frequency of the oscillation circuit block is programmed and stored as the initial adjustment information,
An integrated circuit device, wherein the oscillation circuit block is arranged between the scan driver block and the information storage block. In any one of Claims 1 thru | or 5,
The information storage block includes
An integrated circuit device comprising first to m-th storage blocks in which first to m-th (m is an integer of 2 or more) initial adjustment information is programmed and stored. In claim 6,
The information storage block includes
A first storage block in which an address of a defective cell in the memory block is programmed and stored as the initial adjustment information; and a second storage in which adjustment information of the oscillation frequency of the oscillation circuit block is programmed and stored as the initial adjustment information. An integrated circuit device comprising: a storage block; and at least two of a third storage block in which adjustment information of a reference voltage generated by a reference voltage generation circuit is programmed and stored as the initial adjustment information. In any one of Claims 1 thru | or 7,
The first to Nth circuit blocks are:
Including at least one memory block having a plurality of memory cells and a redundant cell for repairing a defective cell and storing image data supplied to the data driver block;
The integrated circuit device, wherein the information storage block is programmed and stored with an address of a defective cell in the memory block as the initial adjustment information. In claim 8,
Including a switching control circuit that performs control to switch access to a defective cell to access to a redundant cell;
The integrated circuit device, wherein the switching control circuit is formed in the logic circuit block by automatic placement / wiring. In claim 8 or 9,
Including a switching control circuit that performs control to switch access to a defective cell to access to a redundant cell;
In the information storage block,
Of the row address and column address of the defective cell, the row address is stored as the defective address,
The switching control circuit includes:
When accessing the display panel, which is an access for display operation of the display panel, the row address of the display panel access is compared with the defective address stored in the information storage block, and the memory block is accessed from the host. During a certain host access, the row address of the host access and the row address of the column address are compared with the defective address stored in the information storage block, and the access to the defective cell is switched to the access to the redundant cell. An integrated circuit device characterized by performing control. In claim 10,
The memory block is
A memory cell array in which a plurality of memory cells and redundant cells are arranged;
A row address decoder for decoding a row address and selecting a word line of the memory cell array;
An integrated circuit device comprising: a column address decoder for decoding a column address and selecting a bit line of the memory cell array. In claim 11,
When accessing the display panel, the row address decoder receives a row address for display panel access,
An integrated circuit device, wherein a host access row address is input to the row address decoder, and a host access column address is input to the column address decoder during host access. In claim 11 or 12,
The switching control circuit includes:
A switching signal for switching access to a defective cell to access to a redundant cell is output to the row address decoder,
The integrated circuit device, wherein the row address decoder selects a word line of a redundant cell when the switching signal from the switching control circuit is active during display panel access or host access. In claims 8 to 13,
The integrated circuit device, wherein the data driver block and the memory block are arranged adjacent to each other in the first direction. In any one of Claims 8 thru | or 14.
Image data stored in the memory block is read from the memory block to the data driver block RN times (RN ≧ 2) in one horizontal scanning period,
The integrated circuit device, wherein the memory block is provided with redundant cells corresponding to at least RN word lines. In any one of Claims 1 thru | or 15,
The integrated circuit device, wherein the information storage block is a fuse block. An integrated circuit device according to any one of claims 1 to 16,
A display panel driven by the integrated circuit device;
An electronic device comprising:

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