JP2007043036A - Integrated circuit device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a slim, thin and long integrated circuit device hardly causing electrostatic discharge damage, and electronic equipment incorporating the same. <P>SOLUTION: The integrated circuit device 10 includes a pad, an electrostatic discharge protection element electrically connected to the pad, and a transistor to be protected with the electrostatic discharge protection element. The pad is arranged on an upper layer of an impurity region so that the pad overlaps one part or entire part of the impurity region forming the electrostatic protective element. A conductive layer for electrically connecting the impurity region to a gate electrode of the transistor, or a conductive layer for electrically connecting the impurity region to a drain region of the transistor is electrically connected to the pad and is electrically connected to the impurity region via a contact hole of an interlayer insulation film provided on the impurity region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  There is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. This display driver is required to reduce the chip size in order to reduce the cost.

  However, the size of a display panel incorporated in a mobile phone or the like is almost constant. Therefore, if a fine process is adopted and the integrated circuit device of the display driver is simply shrunk to reduce the chip size, problems such as difficulty in mounting are caused.

  The integrated circuit device includes a plurality of pads, and an electrostatic protection element is connected to each pad. Therefore, if the layout area of the pad and the electrostatic protection element can be reduced, the chip size can be reduced.

However, if the internal transistor is easily electrostatically destroyed in order to reduce the layout area, the reliability of the integrated circuit device is lowered.
JP 2001-222249 A

  The present invention has been made in view of the technical problems as described above, and an object thereof is to provide a slim and long integrated circuit device and an electronic apparatus including the same.

  Another object of the present invention is to provide an integrated circuit device and an electronic device including the integrated circuit device that are less susceptible to electrostatic breakdown and can reduce the chip size.

  The present invention includes a pad, an electrostatic protection element electrically connected to the pad, and a transistor protected by the electrostatic protection element, and overlaps a part or all of an impurity region constituting the electrostatic protection element. As described above, the pad is disposed on the impurity region, and the conductive layer for electrically connecting the impurity region and the gate electrode of the transistor, or the impurity region and the drain region of the transistor are electrically connected. A conductive layer to be electrically connected to the pad and related to an integrated circuit device electrically connected to the impurity region through a contact hole of an interlayer insulating film provided on the impurity region; To do.

  In the integrated circuit device according to the present invention, the electrostatic protection element may be a gate control transistor, and the impurity region may be a drain region of the gate control transistor.

  According to any one of the above inventions, when static electricity is applied to the pad, the static electricity can surely flow into the conductive layer, and the path to the impurity region electrically connected to the conductive layer through the contact hole Impedance can be lowered. As a result, static electricity can be surely released to the impurity region. For this reason, it is not necessary to cause electrostatic breakdown of the transistor. In addition, a configuration in which a resistance element for electrostatic protection inserted to protect the transistor can be omitted, and when the number of pads is large, the layout area of the integrated circuit device can be greatly reduced.

  The present invention is also an integrated circuit device having an electrostatic protection element and a transistor protected by the electrostatic protection element, wherein the first impurity region constituting the electrostatic protection element and the second impurity constituting the transistor are provided. A first contact hole on the first impurity region and a second contact hole on the second impurity region. The first contact hole is formed on the first impurity region and the second impurity region. A first interlayer insulating film including: a first conductive layer formed on the first interlayer insulating film and electrically connected to the first impurity region through the first contact hole; A second interlayer insulating film formed on one conductive layer and having a third contact hole; and a metal layer as a pad, wherein the metal layer passes through the third contact hole at least through the third contact hole. The second impurity region is electrically connected to the conductive layer and overlapped with a part or all of the first impurity region, and the second impurity region is connected to the first conductive region via the second contact hole. The present invention relates to an integrated circuit device that is electrically connected to a layer.

  In the integrated circuit device according to the present invention, the electrostatic protection element may be a gate control transistor, and the first impurity region may be a drain region of the gate control transistor.

  According to any one of the above inventions, the pad is electrically connected to the first conductive layer, and the first conductive layer is electrically connected to the first impurity region constituting the electrostatic protection element via the first contact hole. Connected. The first conductive layer is electrically connected to the second impurity region of the transistor. As a result, the static electricity applied to the pad can be surely released to the first impurity region of the static electricity protection element, and the internal transistor can be protected. Further, even if the resistance element for electrostatic protection is omitted, static electricity can be surely released.

  The present invention is also an integrated circuit device having an electrostatic protection element and a transistor protected by the electrostatic protection element, wherein the first impurity region constituting the electrostatic protection element is formed, and the first A first interlayer insulating film formed on the impurity region and the gate electrode of the transistor and having a first contact hole on the first impurity region and a second contact hole on the gate electrode; A first conductive layer formed on the first interlayer insulating film and electrically connected to the first impurity region via the first contact hole; and a third contact hole formed on the first conductive layer. A metal layer that is a pad, and the metal layer is electrically connected to the first conductive layer through at least the third contact hole. Both are related to an integrated circuit device that is arranged so as to overlap a part or all of the first impurity region, and in which the gate electrode is electrically connected to the first conductive layer through the second contact hole. To do.

  According to the present invention, the pad is electrically connected to the first conductive layer, and the first conductive layer is electrically connected to the first impurity region constituting the electrostatic protection element through the first contact hole. The The first conductive layer is electrically connected to the gate electrode of the transistor. As a result, the static electricity applied to the pad can be surely released to the first impurity region of the static electricity protection element, and the internal transistor can be protected. Further, even if the resistance element for electrostatic protection is omitted, static electricity can be surely released.

  In the integrated circuit device according to the present invention, the second impurity region or the gate electrode is connected to the first conductive layer via one or a plurality of conductive layers formed on the second interlayer insulating film. It may be electrically connected.

  According to the present invention, since the impedance of the path of static electricity to the transistor can be further increased, static electricity can be more reliably released to the first impurity of the electrostatic protection element.

  In the integrated circuit device according to the present invention, the transistor may be connected in parallel with the electrostatic protection element.

  In the integrated circuit device according to the present invention, the direction from the first side which is the short side of the integrated circuit device to the third side facing the first side is the first direction, and the first side which is the long side of the integrated circuit device. The first to Nth circuit blocks (N is an integer of 2 or more) arranged along the first direction when the direction from the second side to the fourth side facing the second side is the second direction. ), A first interface region provided along the fourth side on the second direction side of the first to Nth circuit blocks, and the second of the first to Nth circuit blocks. And a second interface region provided along the second side on the fourth direction side opposite to the direction, and the electrostatic protection element and the transistor are formed in the first or second interface region The first to Nth circuit blocks are data lines. Including at least one data driver block for driving and circuit blocks other than the data driver block, and the first interface region, the first to Nth circuit blocks, and the second interface region. When the width in the direction 2 is W1, WB, and W2, respectively, the width W in the second direction of the integrated circuit device may be W1 + WB + W2 ≦ W <W1 + 2 × WB + W2.

  In the present invention, the first to Nth circuit blocks include a data driver block and a circuit block other than the data driver block. Then, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 holds for the widths W1, WB, and W2 of the first interface region, the first to Nth circuit blocks, and the second interface region. According to the integrated circuit device in which such a relational expression is satisfied, the width in the second direction can be reduced while ensuring the width of the circuit block in the second direction (without making an excessive flat layout), and slim. And an elongated integrated circuit device can be provided. This makes it possible to achieve both ease of mounting and cost reduction of the apparatus. Further, since the circuit block is not excessively flat, the layout design is facilitated, and the development period of the apparatus can be shortened.

  In the integrated circuit device according to the present invention, the width W of the integrated circuit device in the second direction may be W <2 × WB.

  In this way, it is possible to reduce the width of the integrated circuit device in the second direction while ensuring a large width in the second direction of the first to Nth circuit blocks. Further, by arranging the electrostatic protection element in the lower layer of the pad as in the present invention, the width of the integrated circuit device in the second direction can be greatly reduced. Therefore, W <2 × WB can be easily established, and an even slimmer integrated circuit device can be provided.

  In the integrated circuit device according to the present invention, the first interface region is arranged on the second direction side of the data driver block without any other circuit block, and the second interface region is The data driver block may be arranged on the fourth direction side without any other circuit block.

  In this way, the width of the first to Nth circuit blocks in the second direction can be set based on the width of the data driver block in the second direction. And at least in the portion where the data driver block exists, only one circuit block (data driver block) exists in the second direction, so that the layout of the data driver block is elongated without being excessively flattened. The integrated circuit device can be realized.

  In the integrated circuit device according to the present invention, each of the data drivers included in the data driver block outputs a data signal corresponding to the image data for one pixel, and is Q pieces arranged along the second direction. When the width of the driver cell including the driver cell in the second direction is WD, the width WB of the first to Nth circuit blocks in the second direction is Q × WD ≦ WB. <(Q + 1) × WD may be sufficient.

  If a plurality of driver cells are arranged along the second direction in this way, image data signals from other circuit blocks arranged along the first direction can be efficiently input to these driver cells. it can. The width of the integrated circuit device in the second direction can be reduced by minimizing the width of the data driver block in the second direction.

  In the integrated circuit device according to the present invention, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of data driver blocks is DBN, and image data input to the driver cell in one horizontal scanning period is stored. When the number of inputs is IN, the number Q of the driver cells arranged along the second direction may be Q = HPN / (DBN × IN).

  In this way, the width of the first to Nth circuit blocks in the second direction can be set to an optimum width according to the number of data driver blocks and the number of times image data is input.

  In the integrated circuit device according to the present invention, the first to Nth circuit blocks include at least one memory block for storing image data, and each of the data drivers included in the data driver block corresponds to one pixel. A data signal corresponding to the image data is output, includes Q driver cells arranged in the second direction, and the width of the driver cell in the second direction is WD, and the memory block includes When the width of the peripheral circuit portion in the second direction is WPC, Q × WD ≦ WB <(Q + 1) × WD + WPC may be satisfied.

  In this way, the widths of the first to Nth circuit blocks can be set based on the width of the memory block. Since at least a circuit block (memory block) exists in the second direction at least in a portion where the memory block exists, a narrow integrated circuit device can be realized. The width of the integrated circuit device in the second direction can be reduced by minimizing the width of the data driver block in the second direction.

  In the integrated circuit device according to the present invention, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of data driver blocks is DBN, and image data input to the driver cell in one horizontal scanning period is stored. When the number of inputs is IN, the number Q of the driver cells arranged along the second direction may be Q = HPN / (DBN × IN).

  In this way, the width of the integrated circuit device in the second direction can be reduced by minimizing the width of the memory block in the second direction.

  In the integrated circuit device according to the present invention, the memory block and the data driver block may be arranged adjacent to each other along the first direction.

  In this way, the width of the integrated circuit device in the second direction can be reduced as compared with the technique in which the memory block and the data driver block are arranged along the second direction. In addition, when the configuration of the memory block or the data driver block is changed, the influence on other circuit blocks can be minimized, and design efficiency can be improved.

  In the integrated circuit device according to the present invention, the image data stored in the memory block may be read a plurality of times in one horizontal scanning period with respect to the adjacent data driver block from the memory block.

  This reduces the number of memory cells in the second direction of the memory block, so that the width of the memory block in the second direction can be reduced, and the width of the integrated circuit device in the second direction is also reduced. It becomes possible.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example FIG. 1A shows an integrated circuit device 500 as a comparative example of the present embodiment. The integrated circuit device 500 of FIG. 1A includes a memory block MB (display data RAM) and a data driver block DB. The memory block MB and the data driver block DB are arranged along the direction D2. Further, the memory block MB and the data driver block DB are ultra flat blocks whose length along the D1 direction is longer than the width in the D2 direction.

  Image data from the host side is written in the memory block MB. The data driver block DB converts the digital image data written in the memory block MB into an analog data voltage and drives the data lines of the display panel. Thus, in FIG. 1A, the signal flow of the image data is in the direction D2. For this reason, in the comparative example of FIG. 1A, the memory block MB and the data driver block DB are arranged along the direction D2 in accordance with the flow of this signal. By doing so, a short path is formed between the input and the output, the signal delay can be optimized, and efficient signal transmission becomes possible.

  However, the comparative example of FIG. 1A has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, when a fine process is employed and the integrated circuit device 500 is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced. Therefore, as shown in FIG. 2A, there is a problem of difficulty in mounting. That is, the output pitch is desirably 22 μm or more, for example, but a simple shrink as shown in FIG. 2A has a pitch of 17 μm, for example, which makes mounting difficult due to the narrow pitch. Moreover, the frame of the glass of the display panel is widened, the number of pieces of glass is reduced, and the cost is increased.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the comparative example of FIG. 1A, in some products, as shown in FIG. 1B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match, the configuration of the memory and data driver changes. As shown in FIG. 1C, these pitches do not match. If the pitches do not match as shown in FIG. 1C, a useless wiring region for absorbing the pitch mismatch must be formed between the circuit blocks. In particular, in the comparative example of FIG. 1A in which the block is flat in the D1 direction, a useless wiring area for absorbing the pitch mismatch becomes large. As a result, the width W of the integrated circuit device 500 in the D2 direction is increased, the chip area is increased, and the cost is increased.

  On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost. That is, in the comparative example of FIG. 1A, the circuit configuration and layout of each circuit block are individually designed, and then the pitch and the like are adjusted, resulting in useless empty areas and inefficient design. Problems arise.

2. Configuration of Integrated Circuit Device FIG. 3 shows a configuration example of the integrated circuit device 10 of the present embodiment that can solve the above problems. In the present embodiment, the direction from the first side SD1 which is the short side of the integrated circuit device 10 to the third side SD3 facing the first direction D1 is the first direction D1, and the opposite direction of D1 is the third direction D3. Yes. The direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and the opposite direction of D2 is a fourth direction D4. In FIG. 3, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3. However, the left side is the third side SD3 and the right side is the first side SD1. May be.

  As shown in FIG. 3, the integrated circuit device 10 of this embodiment includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. That is, in the comparative example of FIG. 1A, the circuit blocks are arranged in the D2 direction, but in this embodiment, the circuit blocks CB1 to CBN are arranged in the D1 direction. Further, each circuit block is not a very flat block as in the comparative example of FIG. 1A, but is a relatively square block.

  The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F region 12 (first I / O region) is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. The input-side I / F area 14 (second I / O area) is arranged on the D4 direction side of the circuit blocks CB1 to CBN, for example, without passing through other circuit blocks. That is, at least in the portion where the data driver block exists, there is only one circuit block (data driver block) in the direction D2. When the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, etc., it may be configured such that at least one of the I / F regions 12 and 14 is not provided.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and includes various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, it includes an output transistor for outputting a data signal to the data line and a scanning signal to the scanning line. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like are included.

  Note that an output-side or input-side I / F area along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to. More specifically, the circuit blocks CB1 to CBN can include at least a data driver block and a logic circuit block, and can further include a grayscale voltage generation circuit block. In the case of a built-in memory type, a memory block can be further included.

  For example, FIG. 4 shows examples of various types of display drivers and circuit blocks incorporated therein. In a display driver for an amorphous TFT (Thin Film Transistor) panel with a built-in memory (RAM), circuit blocks CB1 to CBN include a memory, a data driver (source driver), a scanning driver (gate driver), a logic circuit (gate array circuit), It includes a gradation voltage generation circuit (γ correction circuit) and a power supply circuit block. On the other hand, in a display driver for a low-temperature polysilicon (LTPS) TFT panel with a built-in memory, the scanning driver can be formed on a glass substrate, so that the scanning driver block can be omitted. Also, the memory block can be omitted for an amorphous TFT panel without a memory, and the memory and scan driver blocks can be omitted for a low-temperature polysilicon TFT panel without a memory. Further, for a CSTN (Collar Super Twisted Nematic) panel and a TFD (Thin Film Diode) panel, the block of the gradation voltage generation circuit can be omitted.

  FIGS. 5A and 5B show examples of a planar layout of the integrated circuit device 10 of the display driver of this embodiment. 5A and 5B are examples for an amorphous TFT panel with a built-in memory. FIG. 5A targets, for example, a display driver for QCIF and 32 gradations, and FIG. The display driver for gradation is targeted.

  5A and 5B, the first to Nth circuit blocks CB1 to CBN are first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense. I is 2). Including the above integer). The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  In FIG. 5A, MB1 of the memory blocks MB1 to MB4 (Jth memory block in a broad sense, 1 ≦ J <I) is placed on the D3 direction side of the data driver blocks DB1 to DB4. In a broad sense, the Jth data driver block) is arranged adjacent to each other. Further, a memory block MB2 (J + 1th memory block in a broad sense) is arranged adjacent to the D1 direction side of the memory block MB1. A data driver block DB2 (J + 1th data driver block in a broad sense) is arranged adjacent to the D1 direction side of the memory block MB2. The arrangement of the memory blocks MB3 and MB4 and the data driver blocks DB3 and DB4 is the same. In this way, in FIG. 5A, MB1, DB1, and MB2, DB2 are arranged symmetrically with respect to the boundary lines of MB1 and MB2, and MB3, DB3, and MB4 are arranged symmetrically with respect to the boundary lines of MB3 and MB4. , DB4 are arranged. In FIG. 5A, DB2 and DB3 are arranged adjacent to each other, but other circuit blocks may be arranged between them without adjoining them.

  On the other hand, in FIG. 5B, DB1 (Jth data driver block) of the data driver blocks DB1 to DB4 is on the D3 direction side of MB1 (Jth memory block) of the memory blocks MB1 to MB4. Adjacent to each other. Further, DB2 (J + 1th data driver block) is arranged on the D1 direction side of MB1. MB2 (J + 1th memory block) is arranged on the D1 direction side of DB2. DB3, MB3, DB4, and MB4 are similarly arranged. In FIG. 5B, MB1 and DB2, MB2 and DB3, and MB3 and DB4 are arranged adjacent to each other, but other circuit blocks may be arranged between them without being adjacent to each other. Good.

  5A has an advantage that the column address decoder can be shared between the memory blocks MB1 and MB2 and between the MB3 and MB4 (between the Jth and J + 1th memory blocks). On the other hand, according to the layout arrangement of FIG. 5B, there is an advantage that the wiring pitch of the data signal output lines from the data driver blocks DB1 to DB4 to the output side I / F region 12 can be equalized and the wiring efficiency can be improved. is there.

  The layout arrangement of the integrated circuit device 10 of the present embodiment is not limited to FIGS. For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. In addition, a configuration in which a memory block, a scan driver block, a power supply circuit block, a gradation voltage generation circuit block, or the like is not provided may be employed. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  6A is an example of a cross-sectional view along the direction D2 of the integrated circuit device of this embodiment, and FIG. 6B is an example of a cross-sectional view of a comparative example. In the comparative example of FIG. 1A, as shown in FIG. 6B, two or more circuit blocks are arranged along the direction D2. In the D2 direction, a wiring region is formed between the circuit blocks or between the circuit block and the I / F region. Therefore, the width W of the integrated circuit device 500 in the D2 direction (short side direction) becomes large, and a slim elongated chip cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened as shown in FIG. Incurs difficulty in implementation.

  On the other hand, in this embodiment, as shown in FIGS. 3, 5A and 5B, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. Further, as shown in FIG. 6A, a transistor (circuit element) can be disposed under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, as shown in FIG. 2B, the width W in the D2 direction can be narrowed while maintaining the length LD in the D1 direction of the integrated circuit device 10, and an ultra slim slim chip can be realized. As a result, the output pitch can be maintained at, for example, 22 μm or more, and mounting can be facilitated.

  In the present embodiment, since the plurality of circuit blocks CB1 to CBN are arranged along the direction D1, it is possible to easily cope with a change in product specifications and the like. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, in FIGS. 5A and 5B, even when the number of pixels and the number of gradations of the display panel increase or decrease, the number of memory blocks and data driver blocks, the number of times image data is read out in one horizontal scanning period, etc. Just increase or decrease the number. FIGS. 5A and 5B are examples for an amorphous TFT panel with a built-in memory. When developing a product for a low-temperature polysilicon TFT panel with a built-in memory, scanning is performed from among the circuit blocks CB1 to CBN. Just remove the driver block. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, in this embodiment, the influence of the circuit block on the other circuit blocks can be minimized, so that the design efficiency can be improved.

  In the present embodiment, the width (height) of each circuit block CB1 to CBN in the D2 direction can be unified with, for example, the width (height) of the data driver block and the memory block. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, in FIGS. 5A and 5B, even when the configuration of the gradation voltage generation circuit block or the power supply circuit block is changed and the number of transistors is increased or decreased, the direction of the gradation voltage generation circuit block or the power supply circuit block in the direction D1 This can be dealt with by increasing or decreasing the length.

  As a second comparative example, there is also a method in which, for example, the data driver block is elongated in the D1 direction, and other circuit blocks such as a memory block are arranged along the D1 direction on the D4 direction side of the data driver block. Conceivable. However, in the second comparative example, a data driver block having a large width is interposed between another circuit block such as a memory block and the output-side I / F region. Therefore, in the D2 direction of the integrated circuit device. The width W becomes larger, and it becomes difficult to realize a slim elongated chip. In addition, a useless wiring area is generated between the data driver block and the memory block, and the width W is further increased. Further, when the configuration of the data driver block or the memory block is changed, the pitch mismatch problem described with reference to FIGS. 1B and 1C occurs, and the design efficiency cannot be improved.

  Further, as a third comparative example of the present embodiment, a method in which only circuit blocks having the same function (for example, data driver blocks) are divided into blocks and arranged in the D1 direction is also conceivable. However, in the third comparative example, since the integrated circuit device can have only the same function (for example, the function of the data driver), various product development cannot be realized. On the other hand, in the present embodiment, the circuit blocks CB1 to CBN include circuit blocks having at least two different functions. Accordingly, as shown in FIGS. 4, 5A and 5B, there is an advantage that various types of integrated circuit devices corresponding to various types of display panels can be provided.

3. Circuit Configuration FIG. 7 shows a circuit configuration example of the integrated circuit device 10. The circuit configuration of the integrated circuit device 10 is not limited to that shown in FIG. 7, and various modifications can be made. The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). In this case, one pixel is composed of, for example, three subpixels (3 dots) of R, G, and B, and image data of, for example, 6 bits (k bits) is stored for each subpixel. The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22. The access area of the memory cell array 22 is defined by, for example, a rectangle having a start address and an end address as opposite vertices. That is, an access area is defined by the column address and row address of the start address and the column address and row address of the end address, and memory access is performed.

  The logic circuit 40 (for example, an automatic placement and routing circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation characteristic (γ characteristic) adjustment data (γ correction data) is output to the gradation voltage generation circuit 110 and voltage generation of the power supply circuit 90 is controlled. Further, it controls the write / read processing to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28. The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory to the display panel side. The host (MPU) interface circuit 46 implements a host interface that generates an internal pulse for each access from the host and accesses the memory. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to a memory using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  In FIG. 7, the host interface circuit 46 and the RGB interface circuit 48 access the memory 20 in units of pixels. On the other hand, to the data driver 50, image data designated by a line address and read in units of lines is sent for each line period at an internal display timing independent of the host interface circuit 46 and the RGB interface circuit 48.

  The data driver 50 is a circuit for driving the data lines of the display panel, and FIG. 8A shows a configuration example thereof. The data latch circuit 52 latches digital image data from the memory 20. The D / A conversion circuit 54 (voltage selection circuit) performs D / A conversion of the digital image data latched by the data latch circuit 52 and generates an analog data voltage. Specifically, a plurality of (for example, 64 levels) gradation voltages (reference voltages) are received from the gradation voltage generation circuit 110, and a voltage corresponding to digital image data is selected from the plurality of gradation voltages. And output as a data voltage. The output circuit 56 (drive circuit, buffer circuit) buffers the data voltage from the D / A conversion circuit 54 and outputs it to the data line of the display panel to drive the data line. Note that a part of the output circuit 56 (for example, an output stage of an operational amplifier) may not be included in the data driver 50 but may be arranged in another region.

  The scan driver 70 is a circuit for driving the scan lines of the display panel, and FIG. 8B shows a configuration example thereof. The shift register 72 includes a plurality of flip-flops sequentially connected, and sequentially shifts the enable input / output signal EIO in synchronization with the shift clock signal SCK. The level shifter 76 converts the voltage level of the signal from the shift register 72 into a high voltage level for scanning line selection. The output circuit 78 buffers the scanning voltage converted and output by the level shifter 76 and outputs it to the scanning line of the display panel to selectively drive the scanning line. Note that the scan driver 70 may have the configuration shown in FIG. In FIG. 8C, the scan address generation circuit 73 generates and outputs a scan address, and the address decoder performs a scan address decoding process. A scanning voltage is output via the level shifter 76 and the output circuit 78 to the scanning line specified by this decoding process.

  The power supply circuit 90 is a circuit that generates various power supply voltages, and FIG. The booster circuit 92 is a circuit that boosts the input power supply voltage and the internal power supply voltage by a charge pump method using a boosting capacitor and a boosting transistor, and generates a boosted voltage, and includes primary to quaternary boosting circuits and the like. be able to. The booster circuit 92 can generate a high voltage used by the scan driver 70 and the gradation voltage generation circuit 110. The regulator circuit 94 adjusts the level of the boosted voltage generated by the booster circuit 92. The VCOM generation circuit 96 generates and outputs a VCOM voltage supplied to the counter electrode of the display panel. The control circuit 98 controls the power supply circuit 90 and includes various control registers.

  A gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage, and FIG. 9B shows a configuration example thereof. The selection voltage generation circuit 112 (voltage division circuit) generates selection voltages VS0 to VS255 (R selection voltages in a broad sense) based on the high voltage power supply voltages VDDH and VSSH generated by the power supply circuit 90. Output. Specifically, the selection voltage generation circuit 112 includes a ladder resistor circuit having a plurality of resistor elements connected in series. Then, voltages obtained by dividing VDDH and VSSH by the ladder resistor circuit are output as selection voltages VS0 to VS255. Based on the gradation characteristic adjustment data set in the adjustment register 116 by the logic circuit 40, the gradation voltage selection circuit 114 is selected from among the selection voltages VS0 to VS255, for example, 64 in the case of 64 gradations ( In a broad sense, S voltages (R> S) are selected and output as gradation voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel. In the case of polarity inversion driving, a positive ladder resistance circuit and a negative ladder resistance circuit may be provided in the selection voltage generation circuit 112. Further, the resistance value of each resistance element of the ladder resistor circuit may be changed based on the adjustment data set in the adjustment register 116. Further, the selection voltage generation circuit 112 and the gradation voltage selection circuit 114 may be provided with an impedance conversion circuit (an operational amplifier having a voltage follower connection).

  FIG. 10A shows a configuration example of each DAC (Digital Analog Converter) included in the D / A conversion circuit 54 of FIG. Each DAC in FIG. 10A can be provided, for example, for each subpixel (or for each pixel), and is configured by a ROM decoder or the like. Then, based on the 6-bit digital image data D0 to D5 from the memory 20 and the inverted data XD0 to XD5, any one of the gradation voltages V0 to V63 from the gradation voltage generation circuit 110 is selected. Data D0 to D5 are converted into analog voltages. The obtained analog voltage signal DAQ (DAQR, DAQG, DAQB) is output to the output circuit 56.

  In addition, when the data signals for R, G, and B are multiplexed and sent to the display driver by the display driver for the low-temperature polysilicon TFT (in the case of FIG. 10C), for R and G , B image data can also be D / A converted using one common DAC. In this case, each DAC in FIG. 10A is provided for each pixel.

  FIG. 10B shows a configuration example of each output unit SQ included in the output circuit 56 of FIG. Each output unit SQ in FIG. 10B can be provided for each pixel. Each output unit SQ includes impedance conversion circuits OPR, OPG, and OPB (voltage follower-connected operational amplifiers) for R (red), G (green), and B (blue), and signals DAQR and DAQQ from the DAC , DAQB impedance conversion is performed, and data signals DATAR, DATAG, and DATAB are output to the R, G, and B data signal output lines. For example, in the case of a low-temperature polysilicon TFT panel, switch elements (switch transistors) SWR, SWG, and SWB as shown in FIG. 10C are provided, and data signals for R, G, and B are multiplexed. The impedance conversion circuit OP may output the data signal DATA that has been processed. Further, the data signal may be multiplexed over a plurality of pixels. Further, the output unit SQ may be provided with only a switch element or the like without providing the impedance conversion circuit as shown in FIGS.

4). 4.1 Width of Integrated Circuit Device 4.1 Electrostatic Protection Element In the integrated circuit device 10, various signals are input and output in order to interface with a display panel and interface with a host. Various signals are input / output through the pad, and a transistor or an electrostatic protection element is connected to the pad in case static electricity is applied in addition to the signal. The transistors are, for example, transistors constituting an input buffer, transistors constituting an output buffer, and transistors constituting an input / output buffer. Such pads, transistors, and electrostatic protection elements are disposed, for example, in the output-side I / F region 12 and the input-side I / F region 14 of the integrated circuit device 10.

  11A and 11B are explanatory diagrams of the electrostatic protection element. FIG. 11A shows a configuration example of the electrostatic protection element connected to the output buffer, and FIG. 11B shows a configuration example of the electrostatic protection element connected to the input buffer. Since the input / output buffer can be configured by combining an input buffer and an output buffer, illustration and description thereof are omitted.

  In FIG. 11A, an electrostatic protection element EPE1 and an output buffer OBUF are connected to a pad (output pad) PDO. The output buffer OBUF is connected between the high potential side power supply line PSH1 and the low potential side power supply line PSL1. The output buffer OBUF includes a P-type MOS transistor OPTR1 whose source is connected to the high potential side power supply line PSH1 and an N type MOS transistor ONTR1 whose source is connected to the low potential side power supply line PSL1. The drain of the P-type MOS transistor OPTR1 and the drain of the N-type MOS transistor ONTR1 are connected, and this connection node becomes an output node. Then, the voltage at the output node is supplied to the pad PDO as the output voltage.

  The electrostatic protection element EPE1 is provided between the pad PDO (output node of the output buffer OBUF) and the low potential side power supply line PSL1. The electrostatic protection element EPE1 is constituted by a diode. This diode is constituted by a so-called gate control transistor. The gate control transistor has a source and a gate connected to the low potential side power supply line PSL1, and a drain connected to the pad PDO and an output node of the output buffer OBUF. An electrostatic protection element EPE2 is also inserted between the high potential side power supply line PSH1 and the low potential side power supply line PSL1. The electrostatic protection element EPE2 can also be constituted by a gate control transistor.

  Here, the static electricity applied to the pad PDO flows into the power supply line through a path having a lower impedance with respect to the node NDE1. In order to protect the output buffer OBUF (N-type MOS transistor NTR1), it is necessary to pass through the gate control transistor from the node NDE1. Therefore, for example, a resistance element for electrostatic protection is inserted between the node NDE1 and the output node of the output buffer OBUF so that a low-impedance path with respect to the node NDE1 is surely a path toward the electrostatic protection element EPE1. Yes. Static electricity that has flowed into the low-potential-side power supply line PSL1 through the gate control transistor flows into the high-potential-side power supply line PSH1 through the electrostatic protection element EPE2.

  In FIG. 11B, the electrostatic protection element EPE3 and the input buffer IBUF are connected to the pad (input pad) PDI. The input buffer IBUF is connected between the high potential side power supply line PSH2 and the low potential side power supply line PSL2. Input buffer IBUF includes a P-type MOS transistor IPTR1 whose source is connected to high-potential-side power supply line PSH2, and an N-type MOS transistor ONTR1 whose source is connected to low-potential-side power supply line PSL2. The gate of the P-type MOS transistor IPTR1 and the gate of the N-type MOS transistor INTR1 are connected, and this connection node becomes the input node NDE2. The input signal input to the pad PDI is supplied to the input node NDE2. The drain of the P-type MOS transistor IPTR1 and the drain of the N-type MOS transistor INTR1 are connected.

  The electrostatic protection element EPE3 is provided between the pad PDI (input node NDE2) and the low potential side power supply line PSL2. The electrostatic protection element EPE3 is configured by a diode. This diode is constituted by a so-called gate control transistor. The gate control transistor has a source and a gate connected to the low potential side power supply line PSL2, and a drain connected to the pad PDO and the input node NDE2. An electrostatic protection element EPE4 is also inserted between the high potential side power supply line PSH2 and the low potential side power supply line PSL2. The electrostatic protection element EPE4 can also be constituted by a gate control transistor.

  Here, the static electricity applied to the pad PDI flows into the power supply line through a path having a lower impedance with respect to the node NDE2. In order to protect the input buffer IBUF (N-type MOS transistor INTR1), it is necessary to pass the gate control transistor from the node NDE2. Therefore, for example, a resistance element for electrostatic protection is inserted between the node NDE2 and the input node of the input buffer IBUF so that a low-impedance path is surely directed to the electrostatic protection element EPE3 with respect to the node NDE2. Yes. Static electricity that has flowed into the low-potential-side power supply line PSL2 through the gate control transistor flows into the high-potential-side power supply line PSH2 through the electrostatic protection element EPE4.

  By the way, since the data driver for driving the data lines of the display panel and the scan driver for scanning the scanning lines of the display panel drive a large number of output pads, the area of the pad and the electrostatic protection element is reduced to reduce the layout area. Can be much smaller. Therefore, in the present embodiment, the pad PDO (PDI) is arranged on the upper layer of the region so as to overlap a part or the whole of the region where the electrostatic protection element EPE1 (EPE3) is formed. This reduces the layout area of the circuit area around the pad.

  Furthermore, in the present embodiment, static electricity flows from the pad into the first wiring layer (conductive layer in a broad sense) formed immediately above the impurity region for releasing static electricity in the region of the electrostatic protection element, and the first One wiring layer is electrically connected to the transistors constituting the output buffer and input buffer which are internal transistors. In other words, the electrical signal path from the pad always passes through the first wiring layer and branches to the path to the impurity region constituting the electrostatic protection element or the path to the internal transistor. As a result, static electricity from the pad necessarily flows into the first wiring layer, and this static electricity flows into the impurity region that forms the electrostatic protection element that is a lower impedance path.

  FIG. 12A schematically shows a cross-sectional structure of an integrated circuit device in a comparative example. FIG. 12A shows a cross-sectional structure of an electrostatic protection element that protects a transistor included in the output buffer and a pad connected to the electrostatic protection element. The semiconductor substrate SUB (substrate in a broad sense) (or a well region formed in the semiconductor substrate SUB) includes an impurity region (drain region of a gate control transistor) DAesd and an output transistor (N-type MOS) that constitute an electrostatic protection element. Transistor) drain region DAtr.

  A first wiring layer ALA1, a second wiring layer ALB2, and a third wiring layer ALC, which are metal wiring layers, are formed in that order from the lower layer to the upper layer in the upper layer of the impurity region DAesd, and a fourth wiring layer called a top metal is formed. As a result, a pad PD is formed. An interlayer insulating film (not shown) is formed between the wiring layers, and the wiring layers are electrically connected through contact holes of the interlayer insulating films. For example, the first wiring layer ALA1 and the second wiring layer ALB1 are electrically connected via the contact hole CNH2, and the second wiring layer ALB1 and the third wiring layer ALC are electrically connected via the contact hole CNH3. The third wiring layer ALC and the pad PD are electrically connected through the contact hole CNH4. Further, the impurity region DAesd constituting the electrostatic protection element is electrically connected to the first wiring layer ALA1 through the contact hole CNH1.

  On the other hand, in the upper layer of the drain region DAtr of the output transistor, a first wiring layer ALA2 and a second wiring layer ALB2 which are metal wiring layers are formed in order from the lower layer to the upper layer. The first wiring layers ALA1 and ALA2 are electrically separated (blocked). The second wiring layers ALB1 and ALB2 are also electrically separated. An interlayer insulating film (not shown) is formed between the first and second wiring layers ALA2 and ALB2, and the wiring layers are electrically connected through contact holes of the interlayer insulating film. For example, the first wiring layer ALA2 and the second wiring layer ALB2 are electrically connected through the contact hole CNH6. The second wiring layer ALB2 and the third wiring layer ALC are electrically connected through the contact hole CNH7. Further, the drain region DAtr of the transistor is electrically connected to the first wiring layer ALA2 through the contact hole CNH5.

  Here, when static electricity is applied to the pad PD, it flows into the third wiring layer ALC through the contact hole CNH4. Here, with reference to the third wiring layer ALC, static electricity passes through the low impedance path among the path to the impurity region DAesd via the contact hole CNH3 and the path to the drain region DAtr via the contact hole CNH7. Flows in. This impedance is mainly determined by the resistance component of each wiring layer and the contact resistance of each contact hole. Actually, the design rule depends on the layout and withstand voltage of the wiring layer, the number of contact holes, etc., manufacturing variations, etc. It depends on the factors. For this reason, the static electricity applied to the pad PD does not necessarily flow into the impurity region DAesd of the electrostatic protection element, and when the static electricity flows into the drain region DAtr of the transistor, the transistor is electrostatically destroyed.

  Therefore, in this embodiment, as shown in FIG. 12B, the first wiring layer ALA1 and the drain region DAtr are formed so as to form a path that flows from the pad PD to the drain region DAtr of the transistor through the first wiring layer ALA1. Electrical connection is made via contact hole CNH5. More specifically, when the integrated circuit device 10 includes a pad, an electrostatic protection element electrically connected to the pad, and an output transistor protected by the electrostatic protection element, the integrated circuit device 10 includes an electrostatic protection element. A pad is arranged in an upper layer of the impurity region so as to overlap a part or all of the impurity region to be formed. A conductive layer for electrically connecting the impurity region and the drain region of the output transistor is electrically connected to the pad and via a contact hole of an interlayer insulating film provided on the impurity region. It is electrically connected to the impurity region. A conductive layer is formed on the interlayer insulating film. When the electrostatic protection element is a gate control transistor, the impurity region is a drain region of the gate control transistor.

  By doing so, when static electricity is applied to the pad PD, the static electricity can always flow into the first wiring layer ALA1. At this time, even if there are fluctuation factors such as manufacturing variations, the path to the impurity region DAesd via the contact hole CNH1 becomes the lowest impedance path with reference to the first wiring layer ALA1, and the static electricity is surely transferred to the impurity region. You can escape to DAesd. For this reason, it is possible to reliably prevent electrostatic breakdown of the transistor. Further, it is possible to employ a configuration in which a resistance element for electrostatic protection inserted to protect the output transistor can be omitted, and the layout area of the integrated circuit device 10 having a large number of pads can be greatly reduced.

  In the case of the input transistor, the same effect can be obtained only in that the conductive layer electrically connects the impurity region and the gate electrode of the input transistor.

  Note that, as shown in FIG. 12C, it is desirable to electrically connect to the drain region DAtr of the transistor once through the wiring layer above the first wiring layer ALA1. In FIG. 12C, the first wiring layer ALA1 is electrically connected to the second wiring layer ALB2 through the contact hole CNH8. The second wiring layer ALB2 is electrically connected to the drain region DAtr of the transistor through the contact hole CNH6, the first wiring layer ALA2, and the contact hole CNH5. By doing so, for example, the contact resistance of the contact holes CNH8 and CNH6 increases as compared with FIG. 12B, and the impedance of the path to the drain region DAtr of the transistor becomes higher with respect to the first wiring layer ALA1. Furthermore, the static electricity from the pad PD can be surely released to the impurity region DAesd of the static electricity protection element as it is.

  11, 12 </ b> B, and 12 </ b> C, the resistance element for electrostatic protection is omitted, but the resistance element may be inserted so that the impedance of the path to the transistor becomes high.

  FIG. 13 shows an example of a layout plan view of the pad and the electrostatic protection element of this embodiment. FIG. 13 shows a layout plan view and a schematic diagram of a cross-sectional structure taken along line AA of the layout plan view.

  In FIG. 13, the electrostatic protection element is constituted by a gate control transistor. The gate control transistor is divided into two regions by a circulating P-type impurity diffusion region PF in the semiconductor substrate SUB or a well region formed in the semiconductor substrate SUB. In each region, the channel is directly below the gate electrode GM. An N-type impurity diffusion region NF is provided so as to be a region. The substrate potential of the semiconductor substrate SUB is applied to the P-type impurity diffusion region PF through a contact hole (not shown). The drain region is electrically connected to the first wiring layer ALA formed on the interlayer insulating film through a contact hole of an interlayer insulating film (not shown) formed on the drain region. The first wiring layer ALA is electrically connected to the second wiring layer ALB1 formed on the interlayer insulating film through a contact hole of an interlayer insulating film (not shown) formed on the first wiring layer ALA. . Similarly, the second wiring layer ALB1 is electrically connected to the third wiring layer ALC through the contact hole. Third wiring layer ALC is electrically connected to pad PD through a contact hole. On the other hand, the first wiring layer ALA is electrically connected to the second wiring layer ALB2 through a contact hole of an interlayer insulating film (not shown) formed on the first wiring layer ALA. The second wiring layer ALB2 is electrically separated from the second wiring layer ALB1. The second wiring layer ALB2 is electrically connected to the drain region or gate electrode of the transistor to be electrostatically protected by the gate control transistor.

  That is, in this embodiment, the drain region (impurity region constituting the electrostatic protection element) of the gate control transistor is disposed immediately below the pad PD. Then, the pad and the first wiring layer ALA formed through the interlayer insulating film on the drain region are electrically connected, and the first wiring layer ALA and the gate control are connected through the contact hole of the interlayer insulating film. It is electrically connected to the drain region of the transistor. Then, the transistors constituting the output buffer and the input buffer are electrically connected to the pad PD through the first wiring layer ALA.

  FIG. 14 shows an example of a cross-sectional structure of the electrostatic protection element EPE1 and the N-type MOS transistor ONTR1 shown in FIG. Here, the N-type MOS transistor ONTR1 is a transistor protected by the electrostatic protection element EPE1.

  In the semiconductor substrate SUB (substrate in a broad sense) (or a well region formed in the semiconductor substrate SUB), an impurity region for forming the electrostatic protection element EPE1 and an impurity region for forming the transistor ONTR1 are formed. . In FIG. 14, a P-type impurity diffusion region PF and an N-type impurity diffusion region NF are formed in a region where the electrostatic protection element EPE1 is formed as shown in FIG. 13, and each impurity diffusion region is electrically separated by an element isolation film DF. Separated. In the region where the transistor ONTR1 is formed, two N-type impurity diffusion regions NF1 are formed so that the region between them becomes a channel region, and a P-type impurity diffusion region PF1 for fixing the substrate potential is formed. . Each impurity diffusion region is also separated by the element isolation film DF.

  That is, the semiconductor substrate SUB (or the well region formed in the semiconductor substrate SUB) includes an N-type impurity diffusion region NF (first impurity region) which is a drain region as an impurity region constituting the gate control transistor, and the transistor ONTR1. An N-type impurity diffusion region NF1 (second impurity region) serving as a drain region is formed.

  A first interlayer insulating film LF1 is formed on the N-type impurity diffusion regions NF and NF1. The first interlayer insulating film LF1 over the N-type impurity diffusion region NF has a first contact hole CNHL1. The first interlayer insulating film LF1 over the N-type impurity diffusion region NF1 has a second contact hole CNHL2. On the first interlayer insulating film LF1, a first wiring layer (first conductive layer) ALA1 electrically connected to the N-type impurity diffusion region NF (first impurity region) via the first contact hole CNHL1. Is formed. A second interlayer insulating film LF2 having a third contact hole CNHL3 is formed on the first wiring layer ALA1. In FIG. 14, a second wiring layer ALB1 that is electrically connected to the first wiring layer ALA1 through the third contact hole CNHL3 is further formed on the second interlayer insulating film LF2. A third interlayer insulating film LF3 having a fourth contact hole CNHL4 is formed on the second wiring layer ALB1. A third wiring layer ALC1 that is electrically connected to the second wiring layer ALB1 through the fourth contact hole CNHL4 is formed on the third interlayer insulating film LF3. Furthermore, a fourth interlayer insulating film LF4 having a fifth contact hole CNHL5 is formed on the third wiring layer ALC1. On the fourth interlayer insulating film LF3, a metal layer that is a pad PD that is electrically connected to the third wiring layer ALC1 through the fifth contact hole CNHL5 is formed. That is, the metal layer is electrically connected to the first wiring layer ALA1 (first conductive layer) through at least the third contact hole CNHL3. In addition, the metal layer is arranged so as to overlap with part or all of the N-type impurity diffusion region NF (first impurity region) in plan view.

  On the other hand, in the region where the transistor ONTR1 is formed, the gate electrode GM is formed via the gate insulating film GLF formed on the channel region. The N-type impurity diffusion region NF1 (second impurity region) in the region where the transistor ONTR1 is formed is electrically connected to the first wiring layer ALA1 (first conductive layer) through the second contact hole CNHL2. The In FIG. 14, the first wiring layer ALA1 is electrically connected to the second wiring layer ALB2 formed on the second interlayer insulating film LF2 through the sixth contact hole CNHL6 included in the second interlayer insulating film LF2. Connected. The second wiring layer ALB2 is electrically separated from the second wiring layer ALB1. The second wiring layer ALB2 is electrically connected to the first wiring layer ALA2 formed on the first interlayer insulating film LF1 through the seventh contact hole CNHL7 included in the second interlayer insulating film LF2. The first wiring layer ALA2 is electrically separated from the first wiring layer ALA1. The first wiring layer ALA2 is electrically connected to the N-type impurity diffusion region NF1 through the second contact hole CNHL2. That is, the N-type impurity diffusion region NF1 is electrically connected to the first wiring layer ALA1 (first conductive layer) via one or a plurality of conductive layers formed on the second interlayer insulating film LF2. .

  In this way, the pad PD is electrically connected to the first wiring layer ALA1, and the first wiring layer ALA1 is electrically connected to the N-type impurity diffusion region NF constituting the electrostatic protection element via the first contact hole CNHL1. Connected. The first wiring layer ALA1 is electrically connected to the N-type impurity diffusion region NF1 that becomes the drain region of the transistor ONTR1. As a result, the static electricity applied to the pad PD can be surely released to the N-type impurity diffusion region NF of the static electricity protection element, and the internal transistor ONTR1 can be protected. Further, even if the resistance element for electrostatic protection is omitted, static electricity can be surely released.

  FIG. 15 shows an example of a cross-sectional structure of the electrostatic protection element EPE3 and the N-type MOS transistor INTR1 in FIG. Here, the N-type MOS transistor INTR1 is a transistor protected by the electrostatic protection element EPE3. In FIG. 15, the same parts as those in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  15 differs from FIG. 14 in that the first interlayer insulating film LF1 is formed on the N-type impurity diffusion region NF (first impurity region) and the gate electrode GM of the transistor INTR1, and the first and second contact holes CNHL1. , CNHL2 and the gate electrode GM constituting the transistor INTR1 is electrically connected to the first wiring layer ALB2 (first conductive layer) through the second contact hole CNHL2. In FIG. 15, the first wiring layer ALA1 is electrically connected to the second wiring layer ALB2 formed on the second interlayer insulating film LF2 through the sixth contact hole CNHL6 included in the second interlayer insulating film LF2. Connected. The second wiring layer ALB2 is electrically separated from the second wiring layer ALB1. The second wiring layer ALB2 is electrically connected to the first wiring layer ALA2 formed on the first interlayer insulating film LF1 through the seventh contact hole CNHL7 included in the second interlayer insulating film LF2. The first wiring layer ALA2 is electrically separated from the first wiring layer ALA1. The first wiring layer ALA2 is electrically connected to the gate electrode GM through the second contact hole CNHL2. That is, the gate electrode GM is electrically connected to the first wiring layer ALA1 (first conductive layer) via one or a plurality of conductive layers formed on the second interlayer insulating film LF2.

  In this way, the pad PD is electrically connected to the first wiring layer ALA1, and the first wiring layer ALA1 is electrically connected to the N-type impurity diffusion region NF constituting the electrostatic protection element via the first contact hole CNHL1. Connected. Then, the first wiring layer ALA1 is electrically connected to the gate electrode GM of the transistor INTR1. As a result, the static electricity applied to the pad PD can be surely released to the N-type impurity diffusion region NF of the electrostatic protection element, and the internal transistor INTR1 can be protected. Further, even if the resistance element for electrostatic protection is omitted, static electricity can be surely released.

4.2 Examples of Transistors Protected by Electrostatic Protection Element FIGS. 16A and 16B show a configuration example of an electrostatic protection element and a transistor protected by the electrostatic protection element in the integrated circuit device 10. FIGS. 16A and 16B show examples of output transistors that output scanning signals to scanning lines. The shift register 72 in FIG. 8B includes flip-flops FF1 to FFn in which flip-flops corresponding to the scanning lines S1 to Sn are connected in cascade, and FIG. In the scanning driver 70 shown, the configuration per one output to the scanning line St (1 ≦ t ≦ n, t is an integer) is shown. Similarly, FIG. 16B shows a configuration per output to the scanning line St in the scanning driver 70 shown in FIG.

  As shown in FIG. 16A, the voltage level of the output signal of the flip-flop FFt is converted by the level shifter 76t. The level shifter 76t is supplied with the high potential side power supply voltage VDDHG and the low potential side power supply voltage VEE, and the voltage level of the output signal of the flip-flop FFt is changed to the voltage level of the high potential side power supply voltage VDDHG or the low potential side power supply voltage VEE. Convert. The output of the level shifter 76t becomes the gate signal of the output transistor constituting the output circuit 78t. The output transistor includes, for example, a P-type MOS transistor pDTrt and an N-type MOS transistor nDTrt connected to each other's drains, and is so-called push-pull connected between a high potential side power source and a low potential side power source. It is desirable that at least one of the transistors pDTrt and nDTrt is formed below the scan signal pad PDt together with the electrostatic protection element ESDt. The high-potential-side power supply voltage VDDHG is supplied to the source of the transistor pDTrt, and the low-potential-side power supply voltage VEE is supplied to the source of the transistor nDTrt. The high potential side power supply voltage VDDHG and the low potential side power supply voltage VEE are generated by the booster circuit 92 of FIG. 9A in the power supply circuit block PB.

  In FIG. 16A, an electrostatic protection element ESDt is connected. The electrostatic protection element ESDt is configured by an N-type MOS transistor GCDTrt. The gate of transistor GCDTrt is connected to its source. The transistor GCDTrt is provided between the drain and source of the transistor nDTrt in parallel with the transistor nDTrt. When a high voltage is applied to the drain of the transistor GCDTrt, current is released to the power source on the low potential side in order to prevent destruction of the transistor nDTrt. Even if a latch-up preventing resistance element RLt is inserted in series between the pad PDt and the drain node DNDt of the transistor GCDTrt, and a protection resistance element RPt for electrostatic protection is inserted in series between the drain node DNDt and the drain of the transistor nDTrt. Good.

  In FIG. 16A, the transistor nDTrt corresponds to the transistor ONTR1 in FIG. 11A, and the electrostatic protection element ESDt corresponds to the electrostatic protection element EPE1 in FIG.

  On the other hand, in FIG. 16B, the voltage level of the output signal decoded by the address decoder 74 is converted by the level shifter 76t. Then, the electrostatic protection element ESDt, which overlaps at least one part or all of the electrostatic protection element ESDt and the transistors pDTrt and nDTrt of the output circuit 78t provided for each output of the scan driver 70 shown in FIG. A pad PDt is disposed on at least one of the transistors pDTrt and nDTrt.

  In FIG. 16B, the transistor nDTrt corresponds to the transistor ONTR1 in FIG. 11A, and the electrostatic protection element ESDt corresponds to the electrostatic protection element EPE1 in FIG.

  In FIGS. 16A and 16B, the latch-up prevention resistance element RLt and the protection resistance element RPt are overlapped with at least one of the latch-up prevention resistance element RLt and the protection resistance element RPt. The pad PDt may be arranged on at least one upper layer. The transistor nDTrt may have the function of the electrostatic protection element ESDt. In this case, a configuration in which the electrostatic protection element ESDt is omitted can be employed.

  Here, among the scan drivers 70 shown in FIGS. 8B and 8C, only the output circuit 78t is arranged in the output-side I / F region 12, and the remaining circuits are one scan driver block of the circuit blocks CB1 to CBN. Can be arranged as For example, the scan driver block SB is arranged as one circuit block at both ends of the circuit blocks CB1 to CBN as shown in FIG. 5A, or the circuits at both ends of the circuit blocks CB1 to CBN as shown in FIG. 5B. Scan driver blocks SB1 and SB2 can be arranged as blocks.

4.3 Elongated Integrated Circuit Device In this embodiment, as shown in FIG. 17A, the first to Nth circuit blocks CB1 to CBN include at least one data driver block DB for driving the data lines. Including. CB1 to CBN include circuit blocks other than the data driver block DB (circuit blocks that realize functions different from DB). Here, the circuit blocks other than the data driver block DB are, for example, logic circuit blocks (40 in FIG. 7). Alternatively, it is a gradation voltage generation circuit block (110 in FIG. 7) or a power supply circuit block (90 in FIG. 7). Alternatively, it is a memory block (20 in FIG. 7) in the case of a built-in memory, and a scan driver block (70 in FIG. 7) in the case of an amorphous TFT.

  In FIG. 17A, W1, WB, and W2 are an output side I / F area 12 (first interface area), first to Nth circuit blocks CB1 to CBN, and an input side I / F area, respectively. 14 (second interface area) in the D2 direction.

  In the present embodiment, as shown in FIG. 17A, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 holds when the width in the D2 direction of the integrated circuit device 10 is W. That is, in the comparative example of FIG. 6B, two or more circuit blocks are arranged along the direction D2. Therefore, the width W in the D2 direction is W ≧ W1 + 2 × WB + W2. On the other hand, in the present embodiment, the output-side I / F area 12 is arranged on the D2 direction side of the data driver block DB (or memory block) without passing through other circuit blocks. That is, the data driver block DB and the output side I / F area 12 are arranged adjacent to each other. The input-side I / F area 14 is arranged on the D4 direction side of the data driver block DB (or memory block) without passing through other circuit blocks. That is, the data driver block DB and the input side I / F area 14 are arranged adjacent to each other. The other circuit blocks in this case are, for example, main macro circuit blocks (grayscale voltage generation circuit, power supply circuit, memory, logic circuit block, etc.) constituting the display driver.

  In the comparative example of FIGS. 1A and 6B, since W ≧ W1 + 2 × WB + W2, the width W in the D2 direction (short side direction) of the integrated circuit device 500 is increased, and a slim elongated chip is obtained. Cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened as shown in FIG. Incurs difficulty in implementation.

  On the other hand, in this embodiment, since no other circuit block is interposed between the data driver block DB and the I / F areas 12 and 14, W <W1 + 2 × WB + W2 holds. Therefore, the width W of the integrated circuit device in the direction D2 can be reduced, and a slim and slender chip as shown in FIG. 2B can be realized. Specifically, the width W in the D2 direction, which is the short side direction, can be W <2 mm, and more specifically, W <1.5 mm. In consideration of chip inspection and mounting, it is desirable that W> 0.9 mm. The length LD in the long side direction can be 15 mm <LD <27 mm. The chip shape ratio SP = LD / W can be set to SP> 10, and more specifically, SP> 12. In this way, according to specifications such as the number of pins, for example, W = 1.3 mm, LD = 22 mm, SP = 16.9, W = 1.35 mm, LD = 17 mm, SP = 12.6. An elongated integrated circuit device can be realized. As a result, the mounting can be facilitated as shown in FIG. Moreover, since the chip area is reduced, the cost can be reduced. In other words, both ease of mounting and cost reduction can be achieved.

  Note that the arrangement method of the comparative example in FIG. 1A is also reasonable if the direction of the signal flow of image data is taken into consideration. In this regard, in this embodiment, as shown in FIG. 17B, the output line DQL of the data signal from the data driver block DB is wired along the direction D2 in the DB. On the other hand, the data signal output line DQL is wired along the direction D1 (D3) in the output-side I / F region 12 (first interface region). Specifically, in the output-side I / F region 12, the data signal output line DQL is arranged along the D1 direction by using a global wiring that is lower than the pad and higher than the local wiring (transistor wiring) in the area. Wiring. In this way, even if an arrangement method in which no other circuit block is interposed between the data driver block DB and the I / F areas 12 and 14 as shown in FIG. It is possible to output properly to the display panel via the pad. Further, if the data signal output line DQL is wired as shown in FIG. 17B, the data signal output line DQL can be connected to a pad or the like using the output side I / F region 12, and the integrated circuit An increase in the width W in the direction D2 of the apparatus can be prevented.

  Note that the widths W1, WB, and W2 in FIG. 17A are the transistor formation regions (bulk region and active region) of the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14, respectively. Width. That is, in the I / F regions 12 and 14, an output transistor, an input transistor, an input / output transistor, a transistor of an electrostatic protection element, and the like are formed. In the circuit blocks CB1 to CBN, transistors constituting the circuit are formed. W1, WB, and W2 are determined based on a well region, a diffusion region, or the like where such a transistor is formed. For example, in order to realize a slimmer integrated circuit device, it is desirable to form bumps (active surface bumps) also on the transistors of the circuit blocks CB1 to CBN. Specifically, a resin core bump having a core formed of a resin and a metal layer formed on the surface of the resin is formed on the transistor (active region). The bumps (external connection terminals) are connected to pads arranged in the I / F regions 12 and 14 by metal wiring. In the present embodiment, W1, WB, and W2 are not the width of the bump formation region but the width of the transistor formation region formed under the bump.

  The widths of the circuit blocks CB1 to CBN in the D2 direction can be unified to the same width, for example. In this case, the widths of the circuit blocks may be substantially the same. For example, a difference of about several μm to 20 μm (several tens of μm) is within an allowable range. When circuit blocks having different widths exist in the circuit blocks CB1 to CBN, the width WB can be the maximum width among the circuit blocks CB1 to CBN. The maximum width in this case can be, for example, the width of the data driver block in the D2 direction. Alternatively, in the case of an integrated circuit device with a built-in memory, the width in the direction D2 of the memory block can be set. An empty area with a width of about 20 to 30 μm can be provided between the circuit blocks CB1 to CBN and the I / F areas 12 and 14, for example.

4.4 Width of Data Driver Block In this embodiment, as shown in FIG. 18A, the data driver DR included in the data driver block DB includes Q driver cells DRC1 to DRC1 arranged side by side along the direction D2. DRCQ may be included. Here, each of driver cells DRC1 to DRCQ receives image data for one pixel. Then, D / A conversion of the image data for one pixel is performed, and a data signal corresponding to the image data for one pixel is output. Each of the driver cells DRC1 to DRCQ can include a data latch circuit, a DAC (DAC for one pixel) in FIG. 10A, and an output unit SQ in FIGS. 10B and 10C.

  When the width (pitch) of the driver cells DRC1 to DRCQ in the D2 direction is WD, the width WB (maximum width) of the circuit blocks CB1 to CBN in the D2 direction is Q as shown in FIG. × WD ≦ WB <(Q + 1) × WD.

  That is, in the present embodiment, the circuit blocks CB1 to CBN are arranged along the direction D1. Accordingly, signal lines for image data input from other circuit blocks (for example, logic circuit blocks and memory blocks) among the circuit blocks CB1 to CBN to the data driver block DB are wirings along the direction D1. The driver cells DRC1 to DRCQ are arranged along the D2 direction as shown in FIG. 18A in order to connect to the signal lines of the image data along the D1 direction. Each of the DRC1 to DRCQ is one pixel. Are connected to the signal line of image data.

  The width WB of the circuit blocks CB1 to CBN can be determined based on, for example, the width of the data driver DB in the D2 direction in an integrated circuit device without a memory. Therefore, in order to reduce the width WB of the circuit blocks CB1 to CBN by reducing the width of the data driver block DB in the D2 direction, the width WB is about Q × WD that is a width in which the driver cells DRC1 to DRCQ are arranged. It is desirable to make it. Then, considering the margin for the wiring region and the like, the width WB is Q × WD ≦ WB <(Q + 1) × WD. In this way, the width of the data driver block DB in the direction D2 can be minimized, and the width WB of the circuit blocks CB1 to CBN can be reduced, so that an elongated integrated circuit device as shown in FIG. 2B can be provided. .

  Note that the number of pixels in the horizontal scanning direction of the display panel (the number of pixels in the horizontal scanning direction of each integrated circuit device when driving the data lines of the display panel shared by a plurality of integrated circuit devices) is HPN, and the data Assume that the number of driver blocks (number of block divisions) is DBN, and the number of input image data input to the driver cell in one horizontal scanning period is IN. Note that IN is equal to the number of read times RN of image data in one horizontal scanning period to be described later. In this case, the number Q of driver cells DRC1 to DRCQ arranged along the direction D2 can be expressed as Q = HPN / (DBN × IN). For example, when HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30.

  As shown in FIG. 18B, the data driver block DB may include a plurality of data drivers DRa and DRb (first to mth data drivers) arranged side by side along the direction D1. If a plurality of data drivers DRa and DRb are arranged (stacked) along the D1 direction in this way, the width W in the D2 direction of the integrated circuit device increases due to the size of the data driver. The situation can be prevented. The data driver has various configurations depending on the type of the display panel. Also in this case, according to the method of arranging a plurality of data drivers along the direction D1, data drivers having various configurations can be efficiently laid out. FIG. 18B shows a case where the number of data drivers arranged in the direction D1 is two, but the number of arranged data drivers may be three or more.

  FIG. 18C shows an example of the configuration and arrangement of the driver cell DRC. A driver cell DRC that receives image data for one pixel includes data latch circuits DLATR, DLATG, and DLATB for R (red), G (green), and B (blue). Each data latch circuit DLATR, DLATG, DLATB latches image data when the latch signal becomes active. The driver cell DRC includes the R, G, and B DACR, DACG, and DACB described with reference to FIG. The output unit SQ described with reference to FIGS. 10B and 10C is also included.

  The configuration and arrangement of the driver cell DRC are not limited to those shown in FIG. 18C, and various modifications can be made. For example, when a data driver for R, G, and B is multiplexed and sent to a display panel as shown in FIG. 10C by a display driver for a low-temperature polysilicon TFT, one common DAC is used. It is possible to perform D / A conversion of image data for R, G, and B (image data for one pixel). Therefore, in this case, as shown in FIG. 18D, the driver cell DRC may include one shared DAC having the configuration of FIG. 18C and 18D, an R circuit (DLATR, DACR), a G circuit (DLATG, DACG), and a B circuit (DLATB, DACB) are arranged along the direction D2 (D4). Has been placed. However, as shown in FIG. 18E, R, G, and B circuits may be arranged along the direction D1 (D3).

4.5 Memory Block Width In the integrated circuit device with a built-in memory, as shown in FIG. 19A, the data driver block DB and the memory block MB can be arranged adjacent to each other in the direction D1.

  In this regard, in the comparative example of FIG. 1A, as shown in FIG. 20A, the memory block MB and the data driver block DB are arranged along the D2 direction, which is the short side direction, according to the signal flow. Is done. For this reason, the width of the integrated circuit device in the D2 direction is increased, and it is difficult to realize a slim elongated chip. If the number of pixels on the display panel, display driver specifications, memory cell configuration, etc. change, and the width in the D2 direction and the length in the D1 direction of the memory block MB and data driver block DB change, the effect will be different. The design block becomes inefficient.

  On the other hand, in FIG. 19A, since the data driver block DB and the memory block MB are arranged along the direction D1, the width W of the integrated circuit device in the direction D2 can be reduced. In addition, when the number of pixels of the display panel changes, it is possible to cope with this by dividing the memory block, so that the design can be made more efficient.

  In the comparative example of FIG. 20A, since the word line WL is arranged along the direction D1, which is the long side direction, the signal delay in the word line WL increases, and the image data read speed decreases. In particular, since the word line WL connected to the memory cell is formed of a polysilicon layer, this signal delay problem is serious. In this case, in order to reduce this signal delay, there is a method of providing buffer circuits 520 and 522 as shown in FIG. However, when this method is adopted, the circuit scale increases correspondingly, resulting in an increase in cost.

  On the other hand, in FIG. 19A, in the memory block MB, the word line WL is wired along the D2 direction which is the short side direction, and the bit line BL is arranged along the D1 direction which is the long side direction. The In this embodiment, the width W of the integrated circuit device in the direction D2 is short. Therefore, the length of the word line WL in the memory block MB can be shortened, and the signal delay at WL can be remarkably reduced as compared with the comparative example of FIG. Further, since it is not necessary to provide the buffer circuits 520 and 522 as shown in FIG. 20B, the circuit area can be reduced. In the comparative example of FIG. 20A, even when a part of the access area of the memory is accessed from the host, the word line WL that is long in the D1 direction and has a large parasitic capacitance is selected. Become. On the other hand, in the method of dividing the memory in the D1 direction as in this embodiment, only the word line WL of the memory block corresponding to the access area is selected during host access. Can be realized.

  In this embodiment, as shown in FIG. 19A, when the width in the D2 direction of the peripheral circuit portion included in the memory block MB is WPC, Q × WD ≦ WB <(Q + 1) × WD + WPC. Can do. Here, the peripheral circuit portion is a peripheral circuit (row address decoder, control circuit, etc.) or a wiring region that is arranged on the D2 or D4 direction side of the memory cell array MA or between the divided memory cell arrays. .

  In the arrangement of FIG. 19A, it is desirable that the width Q × WD of the driver cells DRC1 to DRCQ and the width of the sense amplifier block SAB match. If these widths do not match, it is necessary to change the wiring pitch of these signal lines when connecting the signal lines of the image data from the sense amplifier block SAB to the driver cells DRC1 to DRCQ. Wiring area is generated.

  In addition to the memory cell array MA, the memory block MB has peripheral circuit portions such as a row address decoder RD. Accordingly, in FIG. 19A, the width of the memory block MB is larger than the width Q × WD of the driver cells DRC1 to DRCQ by the width WPC of the peripheral circuit portion.

  The width WB of the circuit blocks CB1 to CBN can be determined based on the width in the direction D2 of the memory block MB in an integrated circuit device with a built-in memory. Therefore, in order to reduce the width WB of the circuit blocks CB1 to CBN by reducing the width in the direction D2 of the memory block MB, it is desirable that the width WB is Q × WD ≦ WB <(Q + 1) × WD + WPC. . By so doing, the width of the memory block MB in the direction D2 can be minimized and the width WB can be reduced, so that an elongated integrated circuit device as shown in FIG. 2B can be provided.

  FIG. 19B shows the arrangement relationship between the driver cells DRC1 to DRCQ and the sense amplifier block SAB. As shown in FIG. 19B, for a driver cell DRC1 that receives image data for one pixel, a corresponding sense amplifier for one pixel (sense amplifiers SAR10 to SAR15 for R, sense amplifier for G). SAG10 to SAG15 and B sense amplifiers SAB10 to SAB15) are connected. The same applies to the connection between the other driver cells DRC2 to DRCQ and the sense amplifier.

  As shown in FIG. 19B, the width WB (maximum width) in the D2 direction of the circuit blocks CB1 to CBN is equal to the width in the D2 direction of the peripheral circuit portion (row address decoder RD) included in the memory block. When the number of bits of image data for one pixel is PDB, it can be expressed as P × WS ≦ WB <(P + PDB) × WS + WPC. Here, when each of R, G, and B is 6 bits, PDB = 18.

  Note that the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN (= DBN), and data is read from the memory block in one horizontal scanning period. Assume that the number of times of reading image data is RN. In this case, the number P of sense amplifiers arranged along the direction D2 in the sense amplifier block SAB can be expressed as P = (HPN × PDB) / (MBN × RN).

  Note that the number P is the number of effective sense amplifiers corresponding to the number of effective memory cells, and does not include the number of ineffective sense amplifiers such as sense amplifiers for dummy memory cells. The number P is the number of sense amplifiers that output 1-bit image data. For example, when 1-bit image data is switched and output by the first and second sense amplifiers and a selector connected to the output thereof, the first and second sense amplifiers and selectors are switched. The combination is equivalent to a sense amplifier that outputs 1-bit image data.

  21A and 21B show detailed layout arrangement examples of the memory block MB. FIG. 21A shows an arrangement example in the case of a horizontal cell to be described later. The MPU / LCD row address decoder RD performs word line selection control during host access and word line selection control during output to the data driver block (LCD). At the time of output to the data driver block, the sense amplifier block SAB amplifies the signal of the image data read from the memory cell array MA, and outputs the image data to the data driver block. The MPU write / read circuit WR performs control of writing image data to an access target memory cell (access area) in the memory cell array MA and reading image data during host access. The MPU write / read circuit WR can include a sense amplifier for reading image data. The MPU column address decoder CD performs selection control of a bit line corresponding to a memory cell to be accessed during host access. The control circuit CC controls each circuit block in the memory block MB.

  FIG. 21B shows an arrangement example in the case of a vertical cell described later. In FIG. 21B, the memory cell array includes a first memory cell array MA1 and a second memory cell array MA2. An MPU / LCD row address decoder RD is provided between the memory cell arrays MA1 and MA2. The MPU / LCD row address decoder RD selects one of the word lines of the memory cell arrays MA1 and MA2 when accessing from the host side. Further, when outputting image data to the data driver block, both word lines of the memory cell arrays MA1 and MA2 are selected. In this way, only the word line of the memory cell array to be accessed can be selected at the time of host access, so that the signal delay on the word line compared to the method of always selecting the word line of both memory cell arrays. And power consumption can be reduced.

  In the case of FIG. 21A, an MPU / LCD row address decoder provided on the D2 (or D4) direction side of the memory cell array MA and in the case of FIG. 21B provided between the memory cell arrays MA1 and MA2. The RD, the control circuit CC, and the wiring area thereof are peripheral circuit portions, and the width thereof is WPC.

  In the present embodiment, the arrangement of the driver cells and the sense amplifiers has been described on the assumption of the arrangement for each pixel. However, a modification may be made in which the arrangement is for each subpixel. Also, the subpixels are not limited to the R, G, and B subpixel configurations, and may be RGB + 1 (for example, white) 4-subpixel configurations.

4.6 Relationship between WB and W1, W2 In this embodiment, as shown in FIG. 22, the width W1 of the output I / F region 12 in the D2 direction is set to 0.13 mm ≦ W1 ≦ 0.4 mm. it can. The width WB of the circuit blocks CB1 to CBN can be set to 0.65 mm ≦ WB ≦ 1.2 mm. Further, the width W2 of the input side I / F region 14 can be 0.1 mm ≦ W2 ≦ 0.2 mm.

  For example, in the output-side I / F region 12, pads having one or more stages in the D2 direction are arranged. As shown in FIG. 6A, the output transistor, the electrostatic protection element transistor, and the like are arranged under the pad so that the width W1 of the output-side I / F region 12 is minimized. . Therefore, considering the pad width (for example, 0.1 mm) and the pad pitch, 0.13 mm ≦ W1 ≦ 0.4 mm.

  On the other hand, in the input-side I / F area 14, a pad having one stage in the D2 direction is arranged. Then, as shown in FIG. 6A, by arranging an input transistor, an electrostatic protection element transistor, and the like under the pad, the width W2 of the input side I / F region 14 is minimized. . Accordingly, in consideration of the pad width and pad pitch, 0.1 mm ≦ W2 ≦ 0.2 mm. In the output-side I / F region 12, the number of pad stages in the D2 direction is set to a plurality of stages because the number (or size) of transistors to be arranged under the pad is in the input-side I / F region 14. This is because the output-side I / F area 12 is more in comparison.

  The width WB of the circuit blocks CB1 to CBN is determined based on the width in the direction D2 of the data driver block DB and the memory block MB as described with reference to FIGS. 18A and 19A. In order to realize an elongated integrated circuit device, the logic signal from the logic circuit block, the gradation voltage signal from the gradation voltage generation circuit block, and the power supply wiring are globally arranged on the circuit blocks CB1 to CBN. It is necessary to form by wiring. The total wiring width is about 0.8 to 0.9 mm, for example. Therefore, in consideration of these, the width WB of the circuit blocks CB1 to CBN is 0.65 mm ≦ WB ≦ 1.2 mm.

  Even if W1 = 0.4 mm and W2 = 0.2 mm, since 0.65 mm ≦ WB ≦ 1.2 mm, WB> W1 + W2 holds. When W1, WB, and W2 are the smallest values, W1 = 0.13 mm, WB = 0.65 mm, and W2 = 0.1 mm, and the width of the integrated circuit device is about W = 0.88 mm. Therefore, W = 0.88 mm <2 × WB = 1.3 mm holds. When W1, WB, and W2 are the largest values, W1 = 0.4 mm, WB = 1.2 mm, and W2 = 0.2 mm, and the width of the integrated circuit device is about W = 1.8 mm. Therefore, W = 1.8 mm <2 × WB = 2.4 mm holds. That is, W <2 × WB holds. If W <2 × WB is established in this way, a narrow integrated circuit device as shown in FIG. 2B can be realized.

  By disposing the output transistor for driving the scanning line below the pad as in this embodiment, the width of W1 of the integrated circuit device 10 including the scanning driver block can be greatly reduced. Therefore, W <2 × WB can be realized easily. As a result, an even slimmer integrated circuit device can be provided.

5. Details of Memory Block and Data Driver Block 5.1 Block Division As shown in FIG. 23A, the display panel has the number of pixels in the vertical scanning direction (data line direction) of VPN = 320, and the horizontal scanning direction (scanning). Assume that the QVGA panel has HPN = 240 pixels in the line direction. Further, it is assumed that the bit number PDB of image (display) data for one pixel is 6 bits for each of R, G, and B, and PDB = 18 bits. In this case, the number of bits of image data necessary for displaying one frame of the display panel is VPN × HPN × PDB = 320 × 240 × 18 bits. Therefore, the memory of the integrated circuit device stores image data for at least 320 × 240 × 18 bits. Further, the data driver displays HPN = 240 data signals (data signals corresponding to 240 × 18 bits of image data) every horizontal scanning period (every period during which one scanning line is scanned). Output to the panel.

  In FIG. 23B, the data driver is divided into DBN = 4 data driver blocks DB1 to DB4. The memory is also divided into MBN = DBN = 4 memory blocks MB1 to MB4. Accordingly, each data driver block DB1 to DB4 outputs HPN / DBN = 240/4 = 60 data signals to the display panel every horizontal scanning period. Each of the memory blocks MB1 to MB4 stores (VPN × HPN × PDB) / MBN = (320 × 240 × 18) / 4 bits of image data. In FIG. 23B, the memory block MB1 and MB2 share the column address decoder CD12, and the memory block MB3 and MB4 share the column address decoder CD34.

5.2 Reading Multiple Times in One Horizontal Scan Period In FIG. 23B, each data driver block DB1 to DB4 outputs 60 data signals in one horizontal scan period. Therefore, it is necessary to read image data corresponding to 240 data signals for each horizontal scanning period from the memory blocks MB1 to MB4 corresponding to DB1 to DB4.

  However, if the number of bits of image data to be read for each horizontal scanning period increases, it is necessary to increase the number of memory cells (sense amplifiers) arranged in the D2 direction. As a result, the width W in the direction D2 of the integrated circuit device is increased, and the slimming of the chip is prevented. In addition, the word line WL becomes long, which causes a problem of WL signal delay.

  Therefore, in the present embodiment, a method of reading image data stored in each of the memory blocks MB1 to MB4 from the memory blocks MB1 to MB4 a plurality of times (RN times) for each data driver block DB1 to DB4 in one horizontal scanning period. Is adopted.

  For example, in FIG. 24, as indicated by A1 and A2, the memory access signal MACS (word selection signal) becomes active (high level) only RN = 2 times in one horizontal scanning period. Thus, image data is read from each memory block to each data driver block RN = 2 times in one horizontal scanning period. Then, the data latch circuits included in the data driver block and included in the data drivers DRa and DRb in FIG. 25 latch the read image data based on the latch signals LATa and LATb indicated by A3 and A4. A D / A conversion circuit included in DRa and DRb performs D / A conversion of the latched image data, and an output circuit included in DRa and DRb converts the data signals DATAa and DATAb obtained by the D / A conversion into A5. , A6 is output to the data signal output line. Thereafter, as shown at A7, the scanning signal SCSEL inputted to the gate of the TFT of each pixel of the display panel becomes active, and the data signal is inputted and held in each pixel of the display panel.

  In FIG. 24, the image data is read twice in the first horizontal scanning period, and the data signals DATAa and DATAb are output to the data signal output line in the same first horizontal scanning period. However, the image data is read and latched twice in the first horizontal scanning period, and the data signals DATAa and DATAb corresponding to the latched image data are supplied to the data signal output lines in the next second horizontal scanning period. It may be output. FIG. 24 shows the case where the number of times of reading RN = 2, but RN ≧ 3 may be possible.

  According to the method of FIG. 24, as shown in FIG. 25, image data corresponding to 30 data signals is read from each memory block, and each data driver DRa, DRb outputs 30 data signals. To do. As a result, 60 data signals are output from each data driver block. In this way, in FIG. 24, it is only necessary to read image data corresponding to 30 data signals from each memory block in one reading. Therefore, the number of memory cells and sense amplifiers in the direction D2 in FIG. 25 can be reduced as compared with the method of reading only once in one horizontal scanning period. As a result, the width of the integrated circuit device in the D2 direction can be reduced, and an ultra slim slim chip as shown in FIG. 2B can be realized. In particular, the length of one horizontal scanning period is about 52 μsec in the case of QVGA. On the other hand, the memory read time is, for example, about 40 nsec, which is sufficiently shorter than 52 μsec. Therefore, even if the number of readings in one horizontal scanning period is increased from one to a plurality of times, the influence on the display characteristics is not so great.

  FIG. 23A shows a QVGA (320 × 240) display panel. If the number of readings in one horizontal scanning period is set to RN = 4, for example, the display panel corresponds to a VGA (640 × 480) display panel. It is also possible to increase the degree of design freedom.

  The plurality of readings in one horizontal scanning period may be realized by a first method in which a row address decoder (word line selection circuit) selects a plurality of different word lines in each memory block in one horizontal scanning period. Alternatively, the same word line in each memory block may be realized by a second method in which a row address decoder (word line selection circuit) selects a plurality of times in one horizontal scanning period. Alternatively, it may be realized by a combination of both the first and second methods.

5.3 Arrangement of Data Driver and Driver Cell FIG. 25 shows an arrangement example of the data driver and the driver cell included in the data driver. As shown in FIG. 25, the data driver block includes a plurality of data drivers DRa and DRb arranged side by side along the direction D1. Each data driver DRa, DRb includes a plurality of 30 (Q in a broad sense) driver cells DRC1 to DRC30.

  When the word line WL1a of the memory block is selected and the first image data is read from the memory block as shown by A1 in FIG. 24, the data driver DRa is read based on the latch signal LATa shown by A3. Latch image data. Then, D / A conversion of the latched image data is performed, and a data signal DATAa corresponding to the first read image data is output to the data signal output line as indicated by A5.

  On the other hand, when the word line WL1b of the memory block is selected and the second image data is read from the memory block as shown by A2 in FIG. 24, the data driver DRb reads based on the latch signal LATb shown by A4. Latched image data. Then, the latched image data is D / A converted, and a data signal DATAb corresponding to the second read image data is output to the data signal output line as indicated by A6.

  In this way, each data driver DRa, DRb outputs 30 data signals corresponding to 30 pixels, so that 60 data signals corresponding to 60 pixels in total are output. It becomes like this.

  As described above, the number Q of the driver cells DRC1 to DRC30 arranged along the direction D2 can be expressed as Q = HPN / (DBN × IN). In the case of FIG. 25, since HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30. As described above, the number P of sense amplifiers arranged along the direction D2 in the sense amplifier block SAB can be expressed as P = (HPN × PDB) / (MBN × RN). In the case of FIG. 25, since HPN = 240, PDB = 18, MBN = 4, and RN = 2, P = (240 × 18) / (4 × 2) = 540.

5.4 Memory Cell FIG. 26A shows a configuration example of a memory cell (SRAM) included in the memory block. This memory cell includes transfer transistors TRA1 and TRA2, load transistors TRA3 and TRA4, and drive transistors TRA5 and TRA6. When the word line WL becomes active, the transfer transistors TRA1 and TRA2 are turned on, and image data can be written to the nodes NA1 and NA2 and image data can be read from the nodes NA1 and NA2. The written image data is held in the nodes NA1 and NA2 by a flip-flop circuit composed of transistors TRA3 to TRA6. Note that the memory cell of this embodiment is not limited to the configuration shown in FIG. 26A, and modifications such as using resistance elements as the load transistors TRA3 and TRA4 and adding other transistors are possible.

  FIGS. 26B and 26C show layout examples of memory cells. FIG. 26B shows a layout example of a horizontal cell, and FIG. 26C shows a layout example of a vertical cell. Here, as shown in FIG. 26B, the horizontal cell is a cell in which the word line WL is longer than the bit lines BL and XBL in each memory cell. On the other hand, as shown in FIG. 26C, the vertical cell is a cell in which the bit lines BL and XBL are longer than the word line WL in each memory cell. Note that WL in FIG. 26C is a local word line formed of a polysilicon layer and connected to the transfer transistors TRA1 and TRA2, but a metal layer word line for preventing signal delay of WL and stabilizing the potential. May be further provided.

  FIG. 27 shows an arrangement example of memory blocks and driver cells when the horizontal cell shown in FIG. 26B is used as the memory cell. FIG. 27 shows in detail a portion corresponding to one pixel in the driver cell and the memory block.

  As shown in FIG. 27, a driver cell DRC that receives image data for one pixel includes R, G, and B data latch circuits DLATR, DLATG, and DLATB. Each data latch circuit DLATR, DLATG, DLATB latches image data when a latch signal LAT (LATa, LATb) becomes active. The driver cell DRC includes the R, G, and B DACR, DACG, and DACB described with reference to FIG. The output unit SQ described with reference to FIGS. 10B and 10C is also included.

  The portion corresponding to one pixel in the sense amplifier block SAB includes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 to SAG5, and B sense amplifiers SAB0 to SAB5. The bit lines BL and XBL of the memory cells MC arranged along the D1 direction on the D1 direction side of the sense amplifier SAR0 are connected to SAR0. In addition, the bit lines BL and XBL of the memory cells MC arranged along the D1 direction on the D1 direction side of the sense amplifier SAR1 are connected to the SAR1. The same applies to the relationship between other sense amplifiers and memory cells.

  When the word line WL1a is selected, image data is read from the memory cell MC to which the gate of the transfer transistor is connected to WL1a to the bit lines BL and XBL, and sense amplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0. ... SAB5 performs signal amplification operation. DLATR latches 6-bit R image data D0R to D5R from SAR0 to SAR5, DACR performs D / A conversion of the latched image data, and output unit SQ outputs data signal DATAAR. . DLATG latches 6-bit G image data D0G to D5G from SAG0 to SAG5, DACG performs D / A conversion of the latched image data, and output unit SQ outputs data signal DATAT. . DLATB latches 6-bit B image data D0B to D5B from SAB0 to SAB5, DACB performs D / A conversion of the latched image data, and output unit SQ outputs data signal DATAB. .

  In the case of the configuration shown in FIG. 27, the image data can be read a plurality of times in one horizontal scanning period shown in FIG. 24 as follows. That is, in the first horizontal scanning period (first scanning line selection period), first, the word line WL1a is selected to read the image data for the first time, and the first data is displayed as indicated by A5 in FIG. The signal DATAa is output. Next, in the same first horizontal scanning period, the word line WL1b is selected, the image data is read for the second time, and the second data signal DATAb is output as indicated by A6 in FIG. In the next second horizontal scanning period (second scanning line selection period), the word line WL2a is first selected to read the image data for the first time, and the first data signal DATAa is output. Next, in the same second horizontal scanning period, the word line WL2b is selected, the image data is read for the second time, and the second data signal DATAb is output. When horizontal cells are used in this way, a plurality of different word lines (WL1a, WL1b) in the memory block are selected in one horizontal scanning period, so that multiple readings in one horizontal scanning period can be realized.

  FIG. 28 shows an arrangement example of memory blocks and driver cells when the vertical cell shown in FIG. 26C is used as the memory cell. In the vertical cell, the width in the D2 direction can be made shorter than that in the horizontal cell. Therefore, the number of memory cells in the D2 direction can be doubled as compared with the horizontal cells. In the vertical cell, the column of memory cells connected to each sense amplifier is switched using column selection signals COLa and COLb.

  For example, in FIG. 28, when the column selection signal COLa becomes active, the memory cell MC on the column Ca side among the memory cells MC on the D1 direction side of the sense amplifiers SAR0 to SAR5 is selected and connected to the sense amplifiers SAR0 to SAR5. Is done. The signals of the image data stored in these selected memory cells MC are amplified and output as D0R to D5R. On the other hand, when the column selection signal COLb becomes active, the memory cell MC on the column Cb side among the memory cells MC on the D1 direction side of the sense amplifiers SAR0 to SAR5 is selected and connected to the sense amplifiers SAR0 to SAR5. The signals of the image data stored in these selected memory cells MC are amplified and output as D0R to D5R. The same applies to reading of image data of memory cells connected to other sense amplifiers.

  In the case of the configuration of FIG. 28, the image data can be read a plurality of times in one horizontal scanning period shown in FIG. 24 as follows. That is, in the first horizontal scanning period, first, the word line WL1 is selected, the column selection signal COLa is activated, the first reading of the image data is performed, and the first data signal is displayed as indicated by A5 in FIG. DATAa is output. Next, the same word line WL1 is selected in the same first horizontal scanning period, the column selection signal COLb is activated, and the second reading of the image data is performed. As shown in A6 of FIG. 24, the second data is read. The signal DATAb is output. In the next second horizontal scanning period, the word line WL2 is selected, the column selection signal COLa is activated, the image data is read for the first time, and the first data signal DATAa is output. Next, the same word line WL2 is selected in the same second horizontal scanning period, the column selection signal COLb is activated, the image data is read a second time, and the second data signal DATAb is output. As described above, in the case of a vertical cell, the same word line in the memory block is selected a plurality of times in one horizontal scanning period, so that reading can be performed a plurality of times in one horizontal scanning period.

6). Electronic Device FIGS. 29A and 29B show examples of electronic devices (electro-optical devices) including the integrated circuit device 10 of the present embodiment. Note that the electronic device may include components other than those shown in FIGS. 29A and 29B (for example, a camera, an operation unit, a power supply, or the like). The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  29A and 29B, the host device 410 is, for example, an MPU (Micro Processor Unit), a baseband engine (baseband processor), or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. An image processing controller (display controller) 420 in FIG. 29B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  The display panel 400 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. The display panel 400 can be constituted by an active matrix panel using switching elements such as TFTs and TFDs. Note that the display panel 400 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel.

  In the case of FIG. 29A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 29B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, in the specification or drawings, terms (output-side I / F region, input-side I / F) described at least once together with different terms having a broader meaning or the same meaning (first interface region, second interface region, etc.) (Area, etc.) can be replaced with the different terms anywhere in the specification or drawings. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

1A, 1B, and 1C are explanatory diagrams of a comparative example of the present embodiment. FIGS. 2A and 2B are explanatory views for mounting an integrated circuit device. 1 is a configuration example of an integrated circuit device according to an embodiment. Examples of various types of display drivers and the circuit blocks they contain. 5A and 5B are plan layout examples of the integrated circuit device of this embodiment. 6A and 6B are examples of cross-sectional views of the integrated circuit device. 6 is a circuit configuration example of an integrated circuit device. 8A, 8B, and 8C are configuration examples of a data driver and a scan driver. 9A and 9B are configuration examples of a power supply circuit and a gradation voltage generation circuit. 10A, 10B, and 10C are configuration examples of a D / A conversion circuit and an output circuit. 11A and 11B are explanatory diagrams of an electrostatic protection element. 12A, 12B, and 12C are schematic views of a cross-sectional structure of an integrated circuit device according to a comparative example and this embodiment. An example of the layout top view of the pad and electrostatic protection element of this embodiment. 11A is an example of a cross-sectional structure of the electrostatic protection element and the transistor in FIG. FIG. 11B illustrates an example of a cross-sectional structure of the electrostatic protection element and the transistor in FIG. 16A and 16B show configuration examples of pads and transistors. 17A and 17B are explanatory diagrams of the width of the integrated circuit device. 18A to 18E are explanatory diagrams of the width of the data driver block. 19A and 19B are explanatory diagrams of the width of the memory block. 20A and 20B are explanatory diagrams of a comparative example. 21A and 21B are configuration examples of memory blocks. Explanatory drawing about the relationship between W1, W2, and WB. 23A and 23B are explanatory diagrams of the arrangement of memory blocks and data driver blocks. Explanatory drawing of the method of reading image data in multiple times in 1 horizontal scanning period. Data driver and driver cell arrangement example. 26A, 26B, and 26C are configuration examples of memory cells. An arrangement example of memory blocks and driver cells in the case of a horizontal cell. An arrangement example of memory blocks and driver cells in the case of a vertical cell. 29A and 29B are configuration examples of electronic devices.

Explanation of symbols

CB1 to CBN 1st to Nth circuit blocks, 10 integrated circuit devices,
12 output side I / F area, 14 input side I / F area, 20 memory,
22 memory cell array, 24 row address decoder,
26 column address decoder, 28 write / read circuit,
40 logic circuit, 42 control circuit, 44 display timing control circuit,
46 host interface circuit, 48 RGB interface circuit,
50 data drivers, 52 data latch circuits, 54 D / A conversion circuits,
56 output circuit, 70 scan driver, 72 shift register,
73 scanning address generation circuit, 74 address decoder, 76 level shifter,
78 output circuit, 90 power supply circuit, 92 booster circuit, 94 regulator circuit,
96 VCOM generation circuit, 98 control circuit, 110 gradation voltage generation circuit,
112 selection voltage generation circuit, 114 gradation voltage selection circuit, 116 adjustment register

Claims (17)

Pad,
An electrostatic protection element electrically connected to the pad;
A transistor protected by the electrostatic protection element,
The pad is disposed above the impurity region so as to overlap with part or all of the impurity region constituting the electrostatic protection element,
A conductive layer for electrically connecting the impurity region and the gate electrode of the transistor, or a conductive layer for electrically connecting the impurity region and the drain region of the transistor,
An integrated circuit device, wherein the integrated circuit device is electrically connected to the pad and is also electrically connected to the impurity region through a contact hole of an interlayer insulating film provided on the impurity region. In claim 1,
The electrostatic protection element is
A gate control transistor,
The impurity region is
An integrated circuit device comprising the drain region of the gate control transistor. An integrated circuit device having an electrostatic protection element and a transistor protected by the electrostatic protection element,
A substrate on which a first impurity region constituting the electrostatic protection element and a second impurity region constituting the transistor are formed;
A first interlayer insulating film formed on the first and second impurity regions and having a first contact hole on the first impurity region and a second contact hole on the second impurity region; ,
A first conductive layer formed on the first interlayer insulating film and electrically connected to the first impurity region through the first contact hole;
A second interlayer insulating film formed on the first conductive layer and having a third contact hole;
Including a metal layer that is a pad,
The metal layer is
At least electrically connected to the first conductive layer via the third contact hole and disposed so as to overlap a part or all of the first impurity region;
The second impurity region is
An integrated circuit device, wherein the integrated circuit device is electrically connected to the first conductive layer through the second contact hole. In claim 3,
The electrostatic protection element is
A gate control transistor,
The first impurity region is
An integrated circuit device comprising the drain region of the gate control transistor. An integrated circuit device having an electrostatic protection element and a transistor protected by the electrostatic protection element,
A substrate on which a first impurity region constituting the electrostatic protection element is formed;
A first interlayer insulating film formed on the first impurity region and the gate electrode of the transistor and having a first contact hole on the first impurity region and a second contact hole on the gate electrode; ,
A first conductive layer formed on the first interlayer insulating film and electrically connected to the first impurity region through the first contact hole;
A second interlayer insulating film formed on the first conductive layer and having a third contact hole;
Including a metal layer that is a pad,
The metal layer is
At least electrically connected to the first conductive layer via the third contact hole and disposed so as to overlap a part or all of the first impurity region;
The gate electrode is
An integrated circuit device, wherein the integrated circuit device is electrically connected to the first conductive layer through the second contact hole. In any of claims 3 to 5,
The second impurity region or the gate electrode is electrically connected to the first conductive layer through one or a plurality of conductive layers formed on the second interlayer insulating film. Integrated circuit device. In any one of Claims 1 thru | or 6.
The transistor is
An integrated circuit device connected in parallel with the electrostatic protection element. In any one of Claims 1 thru | or 7,
The direction from the first side, which is the short side of the integrated circuit device, to the third side facing the first side is the first direction, and the fourth side is the second side, which is the long side of the integrated circuit device. When the direction to go to the second direction,
First to Nth circuit blocks (N is an integer of 2 or more) arranged along the first direction;
A first interface region provided along the fourth side on the second direction side of the first to Nth circuit blocks;
A second interface region provided along the second side on the fourth direction side opposite to the second direction of the first to Nth circuit blocks,
The electrostatic protection element and the transistor are
Formed in the first or second interface region;
The first to Nth circuit blocks are:
Including at least one data driver block for driving the data line, and a circuit block other than the data driver block;
When the widths of the first interface region, the first to Nth circuit blocks, and the second interface region in the second direction are W1, WB, and W2, respectively, The width W in the second direction is W1 + WB + W2 ≦ W <W1 + 2 × WB + W2. In claim 8,
The integrated circuit device, wherein the width W of the integrated circuit device in the second direction is W <2 × WB. In claim 8 or 9,
The first interface region is arranged on the second direction side of the data driver block without passing through other circuit blocks,
The integrated circuit device, wherein the second interface region is arranged on the fourth direction side of the data driver block without passing through another circuit block. In any one of Claims 8 thru | or 10.
The data driver included in the data driver block is:
Each of them outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction,
When the width of the driver cell in the second direction is WD, the width WB of the first to Nth circuit blocks in the second direction is Q × WD ≦ WB <(Q + 1) × An integrated circuit device characterized by being a WD. In claim 11,
When the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of data driver blocks is DBN, and the number of input times of image data input to the driver cell in one horizontal scanning period is IN,
The number Q of the driver cells arranged along the second direction is Q = HPN / (DBN × IN). In any one of Claims 8 thru | or 12.
The first to Nth circuit blocks are:
Including at least one memory block for storing image data;
The data driver included in the data driver block is:
Each of them outputs a data signal corresponding to image data for one pixel, and includes Q driver cells arranged along the second direction,
When the width in the second direction of the driver cell is WD and the width in the second direction of the peripheral circuit portion included in the memory block is WPC, Q × WD ≦ WB <(Q + 1) × An integrated circuit device characterized by being WD + WPC. In claim 13,
When the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of data driver blocks is DBN, and the number of input times of image data input to the driver cell in one horizontal scanning period is IN,
The number Q of the driver cells arranged along the second direction is Q = HPN / (DBN × IN). In claim 13 or 14,
The integrated circuit device, wherein the memory block and the data driver block are arranged adjacent to each other along the first direction. In any of claims 13 to 15,
An integrated circuit device, wherein the image data stored in the memory block is read a plurality of times in one horizontal scanning period from the memory block to the adjacent data driver block. An integrated circuit device according to any one of claims 1 to 16,
A display panel driven by the integrated circuit device;
An electronic device comprising:

Images