JP4270773B2 - 1 chip dual type insulated gate type semiconductor device - Google Patents

1 chip dual type insulated gate type semiconductor device Download PDF

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Publication number
JP4270773B2
JP4270773B2 JP2001173543A JP2001173543A JP4270773B2 JP 4270773 B2 JP4270773 B2 JP 4270773B2 JP 2001173543 A JP2001173543 A JP 2001173543A JP 2001173543 A JP2001173543 A JP 2001173543A JP 4270773 B2 JP4270773 B2 JP 4270773B2
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Prior art keywords
electrode
chip
gate
source
semiconductor device
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JP2001173543A
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JP2002368219A (en
Inventor
雅也 齋藤
慎 及川
充弘 吉村
詔 有山
保裕 五十嵐
弘樹 江藤
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明はＭＯＳＦＥＴに係り、特に二次電池に内蔵できるバッテリーマネジメントを行うＭＯＳＦＥＴ関する。
【０００２】
【従来の技術】
携帯端末の普及に伴い小型で大容量のリチュウムイオン電池が求められるようになってきた。このリチュウムイオン電池の充放電のバッテリーマネージメントを行う保護回路基板は携帯端末の軽量化のニーズにより、より小型で負荷ショートにも十分に耐えうるものでなくてはならない。かかる保護回路装置はリチュウムイオン電池の容器内に内蔵されるために小型化が求められ、チップ部品を多用したＣＯＢ(Ｃｈｉｐ ｏｎ Ｂｏａｒｄ)技術が駆使され、小型化の要求に応えてきた。しかし一方ではリチュウムイオン電池に直列にスイッチング素子を接続するのでこのスイッチング素子のオン抵抗も極めて小さくするニーズがあり、これが携帯電話では通話時間や待機時間を長くするために不可欠の要素である。
【０００３】
また、パワーＭＯＳＦＥＴを基板に実装する場合にその実装面積を低減したり、生産コストを低減するためパワーＭＯＳＦＥＴの用途を汎用的にする等、さまざまな技術課題がある。
【０００４】
図５に具体的なバッテリーマネージメントを行う保護回路を示す。リチュウムイオン電池ＬｉＢに直列に２個のパワーＭＯＳＦＥＴＱ１、Ｑ２を接続し、リチュウムイオン電池ＬｉＢの電圧をコントロールＩＣで検知しながら２個のパワーＭＯＳＦＥＴＱ１、Ｑ２ のオンオフ制御を行って過充電、過放電あるいは負荷ショートからリチュウムイオン電池ＬｉＢを保護している。２個のパワーＭＯＳＦＥＴＱ１、Ｑ２はドレイン電極Ｄを共通接続し、両端にそれぞれのソース電極Ｓが配置され、各々のゲート電極ＧはコントロールＩＣに接続されている。
【０００５】
このパワーＭＯＳＦＥＴＱ１、Ｑ２は薄いゲート酸化膜を静電破壊から保護するためにゲート電極とソース電極間に保護用の双方向ツェナーダイオードが接続されている。
【０００６】
充電時には両端に電源が接続され、リチュウムイオン電池ＬｉＢに充電電流が矢印の方向に供給され充電を行う。リチュウムイオン電池ＬｉＢが過充電になるとコントロールＩＣで電圧の検出をして、パワーＭＯＳＦＥＴＱ２のゲート電圧がＨ(ハイレベル)からＬ（ローレベル）になり、パワーＭＯＳＦＥＴＱ２がオフして回路を遮断してリチュウムイオン電池ＬｉＢの保護をする。
【０００７】
放電時には両端は負荷に接続され、所定の電圧までは携帯端末の動作を行う。しかしリチュウムイオン電池ＬｉＢが過放電となるとコントロールＩＣで電圧を検知して、パワーＭＯＳＦＥＴＱ１のゲート電圧をＨからＬにしてパワーＭＯＳＦＥＴＱ１をオフして回路を遮断してリチュウムイオン電池ＬｉＢの保護を行う。
【０００８】
更に負荷ショート時あるいは過電流が流れた時はパワーＭＯＳＦＥＴＱ１、Ｑ２に大電流が流れ、パワーＭＯＳＦＥＴＱ１、Ｑ２の両端電圧が急激に上昇するので、この電圧をコントロールＩＣで検出して放電時と同様にパワーＭＯＳＦＥＴＱ１をオフして回路を遮断してリチュウムイオン電池ＬｉＢの保護を行う。しかし保護回路が動作するまでの短期間に大電流が流れるため、パワーＭＯＳＦＥＴＱ１、Ｑ２に対してせん頭ドレイン電流の大電流化が要求される。
【０００９】
上記の如く、バッテリマネジメント用としてドレイン共通の１チップデュアル型ＭＯＳＦＥＴは需要が高まっている。
【００１０】
図６に従来の1チップデュアル型ＭＯＳＦＥＴの一例を示す。１チップデュアル型ＭＯＳＦＥＴは２個のパワーＭＯＳＦＥＴを１チップに集積化して表面にソース電極１１とゲートパッド電極１２を有し、裏面全面には金属が蒸着されており、２個のパワーＭＯＳＦＥＴに共通でドレイン電極（図示せず）を設けている。各パワーＭＯＳＦＥＴはチップの中心線Ｙ−Ｙに対して線対称に配置され、それぞれのゲートパッド電極１２は独立してチップのコーナー部分に配置される。ゲートパッド電極１２およびソース電極１１には、丸印で示すボンディングワイヤが熱圧着される。
【００１１】
図７に１個のパワーＭＯＳＦＥＴの詳細な構造を示す。ゲートパッド電極１２の下に保護用のツェナーダイオード１３（同心円の点線）が形成され、点線の丸印で示すようにボンディングワイヤーで電極の取り出しが行われる。実動作領域１６の中にパワーＭＯＳＦＥＴを構成する多数のＭＯＳトランジスタのセル７が配列されている。ソース電極１１は、実動作領域１６上の各セル７のソース領域と接続して設けられる。ゲート連結電極１７は各セル７のゲート電極と接続され且つ実動作領域１６の周囲に配置されている。なお、ソース電極１１には点線の丸印で示すようにボンディングワイヤが熱厚着され、電極の取り出しを行う。
【００１２】
図８に図６のＢ−Ｂ線の断面図を示す。
【００１３】
実動作領域１６はその中にＭＯＳＦＥＴを構成するトレンチ型のＭＯＳトランジスタのセル７が多数個配列されている。ＮチャンネルのパワーＭＯＳＦＥＴにおいては、Ｎ+型の半導体基板１の上にＮ-型のエピタキシャル層からなるドレイン領域２を設け、その上にＰ型のチャネル層３を設ける。チャネル層３からドレイン領域２まで到達するトレンチ４を作り、トレンチ４の内壁をゲート酸化膜５で被膜し、トレンチ４に充填されたポリシリコンよりなるゲート電極６を設けて各セル７を形成する。トレンチ４に隣接したチャネル層３表面にはＮ+型のソース領域８が形成され、隣り合う２つのセルのソース領域８間のチャネル層３表面にはＰ+型のボディコンタクト領域９が形成される。さらにチャネル層３にはソース領域８からトレンチ４に沿ってチャネル領域（図示せず）が形成される。トレンチ４上は層間絶縁膜１０で覆われている。
【００１４】
ソース電極１１は層間絶縁膜１０を介して実動作領域１６上に設けられ、ＭＯＳトランジスタのソース領域８にコンタクトされている。ソース電極１１にはボンディングワイヤ１７が熱圧着され、電極の取り出しを行う。
【００１５】
ドレイン電極１９は、半導体チップの裏面に金等の裏張金属を設け、裏面電極とする。
【００１６】
ゲートパッド電極１２は、実動作領域１６の外側に配置される。ゲートパッド電極１２は、ソース電極１１と同一工程にて形成された電極であり、ゲート電極を延在してコンタクトさせる。ゲートパッド電極１２直下には保護用のツェナーダイオード１３が設けられ、ツェナーダイオード１３の中心はゲートパッド電極１２とコンタクトし、最外周は各セル７のソース電極１１と連結される。ゲートパッド電極１２には、ボンディングワイヤ１８が熱圧着され、電極の取り出しを行う。
【００１７】
半導体チップ最外周となるドレイン領域２には、高濃度領域であるアニュラー１４が幅約０．１６ｍｍに設けられ、信頼性試験におけるリークを防いでいる。
【００１８】
従来の半導体装置の組立工程においては、ウェハからダイシングして分離した半導体素子をリードフレームに固着し、金型と樹脂注入によるトランスファーモールドによって半導体素子を封止し、リードフレームを切断して個々の半導体装置毎に分離する、という工程が行われている。
【００１９】
図９は上記した方法により製造したパワーＭＯＳＦＥＴを示す。図９（Ａ）は上面図であり、Ｃ−Ｃ線の断面図を図９（Ｂ）に示す。
【００２０】
リードフレームは、銅を素材とした打ち抜きフレームであり、このフレームのヘッダー３１上に半田あるいはＡｇペーストよりなるプリフォーム材３２でパワーＭＯＳＦＥＴのベアチップ３３が固着される。パワーＭＯＳＦＥＴのベアチップ３３の下面は金の裏張り電極（図示せず）によりドレイン電極が形成され、上面にはアルミニウム合金のスパッタによりゲート電極とソース電極が形成される。更に、半田および導電材料との抵抗を下げるためＡｕ等の金属多層膜をその上部に蒸着する。フレームのドレイン端子３５はヘッダー３１と連結されているので、ドレイン電極と直結され、ゲート電極およびソース電極はボンディングワイヤ３４によりゲート端子３６およびソース端子３７と電気的に接続される。
【００２１】
ベアチップ３３およびフレームは金型およびトランスファーモールドで樹脂封止され、樹脂層３８はパッケージ外形を構成する。フレームは、半田等によりプリント基板３９に実装される。
【００２２】
【発明が解決しようとする課題】
上記の通り、このリチュウムイオン電池の充放電のバッテリーマネージメントを行う保護回路基板は携帯端末の軽量化のニーズにより、より小型で負荷ショートにも十分に耐えうるものでなくてはならない。かかる保護回路装置はリチュウムイオン電池の容器内に内蔵されるために小型化が求められ、チップ部品を多用したＣＯＢ(Ｃｈｉｐ ｏｎ Ｂｏａｒｄ)技術が駆使され、小型化の要求に応えてきた。
【００２３】
しかし、かかる従来のＭＯＳＦＥＴでは、基板に実装する場合、図９に示す如く、トランスファモールド等でパッケージして実装するか、ベアチップを基板に実装し、ソースおよびゲート電極をボンディングワイヤにより接続している。ベアチップやパッケージ品は、実装面積がチップサイズよりも大きくなり、樹脂層の厚みやボンディングワイヤの高さを必要とするため、市場要求である小型化・薄型化には限界があった。
【００２４】
【課題を解決するための手段】
本発明はかかる課題に鑑みてなされ、表面に２組のソース電極及びゲートパッド電極を有し、裏面に共通のドレイン電極を有する１チップデュアル型ＭＯＳＦＥＴにおいて、前記ソース電極上に設けられる複数のソースバンプ電極および前記ゲートパッド電極上に設けられるゲートバンプ電極をチップの中心線に対して線対称の位置に配置することを特徴とするものであり、１チップデュアル型ＭＯＳＦＥＴをチップサイズで実装できるため小型化・薄型化が実現するものである。
【００２５】
【発明の実施の形態】
本発明の実施の形態を図１から図４を参照して詳細に説明する。本発明の１チップデュアル型ＭＯＳＦＥＴは、２組のソース電極とゲートパッド電極と、ドレイン電極と、ソースバンプ電極と、ゲートバンプ電極とから構成される。
【００２６】
図１に本発明の1チップデュアル型パワーＭＯＳＦＥＴの平面図を示す。尚、この図は電極層の平面図である。
【００２７】
１チップデュアル型ＭＯＳＦＥＴは２個のパワーＭＯＳＦＥＴを１チップに集積化して表面にソース電極１１とゲートパッド電極１２を有し、裏面全面には金属が蒸着されており、２個のパワーＭＯＳＦＥＴに共通でドレイン電極（図示せず）を設けている。各パワーＭＯＳＦＥＴはチップの中心線Ｘ−Ｘに対して線対称に配置され、それぞれのゲートパッド電極１２は独立してチップのコーナー部分に配置される。Ｌｉｂ用途では通常充放電の制御をＩＣから２つのゲート電極に送られる信号で制御している。そのため、ゲートパッド電極１２をＩＣのある側に配置すれば配線等の無駄がなくなるので、ゲートパッド電極１２は半導体チップの同一辺に沿って配置される。
【００２８】
ソースバンプ電極１１０は、ソース電極１１上に複数個設けられた半田バンプである。その数はチップサイズにも依るが、例えば６〜８個程度である。隣接するソースバンプ電極１１０との間隔は０．２mm程度以上とし、なるべく多くのソースバンプ電極１１０が取れるように配置する。また、各バンプ電極によるショートを防ぐため、ソースバンプ電極１１０及びゲートバンプ電極１２０の間隔はショート防止のため０．５mm程度とする。
【００２９】
ゲートバンプ電極１２０は、ゲートパッド電極１２上に１個設ける。ゲートパッド電極１２はＩＣとの配線等の無駄をなくすために、チップ上でＩＣが実装される側（図１ａ側）の同一辺に沿って設けられているため、ゲートバンプ電極１２０もチップの同一辺に沿って設けられる。ここで本発明の実施の形態ではチップのコーナーに配置されているが、ＩＣが実装される側（図１ａ側）の同一辺に沿っていれば、この配置に限らない。
【００３０】
このＭＯＳＦＥＴをフェイスダウンでプリント基板に実装する。つまり、１チップデュアル型ＭＯＳＦＥＴをチップサイズで実装できるわけである。ここで、重要なことは、第１に、各バンプ電極１１０、１２０はチップ中心線Ｘ−Ｘに対して線対称に配置され、ゲートバンプ電極１２０が設けられたチップの同一辺と相対向する他の同一辺側（図１ｂ側）では、ソースバンプ電極１１０は、ゲートバンプ電極１２０側のゲートおよびソースバンプ電極１２０、１１０の配置と異なるように配置されることである。つまり、ゲートバンプ電極１２０が設けられる側（ａ側）と、ゲートバンプ電極１２０が設けられない側（ｂ側）の、各バンプ電極の配置を変えることで、ゲートバンプ電極１２０の位置（向き）を認識するものであり、これにより実装時のチップ認識が容易となる。
【００３１】
第２に、各バンプ電極１１０、１２０の半田バンプを同一径とすることである。具体的には、本発明の実施の形態では、直径０．１９mmであり、このサイズはコスト面で安価なスクリーンプリンティングにより半田バンプを形成する最小の限界値である。各バンプ電極を同一径にすることにより、半導体チップをフェイスダウンでプリント基板に実装した場合にプリント基板と半導体チップが傾かず、水平に実装できる。
【００３２】
図２には、図１の電極層下層にある１個のパワーＭＯＳＦＥＴの詳細な構造をトレンチ型ＭＯＳＦＥＴを例に示す。
【００３３】
実動作領域１６は、この中にパワーＭＯＳＦＥＴを構成する多数のＭＯＳトランジスタのセル７が多数配列されている。
【００３４】
ソース電極１１は、Ａｌ等のスパッタにより実動作領域１６上に設けられ且つ各セル７のソース領域と接続して設けられる。
【００３５】
ゲートパッド電極１２は、ソース電極１１と同一工程にて形成された電極であり、ゲート電極を延在してコンタクトさせる。ゲートパッド電極１２の下には保護用のツェナーダイオードが設けられる。
【００３６】
アニュラー１４は、実動作領域外のドレイン領域に設けられた高濃度領域で、半導体チップの信頼性試験におけるリークを防いでいる。
【００３７】
図３には、図１のＡ−Ａ線の断面図を示す。ＮチャンネルのパワーＭＯＳＦＥＴにおいては、Ｎ+型の半導体基板１の上にＮ-型のエピタキシャル層からなるドレイン領域２を設け、その上にＰ型のチャネル層３を設ける。チャネル層３からドレイン領域２まで到達するトレンチ４を作り、トレンチ４の内壁をゲート酸化膜５被膜し、トレンチ４に充填されたポリシリコンよりなるゲート電極６を設けて各セル７を形成する。トレンチ４に隣接したチャネル層３表面にはＮ+型のソース領域８が形成され、隣り合う２つのセルのソース領域８間のチャネル層３表面にはＰ+型のボディコンタクト領域９が形成される。さらにチャネル層３にはソース領域８からトレンチ４に沿ってチャネル領域（図示せず）が形成される。トレンチ４上は層間絶縁膜１０で覆われている。
【００３８】
ソース電極１１は層間絶縁膜１０を介して実動作領域１６上に設けられ、ＭＯＳトランジスタのソース領域８にコンタクトされている。ソース電極１１には半田バンプが設けられ、ソースバンプ電極１１０として電極の取り出しを行う。
【００３９】
ゲートパッド電極１２は、実動作領域１６の外側に配置される。ゲートパッド電極１２は、ソース電極１１と同一工程にて形成された電極であり、ゲート電極を延在してコンタクトさせる。ゲートパッド電極１２直下には保護用のツェナーダイオード１３が設けられ、ツェナーダイオード１３の中心はゲートパッド電極１２とコンタクトし、最外周は各セル７のソース電極１１と連結される。ゲートパッド電極１２には、半田バンプが設けられ、ゲートバンプ電極１２０として電極の取り出しを行う。
【００４０】
ドレイン電極１９は、半導体チップ裏面に金等の裏張電極を設けて裏面電極とする。
【００４１】
半導体チップ最外周となるドレイン領域２には、高濃度領域であるアニュラー１４が幅約０．１６ｍｍに設けられ、信頼性試験におけるリークを防いでいる。
【００４２】
ソースバンプ電極１１０は、ソース電極１１とコンタクトする半田バンプである。ソース電極１１上で酸化膜（図示せず）を介して設けた窒化膜１５にコンタクト孔を設け、Ｔｉ/Ｎｉ/Ａｕ等により半田の下地となる下地電極１００を設ける。半田を供給し、加熱して球状のソースバンプ電極１１０とする。
【００４３】
ゲートバンプ電極１２０は、ソースバンプ電極１１０と同様に設けた半田バンプであり、下地電極１００を介してゲートパッド電極１２とコンタクトさせる。
【００４４】
金属板１３０は、Ｃｕ、Ｆｅ、Ａｌ等のチップサイズよりも小さい金属片をウエファ上のチップ配置の座標に合わせて半導体チップ裏面のドレイン電極１９上に貼り付ける。この金属板１３０により、ドレイン抵抗を低減できる。
【００４５】
図４には上記のパワーＭＯＳＦＥＴを基板に実装した側面図を示す。
【００４６】
プリント基板３９のボンディングパッド４０上に、半導体チップ３３をフェイスダウンで配置し、各バンプ電極１１０、１２０とボンディングパッド４０の位置あわせを行い、熱による半田リフローや、加圧状態での超音波振動を用いて接着・接続する。これにより、半導体チップサイズ実装できるので、従来と比較して大幅にその実装面積を低減できる。具体的には本発明の実施の形態では、従来品と比較して３０〜４０％の低減となる。また、ボンディングワイヤの高さや樹脂層の厚みが省けるので、薄型化も実現できる。
【００４７】
尚、本発明の二次電池の充放電用保護回路を説明する回路図は、図５と同様であるので、説明は省略する。
【００４８】
本発明の特徴は、半導体チップ表面に同一径のソースバンプ電極１１０およびゲートバンプ電極１２０を設けることである。また、各バンプ電極は半導体チップの中心線に対して線対称に配置され、チップ上でゲートバンプ電極１２０が設けられる側と、ゲートバンプ電極１２０が設けられない側の、各バンプ電極の配置を変えることである。
【００４９】
この構造により、第１に、フェイスダウンでプリント基板へ実装が可能となる。パッケージ品にしたり、ボンディングワイヤによる接続が不要となるので、プリント基板への実装面積がチップサイズで実現でき、具体的にはパッケージ品と比較して実装面積が３０〜４０％と大幅に低減できる。また、実装面積だけでなく、樹脂層の厚みやボンディングワイヤの高さが省けるので、市場要求である小型化、薄型化が可能となる。
【００５０】
第２に、２つのＭＯＳＦＥＴのゲートバンプ電極がチップの同一辺に沿って配置されるのでＩＣとの配線が容易となる。また、チップの同一辺およびその辺と相対向する辺に沿って配置された各バンプ電極の位置の違いによりゲートバンプ電極側が認識できるので、これにより実装時のチップ認識が容易となる。
【００５１】
第３に、パッケージ品と比較してトランスファーモールド等の技術が不要となるのでコストが低減できる。更にパッケージの抵抗も無くなるので、オン抵抗の上昇の抑制に寄与できる。
【００５２】
第４に、半田バンプの直径は全て同一径であるので、フェイスダウンで実装した場合、プリント基板に対して半導体チップが傾かず、水平に実装できる。
【００５３】
第５に、半導体チップ裏面にはＣｕ、Ｆｅ、Ａｌ等の金属板をチップサイズより小さく貼り付けることにより、ダイシング時の半導体チップおよびブレードに与える悪影響を低減できる。
【００５４】
【発明の効果】
本発明に依れば、第１に、１チップデュアル型ＭＯＳＦＥＴをフェイスダウンでプリント基板に実装できることにある。パッケージやボンディングワイヤを使用しないでプリント基板に実装できるため、市場要求である小型化、薄型化が可能となる。具体的には、パッケージ品と比較して実装面積が３０〜４０％低減できる。
【００５５】
第２に、ゲートバンプ電極をチップの同一辺上に設けることでＩＣとの配線が容易となる。また、各バンプ電極をチップ中心線に対して線対称に設け、各バンプ電極の配置を相対向する２辺において異なる配置とすることによりゲートバンプ電極側が認識できるのでプリント基板実装時にチップ認識が容易となる。
【００５６】
第３に、半田バンプの直径は全て同一径であるので、実装時にプリント基板に対して半導体チップが傾かず、水平に実装できる。
【００５７】
第４に、パッケージ品と比較してトランスファーモールド等の技術が不要となるのでコストが低減できる。更にパッケージの抵抗が無くなるため、オン抵抗上昇の抑制に寄与できる。
【００５８】
第５に、半導体チップ裏面に貼り付けた金属板はチップサイズより小さく設けられるため、ダイシング時にチップおよびブレードに与える悪影響を抑制できる。
【図面の簡単な説明】
【図１】本発明のＭＯＳＦＥＴを説明する平面図である。
【図２】本発明のＭＯＳＦＥＴを説明する平面図である。
【図３】本発明のＭＯＳＦＥＴを説明する断面図である。
【図４】本発明のＭＯＳＦＥＴを説明する側面図である。
【図５】従来および本発明の二次電池の充放電用保護回路を説明する回路図である。
【図６】従来のＭＯＳＦＥＴを説明する平面図である。
【図７】従来のＭＯＳＦＥＴを説明する平面図である。
【図８】従来のＭＯＳＦＥＴを説明する断面図である。
【図９】従来のＭＯＳＦＥＴを説明する（Ａ）平面図、（Ｂ）断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOSFET, and more particularly to a MOSFET that performs battery management that can be incorporated in a secondary battery.
[0002]
[Prior art]
With the widespread use of mobile terminals, small and large capacity lithium ion batteries have been demanded. The protection circuit board that performs battery management of charge / discharge of the lithium ion battery must be smaller and can sufficiently withstand a load short circuit due to the need for weight reduction of the portable terminal. Such a protection circuit device is required to be miniaturized because it is built in a container of a lithium ion battery, and COB (Chip on Board) technology using many chip components has been used to meet the demand for miniaturization. However, on the other hand, since a switching element is connected in series with the lithium ion battery, there is a need to extremely reduce the on-resistance of the switching element, which is an indispensable element for extending the talk time and standby time in the mobile phone.
[0003]
In addition, when the power MOSFET is mounted on a substrate, there are various technical problems such as reducing the mounting area and making the power MOSFET versatile to reduce the production cost.
[0004]
FIG. 5 shows a specific protection circuit for battery management. Two power MOSFETs Q1 and Q2 are connected in series to the lithium ion battery LiB, and the on / off control of the two power MOSFETs Q1 and Q2 is performed while the voltage of the lithium ion battery LiB is detected by the control IC. The lithium ion battery LiB is protected from a load short circuit. The two power MOSFETs Q1 and Q2 have a drain electrode D connected in common, source electrodes S are arranged at both ends, and each gate electrode G is connected to a control IC.
[0005]
In the power MOSFETs Q1 and Q2, a protective bidirectional Zener diode is connected between the gate electrode and the source electrode in order to protect the thin gate oxide film from electrostatic breakdown.
[0006]
During charging, power is connected to both ends, and charging is performed by supplying a charging current to the lithium ion battery LiB in the direction of the arrow. When the lithium ion battery LiB is overcharged, the control IC detects the voltage, the gate voltage of the power MOSFET Q2 changes from H (high level) to L (low level), the power MOSFET Q2 turns off and the circuit is shut off. The lithium ion battery LiB is protected.
[0007]
At the time of discharging, both ends are connected to a load, and the mobile terminal is operated up to a predetermined voltage. However, when the lithium ion battery LiB is overdischarged, the voltage is detected by the control IC, the gate voltage of the power MOSFET Q1 is changed from H to L, the power MOSFET Q1 is turned off, the circuit is shut off, and the lithium ion battery LiB is protected.
[0008]
Further, when the load is short-circuited or when an overcurrent flows, a large current flows through the power MOSFETs Q1 and Q2, and the voltage at both ends of the power MOSFETs Q1 and Q2 rapidly rises. The power MOSFET Q1 is turned off to cut off the circuit to protect the lithium ion battery LiB. However, since a large current flows in a short time until the protection circuit operates, it is required to increase the peak drain current for the power MOSFETs Q1 and Q2.
[0009]
As described above, a demand for a single-chip dual MOSFET having a common drain for battery management is increasing.
[0010]
FIG. 6 shows an example of a conventional one-chip dual MOSFET. The 1-chip dual type MOSFET has two power MOSFETs integrated on one chip and has a source electrode 11 and a gate pad electrode 12 on the front surface, and a metal is deposited on the entire back surface, common to the two power MOSFETs. A drain electrode (not shown) is provided. Each power MOSFET is arranged symmetrically with respect to the center line YY of the chip, and each gate pad electrode 12 is independently arranged at a corner portion of the chip. Bonding wires indicated by circles are thermocompression bonded to the gate pad electrode 12 and the source electrode 11.
[0011]
FIG. 7 shows the detailed structure of one power MOSFET. A protective Zener diode 13 (concentric dotted line) is formed under the gate pad electrode 12, and the electrode is taken out with a bonding wire as indicated by a dotted circle. A large number of MOS transistor cells 7 constituting a power MOSFET are arranged in the actual operation region 16. The source electrode 11 is provided in connection with the source region of each cell 7 on the actual operation region 16. The gate connection electrode 17 is connected to the gate electrode of each cell 7 and is disposed around the actual operation region 16. A bonding wire is thermally deposited on the source electrode 11 as indicated by a dotted circle, and the electrode is taken out.
[0012]
FIG. 8 is a sectional view taken along line BB in FIG.
[0013]
In the actual operation region 16, a large number of trench-type MOS transistor cells 7 constituting a MOSFET are arranged. In an N channel power MOSFET, a drain region 2 made of an N − type epitaxial layer is provided on an N + type semiconductor substrate 1, and a P type channel layer 3 is provided thereon. A trench 4 reaching the drain region 2 from the channel layer 3 is formed, the inner wall of the trench 4 is coated with a gate oxide film 5, and a gate electrode 6 made of polysilicon filled in the trench 4 is provided to form each cell 7. . An N + type source region 8 is formed on the surface of the channel layer 3 adjacent to the trench 4, and a P + type body contact region 9 is formed on the surface of the channel layer 3 between the source regions 8 of two adjacent cells. The Further, a channel region (not shown) is formed in the channel layer 3 along the trench 4 from the source region 8. The trench 4 is covered with an interlayer insulating film 10.
[0014]
The source electrode 11 is provided on the actual operation region 16 through the interlayer insulating film 10 and is in contact with the source region 8 of the MOS transistor. A bonding wire 17 is thermocompression bonded to the source electrode 11 to take out the electrode.
[0015]
The drain electrode 19 is formed as a back electrode by providing a backing metal such as gold on the back surface of the semiconductor chip.
[0016]
The gate pad electrode 12 is disposed outside the actual operation region 16. The gate pad electrode 12 is an electrode formed in the same process as the source electrode 11, and extends and contacts the gate electrode. A protective Zener diode 13 is provided immediately below the gate pad electrode 12, the center of the Zener diode 13 is in contact with the gate pad electrode 12, and the outermost periphery is connected to the source electrode 11 of each cell 7. A bonding wire 18 is thermocompression bonded to the gate pad electrode 12 to take out the electrode.
[0017]
The drain region 2 which is the outermost periphery of the semiconductor chip is provided with an annular 14 which is a high concentration region with a width of about 0.16 mm to prevent leakage in the reliability test.
[0018]
In the assembly process of a conventional semiconductor device, a semiconductor element diced and separated from a wafer is fixed to a lead frame, the semiconductor element is sealed by a transfer mold using a mold and resin injection, and the lead frame is cut to obtain individual components. A process of separating each semiconductor device is performed.
[0019]
FIG. 9 shows a power MOSFET manufactured by the method described above. FIG. 9A is a top view, and a cross-sectional view taken along the line CC is shown in FIG.
[0020]
The lead frame is a punched frame made of copper, and a power MOSFET bare chip 33 is fixed on a header 31 of the frame by a preform material 32 made of solder or Ag paste. A drain electrode is formed on the lower surface of the bare chip 33 of the power MOSFET by a gold backing electrode (not shown), and a gate electrode and a source electrode are formed on the upper surface by sputtering of an aluminum alloy. Further, a metal multilayer film such as Au is deposited on the upper portion in order to lower the resistance to the solder and the conductive material. Since the drain terminal 35 of the frame is connected to the header 31, it is directly connected to the drain electrode, and the gate electrode and the source electrode are electrically connected to the gate terminal 36 and the source terminal 37 by the bonding wire 34.
[0021]
The bare chip 33 and the frame are resin-sealed by a mold and a transfer mold, and the resin layer 38 constitutes the package outer shape. The frame is mounted on the printed circuit board 39 with solder or the like.
[0022]
[Problems to be solved by the invention]
As described above, the protection circuit board that performs battery management of charging and discharging of the lithium ion battery must be smaller and can sufficiently withstand a load short circuit due to the need for weight reduction of the portable terminal. Such a protection circuit device is required to be miniaturized because it is built in a container of a lithium ion battery, and COB (Chip on Board) technology using many chip components has been used to meet the demand for miniaturization.
[0023]
However, in such a conventional MOSFET, when mounted on a substrate, as shown in FIG. 9, the package is mounted by transfer molding or the like, or a bare chip is mounted on the substrate, and the source and gate electrodes are connected by bonding wires. . Bare chips and packaged products have a mounting area larger than the chip size, and require a resin layer thickness and a bonding wire height, so there is a limit to miniaturization and thinning which are market demands.
[0024]
[Means for Solving the Problems]
The present invention has been made in view of such problems, and in a one-chip dual MOSFET having two sets of source electrodes and gate pad electrodes on the front surface and a common drain electrode on the back surface, a plurality of sources provided on the source electrode The bump electrode and the gate bump electrode provided on the gate pad electrode are arranged in a line-symmetrical position with respect to the center line of the chip, and a one-chip dual MOSFET can be mounted in a chip size. A reduction in size and thickness is realized.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail with reference to FIGS. The one-chip dual MOSFET of the present invention is composed of two sets of source electrode, gate pad electrode, drain electrode, source bump electrode, and gate bump electrode.
[0026]
FIG. 1 is a plan view of a one-chip dual type power MOSFET of the present invention. This figure is a plan view of the electrode layer.
[0027]
The 1-chip dual type MOSFET has two power MOSFETs integrated on one chip and has a source electrode 11 and a gate pad electrode 12 on the front surface, and a metal is deposited on the entire back surface, common to the two power MOSFETs. A drain electrode (not shown) is provided. Each power MOSFET is arranged symmetrically with respect to the center line XX of the chip, and each gate pad electrode 12 is independently arranged at a corner portion of the chip. In the Lib application, charge / discharge control is normally controlled by signals sent from the IC to the two gate electrodes. For this reason, if the gate pad electrode 12 is arranged on the side where the IC is present, wiring and the like are not wasted. Therefore, the gate pad electrode 12 is arranged along the same side of the semiconductor chip.
[0028]
The source bump electrodes 110 are a plurality of solder bumps provided on the source electrode 11. The number depends on the chip size, but is about 6 to 8, for example. An interval between adjacent source bump electrodes 110 is set to about 0.2 mm or more, and the source bump electrodes 110 are arranged so that as many source bump electrodes 110 as possible can be obtained. In addition, in order to prevent a short circuit due to each bump electrode, the distance between the source bump electrode 110 and the gate bump electrode 120 is set to about 0.5 mm to prevent the short circuit.
[0029]
One gate bump electrode 120 is provided on the gate pad electrode 12. Since the gate pad electrode 12 is provided along the same side on the side where the IC is mounted (FIG. 1a side) on the chip in order to eliminate waste of wiring and the like with the IC, the gate bump electrode 120 is also formed on the chip. Provided along the same side. Here, in the embodiment of the present invention, it is arranged at the corner of the chip, but it is not limited to this arrangement as long as it is along the same side on the IC mounting side (FIG. 1a side).
[0030]
This MOSFET is mounted face-down on a printed circuit board. That is, a one-chip dual MOSFET can be mounted in a chip size. Here, what is important is that, firstly, the bump electrodes 110 and 120 are arranged symmetrically with respect to the chip center line XX and face the same side of the chip on which the gate bump electrode 120 is provided. On the other same side (FIG. 1 b side), the source bump electrode 110 is arranged differently from the arrangement of the gate and source bump electrodes 120, 110 on the gate bump electrode 120 side. That is, the position (orientation) of the gate bump electrode 120 is changed by changing the arrangement of the bump electrodes on the side where the gate bump electrode 120 is provided (a side) and the side where the gate bump electrode 120 is not provided (b side). This facilitates chip recognition during mounting.
[0031]
Second, the solder bumps of the bump electrodes 110 and 120 have the same diameter. Specifically, in the embodiment of the present invention, the diameter is 0.19 mm, and this size is the minimum limit value for forming solder bumps by cost-effective and low cost screen printing. By making each bump electrode have the same diameter, when the semiconductor chip is mounted face-down on the printed circuit board, the printed circuit board and the semiconductor chip are not inclined and can be mounted horizontally.
[0032]
FIG. 2 shows a detailed structure of one power MOSFET in the lower layer of the electrode layer of FIG. 1 by taking a trench MOSFET as an example.
[0033]
In the actual operation region 16, a large number of cells 7 of a large number of MOS transistors constituting a power MOSFET are arranged therein.
[0034]
The source electrode 11 is provided on the actual operation region 16 by sputtering of Al or the like and is connected to the source region of each cell 7.
[0035]
The gate pad electrode 12 is an electrode formed in the same process as the source electrode 11, and extends and contacts the gate electrode. A protective Zener diode is provided under the gate pad electrode 12.
[0036]
The annular 14 is a high concentration region provided in the drain region outside the actual operation region, and prevents leakage in the reliability test of the semiconductor chip.
[0037]
FIG. 3 is a sectional view taken along line AA in FIG. In an N channel power MOSFET, a drain region 2 made of an N − type epitaxial layer is provided on an N + type semiconductor substrate 1, and a P type channel layer 3 is provided thereon. A trench 4 reaching from the channel layer 3 to the drain region 2 is formed, an inner wall of the trench 4 is coated with a gate oxide film 5, and a gate electrode 6 made of polysilicon filled in the trench 4 is provided to form each cell 7. An N + type source region 8 is formed on the surface of the channel layer 3 adjacent to the trench 4, and a P + type body contact region 9 is formed on the surface of the channel layer 3 between the source regions 8 of two adjacent cells. The Further, a channel region (not shown) is formed in the channel layer 3 along the trench 4 from the source region 8. The trench 4 is covered with an interlayer insulating film 10.
[0038]
The source electrode 11 is provided on the actual operation region 16 through the interlayer insulating film 10 and is in contact with the source region 8 of the MOS transistor. The source electrode 11 is provided with a solder bump, and the electrode is taken out as the source bump electrode 110.
[0039]
The gate pad electrode 12 is disposed outside the actual operation region 16. The gate pad electrode 12 is an electrode formed in the same process as the source electrode 11, and extends and contacts the gate electrode. A protective Zener diode 13 is provided immediately below the gate pad electrode 12, the center of the Zener diode 13 is in contact with the gate pad electrode 12, and the outermost periphery is connected to the source electrode 11 of each cell 7. The gate pad electrode 12 is provided with a solder bump, and the electrode is taken out as the gate bump electrode 120.
[0040]
The drain electrode 19 is used as a back electrode by providing a backing electrode such as gold on the back surface of the semiconductor chip.
[0041]
The drain region 2 which is the outermost periphery of the semiconductor chip is provided with an annular 14 which is a high concentration region with a width of about 0.16 mm to prevent leakage in the reliability test.
[0042]
The source bump electrode 110 is a solder bump that contacts the source electrode 11. A contact hole is provided in the nitride film 15 provided on the source electrode 11 via an oxide film (not shown), and a base electrode 100 serving as a solder base is provided by Ti / Ni / Au or the like. Solder is supplied and heated to form a spherical source bump electrode 110.
[0043]
The gate bump electrode 120 is a solder bump provided in the same manner as the source bump electrode 110 and is in contact with the gate pad electrode 12 through the base electrode 100.
[0044]
The metal plate 130 affixes a metal piece smaller than the chip size such as Cu, Fe, Al, etc. on the drain electrode 19 on the back surface of the semiconductor chip in accordance with the chip arrangement coordinates on the wafer. This metal plate 130 can reduce drain resistance.
[0045]
FIG. 4 shows a side view of the power MOSFET mounted on a substrate.
[0046]
The semiconductor chip 33 is arranged face down on the bonding pad 40 of the printed circuit board 39, the bump electrodes 110, 120 and the bonding pad 40 are aligned, solder reflow due to heat, and ultrasonic vibration in a pressurized state. Adhere and connect using. Thereby, since the semiconductor chip size can be mounted, the mounting area can be greatly reduced as compared with the conventional case. Specifically, in the embodiment of the present invention, the reduction is 30 to 40% compared to the conventional product. Further, since the height of the bonding wire and the thickness of the resin layer can be omitted, a reduction in thickness can be realized.
[0047]
In addition, since the circuit diagram explaining the protection circuit for charging / discharging of the secondary battery of this invention is the same as that of FIG. 5, description is abbreviate | omitted.
[0048]
A feature of the present invention is that the source bump electrode 110 and the gate bump electrode 120 having the same diameter are provided on the surface of the semiconductor chip. Also, each bump electrode is arranged symmetrically with respect to the center line of the semiconductor chip, and the arrangement of the bump electrodes on the side where the gate bump electrode 120 is provided on the chip and the side where the gate bump electrode 120 is not provided is arranged. To change.
[0049]
With this structure, first, it can be mounted face-down on a printed circuit board. Since it is not necessary to use a package or connection by bonding wires, the mounting area on the printed circuit board can be realized in a chip size. Specifically, the mounting area can be greatly reduced to 30 to 40% compared to the package product. . Further, not only the mounting area but also the thickness of the resin layer and the height of the bonding wire can be omitted, so that it is possible to reduce the size and thickness as required in the market.
[0050]
Second, since the gate bump electrodes of the two MOSFETs are arranged along the same side of the chip, wiring with the IC is facilitated. Further, since the gate bump electrode side can be recognized by the difference in the position of each bump electrode arranged along the same side of the chip and the side opposite to the side, this facilitates chip recognition at the time of mounting.
[0051]
Thirdly, since a technique such as transfer molding is not required as compared with package products, the cost can be reduced. Further, since the resistance of the package is eliminated, it is possible to contribute to the suppression of an increase in on-resistance.
[0052]
Fourth, since all the solder bumps have the same diameter, when mounted face down, the semiconductor chip does not tilt with respect to the printed circuit board and can be mounted horizontally.
[0053]
Fifth, by attaching a metal plate such as Cu, Fe, Al or the like smaller than the chip size on the back surface of the semiconductor chip, adverse effects on the semiconductor chip and the blade during dicing can be reduced.
[0054]
【The invention's effect】
According to the present invention, firstly, a one-chip dual MOSFET can be mounted on a printed circuit board face down. Since it can be mounted on a printed circuit board without using a package or bonding wire, it is possible to reduce the size and thickness as required by the market. Specifically, the mounting area can be reduced by 30 to 40% compared to the package product.
[0055]
Second, by providing the gate bump electrode on the same side of the chip, wiring with the IC is facilitated. In addition, each bump electrode is arranged symmetrically with respect to the chip center line, and the arrangement of each bump electrode is different on the two opposite sides so that the gate bump electrode side can be recognized, so chip recognition is easy when mounting on a printed circuit board. It becomes.
[0056]
Thirdly, since all the solder bumps have the same diameter, the semiconductor chip can be mounted horizontally without being inclined with respect to the printed board at the time of mounting.
[0057]
Fourth, a technique such as transfer molding is not required as compared with a package product, so that the cost can be reduced. Furthermore, since the resistance of the package is eliminated, it is possible to contribute to the suppression of an increase in on-resistance.
[0058]
Fifth, since the metal plate attached to the back surface of the semiconductor chip is provided smaller than the chip size, adverse effects on the chip and the blade during dicing can be suppressed.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a MOSFET of the present invention.
FIG. 2 is a plan view illustrating a MOSFET of the present invention.
FIG. 3 is a cross-sectional view illustrating a MOSFET of the present invention.
FIG. 4 is a side view illustrating a MOSFET of the present invention.
FIG. 5 is a circuit diagram for explaining a conventional protection circuit for charging and discharging a secondary battery according to the present invention.
FIG. 6 is a plan view illustrating a conventional MOSFET.
FIG. 7 is a plan view illustrating a conventional MOSFET.
FIG. 8 is a cross-sectional view illustrating a conventional MOSFET.
FIG. 9A is a plan view and FIG. 9B is a sectional view for explaining a conventional MOSFET.

Claims (7)

表面に２組のソース電極及びゲートパッド電極を有し、裏面に共通のドレイン電極を有する１チップデュアル型ＭＯＳＦＥＴにおいて、
前記ソース電極上に設けられる複数のソースバンプ電極および前記ゲートパッド電極上に設けられるゲートバンプ電極をチップの中心線に対して線対称の位置に配置することを特徴とする１チップデュアル型絶縁ゲート型半導体装置。In a one-chip dual MOSFET having two sets of source and gate pad electrodes on the front surface and a common drain electrode on the back surface,
A one-chip dual type insulated gate, wherein a plurality of source bump electrodes provided on the source electrode and a gate bump electrode provided on the gate pad electrode are arranged in a line-symmetric position with respect to a center line of the chip. Type semiconductor device. 前記２組のゲートバンプ電極はチップの同一辺に沿って設けることを特徴とする請求項１に記載の１チップデュアル型絶縁ゲート型半導体装置。2. The one-chip dual insulated gate semiconductor device according to claim 1, wherein the two sets of gate bump electrodes are provided along the same side of the chip. 前記チップの同一辺と相対向する他の同一辺側の前記ソースバンプ電極の配置は前記同一辺側のゲートおよびソースバンプ電極の配置と異なることを特徴とする請求項１に記載の１チップデュアル型絶縁ゲート型半導体装置。2. The one-chip dual according to claim 1, wherein the arrangement of the source bump electrodes on the same side opposite to the same side of the chip is different from the arrangement of the gate and source bump electrodes on the same side. Type insulated gate semiconductor device. 前記ドレイン電極には、チップサイズよりも小さい金属板を設けることを特徴とする請求項１に記載の１チップデュアル型絶縁ゲート型半導体装置。2. The one-chip dual type insulated gate semiconductor device according to claim 1, wherein the drain electrode is provided with a metal plate smaller than a chip size. 前記バンプ電極はすべて同一径であることを特徴とする請求項１に記載の１チップデュアル型絶縁ゲート型半導体装置。2. The one-chip dual insulated gate semiconductor device according to claim 1, wherein all the bump electrodes have the same diameter. 前記チップは、プリント基板にフェイスダウンで実装されることを特徴とする請求項１に記載の１チップデュアル型絶縁ゲート型半導体装置。2. The one-chip dual insulated gate semiconductor device according to claim 1, wherein the chip is mounted face-down on a printed circuit board. 前記ソースバンプ電極は前記ゲートバンプ電極より多く設けることを特徴とする請求項１に記載の１チップデュアル型絶縁ゲート型半導体装置。2. The one-chip dual type insulated gate semiconductor device according to claim 1, wherein the source bump electrode is provided more than the gate bump electrode.
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