JP4270773B2 - 1 chip dual type insulated gate type semiconductor device - Google Patents
1 chip dual type insulated gate type semiconductor device Download PDFInfo
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- JP4270773B2 JP4270773B2 JP2001173543A JP2001173543A JP4270773B2 JP 4270773 B2 JP4270773 B2 JP 4270773B2 JP 2001173543 A JP2001173543 A JP 2001173543A JP 2001173543 A JP2001173543 A JP 2001173543A JP 4270773 B2 JP4270773 B2 JP 4270773B2
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- 239000004065 semiconductor Substances 0.000 title claims description 32
- 230000009977 dual effect Effects 0.000 title claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 19
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 15
- 229910001416 lithium ion Inorganic materials 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 15
- 108091006146 Channels Proteins 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 239000013585 weight reducing agent Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Description
【0001】
【発明の属する技術分野】
本発明はMOSFETに係り、特に二次電池に内蔵できるバッテリーマネジメントを行うMOSFET関する。
【0002】
【従来の技術】
携帯端末の普及に伴い小型で大容量のリチュウムイオン電池が求められるようになってきた。このリチュウムイオン電池の充放電のバッテリーマネージメントを行う保護回路基板は携帯端末の軽量化のニーズにより、より小型で負荷ショートにも十分に耐えうるものでなくてはならない。かかる保護回路装置はリチュウムイオン電池の容器内に内蔵されるために小型化が求められ、チップ部品を多用したCOB(Chip on Board)技術が駆使され、小型化の要求に応えてきた。しかし一方ではリチュウムイオン電池に直列にスイッチング素子を接続するのでこのスイッチング素子のオン抵抗も極めて小さくするニーズがあり、これが携帯電話では通話時間や待機時間を長くするために不可欠の要素である。
【0003】
また、パワーMOSFETを基板に実装する場合にその実装面積を低減したり、生産コストを低減するためパワーMOSFETの用途を汎用的にする等、さまざまな技術課題がある。
【0004】
図5に具体的なバッテリーマネージメントを行う保護回路を示す。リチュウムイオン電池LiBに直列に2個のパワーMOSFETQ1、Q2を接続し、リチュウムイオン電池LiBの電圧をコントロールICで検知しながら2個のパワーMOSFETQ1、Q2 のオンオフ制御を行って過充電、過放電あるいは負荷ショートからリチュウムイオン電池LiBを保護している。2個のパワーMOSFETQ1、Q2はドレイン電極Dを共通接続し、両端にそれぞれのソース電極Sが配置され、各々のゲート電極GはコントロールICに接続されている。
【0005】
このパワーMOSFETQ1、Q2は薄いゲート酸化膜を静電破壊から保護するためにゲート電極とソース電極間に保護用の双方向ツェナーダイオードが接続されている。
【0006】
充電時には両端に電源が接続され、リチュウムイオン電池LiBに充電電流が矢印の方向に供給され充電を行う。リチュウムイオン電池LiBが過充電になるとコントロールICで電圧の検出をして、パワーMOSFETQ2のゲート電圧がH(ハイレベル)からL(ローレベル)になり、パワーMOSFETQ2がオフして回路を遮断してリチュウムイオン電池LiBの保護をする。
【0007】
放電時には両端は負荷に接続され、所定の電圧までは携帯端末の動作を行う。しかしリチュウムイオン電池LiBが過放電となるとコントロールICで電圧を検知して、パワーMOSFETQ1のゲート電圧をHからLにしてパワーMOSFETQ1をオフして回路を遮断してリチュウムイオン電池LiBの保護を行う。
【0008】
更に負荷ショート時あるいは過電流が流れた時はパワーMOSFETQ1、Q2に大電流が流れ、パワーMOSFETQ1、Q2の両端電圧が急激に上昇するので、この電圧をコントロールICで検出して放電時と同様にパワーMOSFETQ1をオフして回路を遮断してリチュウムイオン電池LiBの保護を行う。しかし保護回路が動作するまでの短期間に大電流が流れるため、パワーMOSFETQ1、Q2に対してせん頭ドレイン電流の大電流化が要求される。
【0009】
上記の如く、バッテリマネジメント用としてドレイン共通の1チップデュアル型MOSFETは需要が高まっている。
【0010】
図6に従来の1チップデュアル型MOSFETの一例を示す。1チップデュアル型MOSFETは2個のパワーMOSFETを1チップに集積化して表面にソース電極11とゲートパッド電極12を有し、裏面全面には金属が蒸着されており、2個のパワーMOSFETに共通でドレイン電極(図示せず)を設けている。各パワーMOSFETはチップの中心線Y−Yに対して線対称に配置され、それぞれのゲートパッド電極12は独立してチップのコーナー部分に配置される。ゲートパッド電極12およびソース電極11には、丸印で示すボンディングワイヤが熱圧着される。
【0011】
図7に1個のパワーMOSFETの詳細な構造を示す。ゲートパッド電極12の下に保護用のツェナーダイオード13(同心円の点線)が形成され、点線の丸印で示すようにボンディングワイヤーで電極の取り出しが行われる。実動作領域16の中にパワーMOSFETを構成する多数のMOSトランジスタのセル7が配列されている。ソース電極11は、実動作領域16上の各セル7のソース領域と接続して設けられる。ゲート連結電極17は各セル7のゲート電極と接続され且つ実動作領域16の周囲に配置されている。なお、ソース電極11には点線の丸印で示すようにボンディングワイヤが熱厚着され、電極の取り出しを行う。
【0012】
図8に図6のB−B線の断面図を示す。
【0013】
実動作領域16はその中にMOSFETを構成するトレンチ型のMOSトランジスタのセル7が多数個配列されている。NチャンネルのパワーMOSFETにおいては、N+型の半導体基板1の上にN-型のエピタキシャル層からなるドレイン領域2を設け、その上にP型のチャネル層3を設ける。チャネル層3からドレイン領域2まで到達するトレンチ4を作り、トレンチ4の内壁をゲート酸化膜5で被膜し、トレンチ4に充填されたポリシリコンよりなるゲート電極6を設けて各セル7を形成する。トレンチ4に隣接したチャネル層3表面にはN+型のソース領域8が形成され、隣り合う2つのセルのソース領域8間のチャネル層3表面にはP+型のボディコンタクト領域9が形成される。さらにチャネル層3にはソース領域8からトレンチ4に沿ってチャネル領域(図示せず)が形成される。トレンチ4上は層間絶縁膜10で覆われている。
【0014】
ソース電極11は層間絶縁膜10を介して実動作領域16上に設けられ、MOSトランジスタのソース領域8にコンタクトされている。ソース電極11にはボンディングワイヤ17が熱圧着され、電極の取り出しを行う。
【0015】
ドレイン電極19は、半導体チップの裏面に金等の裏張金属を設け、裏面電極とする。
【0016】
ゲートパッド電極12は、実動作領域16の外側に配置される。ゲートパッド電極12は、ソース電極11と同一工程にて形成された電極であり、ゲート電極を延在してコンタクトさせる。ゲートパッド電極12直下には保護用のツェナーダイオード13が設けられ、ツェナーダイオード13の中心はゲートパッド電極12とコンタクトし、最外周は各セル7のソース電極11と連結される。ゲートパッド電極12には、ボンディングワイヤ18が熱圧着され、電極の取り出しを行う。
【0017】
半導体チップ最外周となるドレイン領域2には、高濃度領域であるアニュラー14が幅約0.16mmに設けられ、信頼性試験におけるリークを防いでいる。
【0018】
従来の半導体装置の組立工程においては、ウェハからダイシングして分離した半導体素子をリードフレームに固着し、金型と樹脂注入によるトランスファーモールドによって半導体素子を封止し、リードフレームを切断して個々の半導体装置毎に分離する、という工程が行われている。
【0019】
図9は上記した方法により製造したパワーMOSFETを示す。図9(A)は上面図であり、C−C線の断面図を図9(B)に示す。
【0020】
リードフレームは、銅を素材とした打ち抜きフレームであり、このフレームのヘッダー31上に半田あるいはAgペーストよりなるプリフォーム材32でパワーMOSFETのベアチップ33が固着される。パワーMOSFETのベアチップ33の下面は金の裏張り電極(図示せず)によりドレイン電極が形成され、上面にはアルミニウム合金のスパッタによりゲート電極とソース電極が形成される。更に、半田および導電材料との抵抗を下げるためAu等の金属多層膜をその上部に蒸着する。フレームのドレイン端子35はヘッダー31と連結されているので、ドレイン電極と直結され、ゲート電極およびソース電極はボンディングワイヤ34によりゲート端子36およびソース端子37と電気的に接続される。
【0021】
ベアチップ33およびフレームは金型およびトランスファーモールドで樹脂封止され、樹脂層38はパッケージ外形を構成する。フレームは、半田等によりプリント基板39に実装される。
【0022】
【発明が解決しようとする課題】
上記の通り、このリチュウムイオン電池の充放電のバッテリーマネージメントを行う保護回路基板は携帯端末の軽量化のニーズにより、より小型で負荷ショートにも十分に耐えうるものでなくてはならない。かかる保護回路装置はリチュウムイオン電池の容器内に内蔵されるために小型化が求められ、チップ部品を多用したCOB(Chip on Board)技術が駆使され、小型化の要求に応えてきた。
【0023】
しかし、かかる従来のMOSFETでは、基板に実装する場合、図9に示す如く、トランスファモールド等でパッケージして実装するか、ベアチップを基板に実装し、ソースおよびゲート電極をボンディングワイヤにより接続している。ベアチップやパッケージ品は、実装面積がチップサイズよりも大きくなり、樹脂層の厚みやボンディングワイヤの高さを必要とするため、市場要求である小型化・薄型化には限界があった。
【0024】
【課題を解決するための手段】
本発明はかかる課題に鑑みてなされ、表面に2組のソース電極及びゲートパッド電極を有し、裏面に共通のドレイン電極を有する1チップデュアル型MOSFETにおいて、前記ソース電極上に設けられる複数のソースバンプ電極および前記ゲートパッド電極上に設けられるゲートバンプ電極をチップの中心線に対して線対称の位置に配置することを特徴とするものであり、1チップデュアル型MOSFETをチップサイズで実装できるため小型化・薄型化が実現するものである。
【0025】
【発明の実施の形態】
本発明の実施の形態を図1から図4を参照して詳細に説明する。本発明の1チップデュアル型MOSFETは、2組のソース電極とゲートパッド電極と、ドレイン電極と、ソースバンプ電極と、ゲートバンプ電極とから構成される。
【0026】
図1に本発明の1チップデュアル型パワーMOSFETの平面図を示す。尚、この図は電極層の平面図である。
【0027】
1チップデュアル型MOSFETは2個のパワーMOSFETを1チップに集積化して表面にソース電極11とゲートパッド電極12を有し、裏面全面には金属が蒸着されており、2個のパワーMOSFETに共通でドレイン電極(図示せず)を設けている。各パワーMOSFETはチップの中心線X−Xに対して線対称に配置され、それぞれのゲートパッド電極12は独立してチップのコーナー部分に配置される。Lib用途では通常充放電の制御をICから2つのゲート電極に送られる信号で制御している。そのため、ゲートパッド電極12をICのある側に配置すれば配線等の無駄がなくなるので、ゲートパッド電極12は半導体チップの同一辺に沿って配置される。
【0028】
ソースバンプ電極110は、ソース電極11上に複数個設けられた半田バンプである。その数はチップサイズにも依るが、例えば6〜8個程度である。隣接するソースバンプ電極110との間隔は0.2mm程度以上とし、なるべく多くのソースバンプ電極110が取れるように配置する。また、各バンプ電極によるショートを防ぐため、ソースバンプ電極110及びゲートバンプ電極120の間隔はショート防止のため0.5mm程度とする。
【0029】
ゲートバンプ電極120は、ゲートパッド電極12上に1個設ける。ゲートパッド電極12はICとの配線等の無駄をなくすために、チップ上でICが実装される側(図1a側)の同一辺に沿って設けられているため、ゲートバンプ電極120もチップの同一辺に沿って設けられる。ここで本発明の実施の形態ではチップのコーナーに配置されているが、ICが実装される側(図1a側)の同一辺に沿っていれば、この配置に限らない。
【0030】
このMOSFETをフェイスダウンでプリント基板に実装する。つまり、1チップデュアル型MOSFETをチップサイズで実装できるわけである。ここで、重要なことは、第1に、各バンプ電極110、120はチップ中心線X−Xに対して線対称に配置され、ゲートバンプ電極120が設けられたチップの同一辺と相対向する他の同一辺側(図1b側)では、ソースバンプ電極110は、ゲートバンプ電極120側のゲートおよびソースバンプ電極120、110の配置と異なるように配置されることである。つまり、ゲートバンプ電極120が設けられる側(a側)と、ゲートバンプ電極120が設けられない側(b側)の、各バンプ電極の配置を変えることで、ゲートバンプ電極120の位置(向き)を認識するものであり、これにより実装時のチップ認識が容易となる。
【0031】
第2に、各バンプ電極110、120の半田バンプを同一径とすることである。具体的には、本発明の実施の形態では、直径0.19mmであり、このサイズはコスト面で安価なスクリーンプリンティングにより半田バンプを形成する最小の限界値である。各バンプ電極を同一径にすることにより、半導体チップをフェイスダウンでプリント基板に実装した場合にプリント基板と半導体チップが傾かず、水平に実装できる。
【0032】
図2には、図1の電極層下層にある1個のパワーMOSFETの詳細な構造をトレンチ型MOSFETを例に示す。
【0033】
実動作領域16は、この中にパワーMOSFETを構成する多数のMOSトランジスタのセル7が多数配列されている。
【0034】
ソース電極11は、Al等のスパッタにより実動作領域16上に設けられ且つ各セル7のソース領域と接続して設けられる。
【0035】
ゲートパッド電極12は、ソース電極11と同一工程にて形成された電極であり、ゲート電極を延在してコンタクトさせる。ゲートパッド電極12の下には保護用のツェナーダイオードが設けられる。
【0036】
アニュラー14は、実動作領域外のドレイン領域に設けられた高濃度領域で、半導体チップの信頼性試験におけるリークを防いでいる。
【0037】
図3には、図1のA−A線の断面図を示す。NチャンネルのパワーMOSFETにおいては、N+型の半導体基板1の上にN-型のエピタキシャル層からなるドレイン領域2を設け、その上にP型のチャネル層3を設ける。チャネル層3からドレイン領域2まで到達するトレンチ4を作り、トレンチ4の内壁をゲート酸化膜5被膜し、トレンチ4に充填されたポリシリコンよりなるゲート電極6を設けて各セル7を形成する。トレンチ4に隣接したチャネル層3表面にはN+型のソース領域8が形成され、隣り合う2つのセルのソース領域8間のチャネル層3表面にはP+型のボディコンタクト領域9が形成される。さらにチャネル層3にはソース領域8からトレンチ4に沿ってチャネル領域(図示せず)が形成される。トレンチ4上は層間絶縁膜10で覆われている。
【0038】
ソース電極11は層間絶縁膜10を介して実動作領域16上に設けられ、MOSトランジスタのソース領域8にコンタクトされている。ソース電極11には半田バンプが設けられ、ソースバンプ電極110として電極の取り出しを行う。
【0039】
ゲートパッド電極12は、実動作領域16の外側に配置される。ゲートパッド電極12は、ソース電極11と同一工程にて形成された電極であり、ゲート電極を延在してコンタクトさせる。ゲートパッド電極12直下には保護用のツェナーダイオード13が設けられ、ツェナーダイオード13の中心はゲートパッド電極12とコンタクトし、最外周は各セル7のソース電極11と連結される。ゲートパッド電極12には、半田バンプが設けられ、ゲートバンプ電極120として電極の取り出しを行う。
【0040】
ドレイン電極19は、半導体チップ裏面に金等の裏張電極を設けて裏面電極とする。
【0041】
半導体チップ最外周となるドレイン領域2には、高濃度領域であるアニュラー14が幅約0.16mmに設けられ、信頼性試験におけるリークを防いでいる。
【0042】
ソースバンプ電極110は、ソース電極11とコンタクトする半田バンプである。ソース電極11上で酸化膜(図示せず)を介して設けた窒化膜15にコンタクト孔を設け、Ti/Ni/Au等により半田の下地となる下地電極100を設ける。半田を供給し、加熱して球状のソースバンプ電極110とする。
【0043】
ゲートバンプ電極120は、ソースバンプ電極110と同様に設けた半田バンプであり、下地電極100を介してゲートパッド電極12とコンタクトさせる。
【0044】
金属板130は、Cu、Fe、Al等のチップサイズよりも小さい金属片をウエファ上のチップ配置の座標に合わせて半導体チップ裏面のドレイン電極19上に貼り付ける。この金属板130により、ドレイン抵抗を低減できる。
【0045】
図4には上記のパワーMOSFETを基板に実装した側面図を示す。
【0046】
プリント基板39のボンディングパッド40上に、半導体チップ33をフェイスダウンで配置し、各バンプ電極110、120とボンディングパッド40の位置あわせを行い、熱による半田リフローや、加圧状態での超音波振動を用いて接着・接続する。これにより、半導体チップサイズ実装できるので、従来と比較して大幅にその実装面積を低減できる。具体的には本発明の実施の形態では、従来品と比較して30〜40%の低減となる。また、ボンディングワイヤの高さや樹脂層の厚みが省けるので、薄型化も実現できる。
【0047】
尚、本発明の二次電池の充放電用保護回路を説明する回路図は、図5と同様であるので、説明は省略する。
【0048】
本発明の特徴は、半導体チップ表面に同一径のソースバンプ電極110およびゲートバンプ電極120を設けることである。また、各バンプ電極は半導体チップの中心線に対して線対称に配置され、チップ上でゲートバンプ電極120が設けられる側と、ゲートバンプ電極120が設けられない側の、各バンプ電極の配置を変えることである。
【0049】
この構造により、第1に、フェイスダウンでプリント基板へ実装が可能となる。パッケージ品にしたり、ボンディングワイヤによる接続が不要となるので、プリント基板への実装面積がチップサイズで実現でき、具体的にはパッケージ品と比較して実装面積が30〜40%と大幅に低減できる。また、実装面積だけでなく、樹脂層の厚みやボンディングワイヤの高さが省けるので、市場要求である小型化、薄型化が可能となる。
【0050】
第2に、2つのMOSFETのゲートバンプ電極がチップの同一辺に沿って配置されるのでICとの配線が容易となる。また、チップの同一辺およびその辺と相対向する辺に沿って配置された各バンプ電極の位置の違いによりゲートバンプ電極側が認識できるので、これにより実装時のチップ認識が容易となる。
【0051】
第3に、パッケージ品と比較してトランスファーモールド等の技術が不要となるのでコストが低減できる。更にパッケージの抵抗も無くなるので、オン抵抗の上昇の抑制に寄与できる。
【0052】
第4に、半田バンプの直径は全て同一径であるので、フェイスダウンで実装した場合、プリント基板に対して半導体チップが傾かず、水平に実装できる。
【0053】
第5に、半導体チップ裏面にはCu、Fe、Al等の金属板をチップサイズより小さく貼り付けることにより、ダイシング時の半導体チップおよびブレードに与える悪影響を低減できる。
【0054】
【発明の効果】
本発明に依れば、第1に、1チップデュアル型MOSFETをフェイスダウンでプリント基板に実装できることにある。パッケージやボンディングワイヤを使用しないでプリント基板に実装できるため、市場要求である小型化、薄型化が可能となる。具体的には、パッケージ品と比較して実装面積が30〜40%低減できる。
【0055】
第2に、ゲートバンプ電極をチップの同一辺上に設けることでICとの配線が容易となる。また、各バンプ電極をチップ中心線に対して線対称に設け、各バンプ電極の配置を相対向する2辺において異なる配置とすることによりゲートバンプ電極側が認識できるのでプリント基板実装時にチップ認識が容易となる。
【0056】
第3に、半田バンプの直径は全て同一径であるので、実装時にプリント基板に対して半導体チップが傾かず、水平に実装できる。
【0057】
第4に、パッケージ品と比較してトランスファーモールド等の技術が不要となるのでコストが低減できる。更にパッケージの抵抗が無くなるため、オン抵抗上昇の抑制に寄与できる。
【0058】
第5に、半導体チップ裏面に貼り付けた金属板はチップサイズより小さく設けられるため、ダイシング時にチップおよびブレードに与える悪影響を抑制できる。
【図面の簡単な説明】
【図1】本発明のMOSFETを説明する平面図である。
【図2】本発明のMOSFETを説明する平面図である。
【図3】本発明のMOSFETを説明する断面図である。
【図4】本発明のMOSFETを説明する側面図である。
【図5】従来および本発明の二次電池の充放電用保護回路を説明する回路図である。
【図6】従来のMOSFETを説明する平面図である。
【図7】従来のMOSFETを説明する平面図である。
【図8】従来のMOSFETを説明する断面図である。
【図9】従来のMOSFETを説明する(A)平面図、(B)断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOSFET, and more particularly to a MOSFET that performs battery management that can be incorporated in a secondary battery.
[0002]
[Prior art]
With the widespread use of mobile terminals, small and large capacity lithium ion batteries have been demanded. The protection circuit board that performs battery management of charge / discharge of the lithium ion battery must be smaller and can sufficiently withstand a load short circuit due to the need for weight reduction of the portable terminal. Such a protection circuit device is required to be miniaturized because it is built in a container of a lithium ion battery, and COB (Chip on Board) technology using many chip components has been used to meet the demand for miniaturization. However, on the other hand, since a switching element is connected in series with the lithium ion battery, there is a need to extremely reduce the on-resistance of the switching element, which is an indispensable element for extending the talk time and standby time in the mobile phone.
[0003]
In addition, when the power MOSFET is mounted on a substrate, there are various technical problems such as reducing the mounting area and making the power MOSFET versatile to reduce the production cost.
[0004]
FIG. 5 shows a specific protection circuit for battery management. Two power MOSFETs Q1 and Q2 are connected in series to the lithium ion battery LiB, and the on / off control of the two power MOSFETs Q1 and Q2 is performed while the voltage of the lithium ion battery LiB is detected by the control IC. The lithium ion battery LiB is protected from a load short circuit. The two power MOSFETs Q1 and Q2 have a drain electrode D connected in common, source electrodes S are arranged at both ends, and each gate electrode G is connected to a control IC.
[0005]
In the power MOSFETs Q1 and Q2, a protective bidirectional Zener diode is connected between the gate electrode and the source electrode in order to protect the thin gate oxide film from electrostatic breakdown.
[0006]
During charging, power is connected to both ends, and charging is performed by supplying a charging current to the lithium ion battery LiB in the direction of the arrow. When the lithium ion battery LiB is overcharged, the control IC detects the voltage, the gate voltage of the power MOSFET Q2 changes from H (high level) to L (low level), the power MOSFET Q2 turns off and the circuit is shut off. The lithium ion battery LiB is protected.
[0007]
At the time of discharging, both ends are connected to a load, and the mobile terminal is operated up to a predetermined voltage. However, when the lithium ion battery LiB is overdischarged, the voltage is detected by the control IC, the gate voltage of the power MOSFET Q1 is changed from H to L, the power MOSFET Q1 is turned off, the circuit is shut off, and the lithium ion battery LiB is protected.
[0008]
Further, when the load is short-circuited or when an overcurrent flows, a large current flows through the power MOSFETs Q1 and Q2, and the voltage at both ends of the power MOSFETs Q1 and Q2 rapidly rises. The power MOSFET Q1 is turned off to cut off the circuit to protect the lithium ion battery LiB. However, since a large current flows in a short time until the protection circuit operates, it is required to increase the peak drain current for the power MOSFETs Q1 and Q2.
[0009]
As described above, a demand for a single-chip dual MOSFET having a common drain for battery management is increasing.
[0010]
FIG. 6 shows an example of a conventional one-chip dual MOSFET. The 1-chip dual type MOSFET has two power MOSFETs integrated on one chip and has a source electrode 11 and a gate pad electrode 12 on the front surface, and a metal is deposited on the entire back surface, common to the two power MOSFETs. A drain electrode (not shown) is provided. Each power MOSFET is arranged symmetrically with respect to the center line YY of the chip, and each gate pad electrode 12 is independently arranged at a corner portion of the chip. Bonding wires indicated by circles are thermocompression bonded to the gate pad electrode 12 and the source electrode 11.
[0011]
FIG. 7 shows the detailed structure of one power MOSFET. A protective Zener diode 13 (concentric dotted line) is formed under the gate pad electrode 12, and the electrode is taken out with a bonding wire as indicated by a dotted circle. A large number of MOS transistor cells 7 constituting a power MOSFET are arranged in the actual operation region 16. The source electrode 11 is provided in connection with the source region of each cell 7 on the actual operation region 16. The gate connection electrode 17 is connected to the gate electrode of each cell 7 and is disposed around the actual operation region 16. A bonding wire is thermally deposited on the source electrode 11 as indicated by a dotted circle, and the electrode is taken out.
[0012]
FIG. 8 is a sectional view taken along line BB in FIG.
[0013]
In the actual operation region 16, a large number of trench-type MOS transistor cells 7 constituting a MOSFET are arranged. In an N channel power MOSFET, a
[0014]
The source electrode 11 is provided on the actual operation region 16 through the interlayer insulating film 10 and is in contact with the source region 8 of the MOS transistor. A bonding wire 17 is thermocompression bonded to the source electrode 11 to take out the electrode.
[0015]
The drain electrode 19 is formed as a back electrode by providing a backing metal such as gold on the back surface of the semiconductor chip.
[0016]
The gate pad electrode 12 is disposed outside the actual operation region 16. The gate pad electrode 12 is an electrode formed in the same process as the source electrode 11, and extends and contacts the gate electrode. A protective Zener diode 13 is provided immediately below the gate pad electrode 12, the center of the Zener diode 13 is in contact with the gate pad electrode 12, and the outermost periphery is connected to the source electrode 11 of each cell 7. A bonding wire 18 is thermocompression bonded to the gate pad electrode 12 to take out the electrode.
[0017]
The
[0018]
In the assembly process of a conventional semiconductor device, a semiconductor element diced and separated from a wafer is fixed to a lead frame, the semiconductor element is sealed by a transfer mold using a mold and resin injection, and the lead frame is cut to obtain individual components. A process of separating each semiconductor device is performed.
[0019]
FIG. 9 shows a power MOSFET manufactured by the method described above. FIG. 9A is a top view, and a cross-sectional view taken along the line CC is shown in FIG.
[0020]
The lead frame is a punched frame made of copper, and a power MOSFET
[0021]
The
[0022]
[Problems to be solved by the invention]
As described above, the protection circuit board that performs battery management of charging and discharging of the lithium ion battery must be smaller and can sufficiently withstand a load short circuit due to the need for weight reduction of the portable terminal. Such a protection circuit device is required to be miniaturized because it is built in a container of a lithium ion battery, and COB (Chip on Board) technology using many chip components has been used to meet the demand for miniaturization.
[0023]
However, in such a conventional MOSFET, when mounted on a substrate, as shown in FIG. 9, the package is mounted by transfer molding or the like, or a bare chip is mounted on the substrate, and the source and gate electrodes are connected by bonding wires. . Bare chips and packaged products have a mounting area larger than the chip size, and require a resin layer thickness and a bonding wire height, so there is a limit to miniaturization and thinning which are market demands.
[0024]
[Means for Solving the Problems]
The present invention has been made in view of such problems, and in a one-chip dual MOSFET having two sets of source electrodes and gate pad electrodes on the front surface and a common drain electrode on the back surface, a plurality of sources provided on the source electrode The bump electrode and the gate bump electrode provided on the gate pad electrode are arranged in a line-symmetrical position with respect to the center line of the chip, and a one-chip dual MOSFET can be mounted in a chip size. A reduction in size and thickness is realized.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail with reference to FIGS. The one-chip dual MOSFET of the present invention is composed of two sets of source electrode, gate pad electrode, drain electrode, source bump electrode, and gate bump electrode.
[0026]
FIG. 1 is a plan view of a one-chip dual type power MOSFET of the present invention. This figure is a plan view of the electrode layer.
[0027]
The 1-chip dual type MOSFET has two power MOSFETs integrated on one chip and has a source electrode 11 and a gate pad electrode 12 on the front surface, and a metal is deposited on the entire back surface, common to the two power MOSFETs. A drain electrode (not shown) is provided. Each power MOSFET is arranged symmetrically with respect to the center line XX of the chip, and each gate pad electrode 12 is independently arranged at a corner portion of the chip. In the Lib application, charge / discharge control is normally controlled by signals sent from the IC to the two gate electrodes. For this reason, if the gate pad electrode 12 is arranged on the side where the IC is present, wiring and the like are not wasted. Therefore, the gate pad electrode 12 is arranged along the same side of the semiconductor chip.
[0028]
The
[0029]
One
[0030]
This MOSFET is mounted face-down on a printed circuit board. That is, a one-chip dual MOSFET can be mounted in a chip size. Here, what is important is that, firstly, the
[0031]
Second, the solder bumps of the
[0032]
FIG. 2 shows a detailed structure of one power MOSFET in the lower layer of the electrode layer of FIG. 1 by taking a trench MOSFET as an example.
[0033]
In the actual operation region 16, a large number of cells 7 of a large number of MOS transistors constituting a power MOSFET are arranged therein.
[0034]
The source electrode 11 is provided on the actual operation region 16 by sputtering of Al or the like and is connected to the source region of each cell 7.
[0035]
The gate pad electrode 12 is an electrode formed in the same process as the source electrode 11, and extends and contacts the gate electrode. A protective Zener diode is provided under the gate pad electrode 12.
[0036]
The annular 14 is a high concentration region provided in the drain region outside the actual operation region, and prevents leakage in the reliability test of the semiconductor chip.
[0037]
FIG. 3 is a sectional view taken along line AA in FIG. In an N channel power MOSFET, a
[0038]
The source electrode 11 is provided on the actual operation region 16 through the interlayer insulating film 10 and is in contact with the source region 8 of the MOS transistor. The source electrode 11 is provided with a solder bump, and the electrode is taken out as the
[0039]
The gate pad electrode 12 is disposed outside the actual operation region 16. The gate pad electrode 12 is an electrode formed in the same process as the source electrode 11, and extends and contacts the gate electrode. A protective Zener diode 13 is provided immediately below the gate pad electrode 12, the center of the Zener diode 13 is in contact with the gate pad electrode 12, and the outermost periphery is connected to the source electrode 11 of each cell 7. The gate pad electrode 12 is provided with a solder bump, and the electrode is taken out as the
[0040]
The drain electrode 19 is used as a back electrode by providing a backing electrode such as gold on the back surface of the semiconductor chip.
[0041]
The
[0042]
The
[0043]
The
[0044]
The
[0045]
FIG. 4 shows a side view of the power MOSFET mounted on a substrate.
[0046]
The
[0047]
In addition, since the circuit diagram explaining the protection circuit for charging / discharging of the secondary battery of this invention is the same as that of FIG. 5, description is abbreviate | omitted.
[0048]
A feature of the present invention is that the
[0049]
With this structure, first, it can be mounted face-down on a printed circuit board. Since it is not necessary to use a package or connection by bonding wires, the mounting area on the printed circuit board can be realized in a chip size. Specifically, the mounting area can be greatly reduced to 30 to 40% compared to the package product. . Further, not only the mounting area but also the thickness of the resin layer and the height of the bonding wire can be omitted, so that it is possible to reduce the size and thickness as required in the market.
[0050]
Second, since the gate bump electrodes of the two MOSFETs are arranged along the same side of the chip, wiring with the IC is facilitated. Further, since the gate bump electrode side can be recognized by the difference in the position of each bump electrode arranged along the same side of the chip and the side opposite to the side, this facilitates chip recognition at the time of mounting.
[0051]
Thirdly, since a technique such as transfer molding is not required as compared with package products, the cost can be reduced. Further, since the resistance of the package is eliminated, it is possible to contribute to the suppression of an increase in on-resistance.
[0052]
Fourth, since all the solder bumps have the same diameter, when mounted face down, the semiconductor chip does not tilt with respect to the printed circuit board and can be mounted horizontally.
[0053]
Fifth, by attaching a metal plate such as Cu, Fe, Al or the like smaller than the chip size on the back surface of the semiconductor chip, adverse effects on the semiconductor chip and the blade during dicing can be reduced.
[0054]
【The invention's effect】
According to the present invention, firstly, a one-chip dual MOSFET can be mounted on a printed circuit board face down. Since it can be mounted on a printed circuit board without using a package or bonding wire, it is possible to reduce the size and thickness as required by the market. Specifically, the mounting area can be reduced by 30 to 40% compared to the package product.
[0055]
Second, by providing the gate bump electrode on the same side of the chip, wiring with the IC is facilitated. In addition, each bump electrode is arranged symmetrically with respect to the chip center line, and the arrangement of each bump electrode is different on the two opposite sides so that the gate bump electrode side can be recognized, so chip recognition is easy when mounting on a printed circuit board. It becomes.
[0056]
Thirdly, since all the solder bumps have the same diameter, the semiconductor chip can be mounted horizontally without being inclined with respect to the printed board at the time of mounting.
[0057]
Fourth, a technique such as transfer molding is not required as compared with a package product, so that the cost can be reduced. Furthermore, since the resistance of the package is eliminated, it is possible to contribute to the suppression of an increase in on-resistance.
[0058]
Fifth, since the metal plate attached to the back surface of the semiconductor chip is provided smaller than the chip size, adverse effects on the chip and the blade during dicing can be suppressed.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a MOSFET of the present invention.
FIG. 2 is a plan view illustrating a MOSFET of the present invention.
FIG. 3 is a cross-sectional view illustrating a MOSFET of the present invention.
FIG. 4 is a side view illustrating a MOSFET of the present invention.
FIG. 5 is a circuit diagram for explaining a conventional protection circuit for charging and discharging a secondary battery according to the present invention.
FIG. 6 is a plan view illustrating a conventional MOSFET.
FIG. 7 is a plan view illustrating a conventional MOSFET.
FIG. 8 is a cross-sectional view illustrating a conventional MOSFET.
FIG. 9A is a plan view and FIG. 9B is a sectional view for explaining a conventional MOSFET.
Claims (7)
前記ソース電極上に設けられる複数のソースバンプ電極および前記ゲートパッド電極上に設けられるゲートバンプ電極をチップの中心線に対して線対称の位置に配置することを特徴とする1チップデュアル型絶縁ゲート型半導体装置。In a one-chip dual MOSFET having two sets of source and gate pad electrodes on the front surface and a common drain electrode on the back surface,
A one-chip dual type insulated gate, wherein a plurality of source bump electrodes provided on the source electrode and a gate bump electrode provided on the gate pad electrode are arranged in a line-symmetric position with respect to a center line of the chip. Type semiconductor device.
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JP2006324320A (en) * | 2005-05-17 | 2006-11-30 | Renesas Technology Corp | Semiconductor device |
EP1917683A4 (en) * | 2005-08-17 | 2008-11-05 | Int Rectifier Corp | Power semiconductor device with interconnected gate trenches |
JP5073992B2 (en) | 2006-08-28 | 2012-11-14 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device |
JP6389300B2 (en) * | 2011-10-17 | 2018-09-12 | ローム株式会社 | Semiconductor device |
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CN111684609B (en) * | 2018-02-12 | 2021-10-19 | 新唐科技日本株式会社 | Semiconductor device with a plurality of semiconductor chips |
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