JP4269725B2 - Level control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a level control circuit, and more particularly to a level control circuit for controlling an input signal level.
[0002]
[Prior art]
Conventionally, the lower limit level control operational amplifier compares the output signal level with the lower limit level, controls the lower limit level limiting transistor according to the difference, and limits the input signal to be larger than the lower limit level, and A limiter circuit that compares the output signal level with the upper limit level by the upper limit level control operational amplifier and controls the upper limit level limiting transistor according to the difference to limit the input signal to be smaller than the upper limit level. It has been proposed (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-321562
[Problems to be solved by the invention]
However, the above-described conventional limiter circuit simply limits the input signal level between the upper limit level and the lower limit level.
[0005]
On the other hand, there are audio ICs (integrated circuits) that drive headphones and speakers in response to audio signals. Such an audio IC usually has a built-in volume control function for controlling the output sound and a limiter function for limiting the upper and lower limits of the output sound.
[0006]
At this time, since the conventional limiter simply limits the input signal level between the upper limit level and the lower limit level as described above, it is provided to an audio IC incorporating a volume control function and a limiter function. In this case, it is necessary to separately provide a volume control circuit and a limiter circuit for realizing the volume control function, and there is a problem that the circuit configuration becomes complicated.
[0007]
The present invention aims to provide a has been made in view of the above, perform level control circuits of the level control and amplitude limitation with a simple circuit configuration.
[0008]
[Means for Solving the Problems]
In the level control circuit (22) for controlling the level of an input signal that is DC-biased by bias voltages (V biasR and V biasL ) , the present invention limits the amplitude of the input signal to an upper limit level and a lower limit level. A circuit (32L, 32R), a reference level generation circuit (R 11 to R 15 , C 11 ) for generating a reference level (V 0 ) , one control signal (Vvol) and a reference level generation circuit (R 11 to R) 15 and C 11 ), and a limit level control circuit (31) for controlling the upper limit level and the lower limit level of the input signal in accordance with the difference from the reference level (V 0 ) generated in C 11 ) .
[0009]
The limit level control circuit (31) sets an upper limit level and a lower limit level to be limited by the amplitude limit circuit (32L, 32R) according to the reference level (V 0 ), and the amplitude limit circuit (32L). 32R) detects a difference between the input signal level and the lower limit level, and controls a lower limit level limiting circuit (51L, Q21) to control the input signal level to be higher than the lower limit level according to the difference. And an upper limit level limiting circuit (52L, Q22) for detecting a difference between the input signal level and the upper limit level and controlling the input signal level to be smaller than the upper limit level according to the difference. Features.
[0010]
According to the present invention, since the level control of the input signal and the amplitude limitation can be performed simultaneously, the circuit configuration can be simplified.
[0011]
In addition, the said reference code is a reference to the last, and a claim is not restrict | limited by this.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a system configuration diagram of an embodiment of the present invention.
[0013]
The audio system 1 of this embodiment includes an audio IC 11, a power supply 12, a left audio signal source 13L, a right audio signal source 13R, bias power supplies 14L and 14R, a variable DC voltage circuit 15, a left input resistor LINL, a right input resistor LINR, The headphone (HP) 16, the speaker (SP) 17, the HP / SP changeover switches 18 and 19, and capacitors C 1 to C 5 are included.
[0014]
The audio IC 11 incorporates a DC voltage control electronic volume function, a stereo headphone drive function, and a monaural speaker drive function.
The audio IC 11 includes a power terminal Tvcc, a left audio signal control terminal Tlcont, a right audio signal control terminal Trcont, a volume terminal Tvol, a left audio signal input terminal Tlin, a right audio signal input terminal Trin, a left audio signal output terminal Tlout, and a right. The audio signal output terminal Trout, the speaker output terminal Tspout, the HP / SP switching terminal Tsw, and the GND terminal Tgnd are included.
[0015]
The drive voltage Vcc is applied from the power supply 12 to the power supply terminal Tvcc of the audio IC 11. The drive voltage Vcc applied to the power supply terminal Tvcc is applied to the power supply circuit 21. The power supply circuit 21 generates a power supply voltage Vcc1 used in the volume control circuit 22 from the drive voltage Vcc.
[0016]
The left audio signal control terminal Tlcont is supplied with the left audio signal from the left audio signal source 13L through the input resistor LINL. The left audio signal is DC-biased by the bias voltage VbiasL by the bias power supply 14L. The left audio signal supplied to the left audio signal control terminal Tlcont is supplied to the volume control circuit 22 inside the audio IC 11.
[0017]
The right audio signal control terminal Trcont is supplied with the right audio signal from the right audio signal source 13R through the input resistor RINR. The right audio signal is DC-biased by the bias voltage VbiasR by the bias power supply 14R. The right audio signal supplied to the right audio signal control terminal Trcont is supplied to the volume control circuit 22 inside the audio IC 11.
[0018]
The volume control voltage Vvol is applied from the variable DC voltage circuit 15 to the volume terminal Tvol. The volume control voltage Vvol applied to the volume terminal Tvol is supplied to the volume control circuit 22 inside the audio IC 11.
[0019]
Here, the volume control circuit 22 will be described.
[0020]
FIG. 2 shows a circuit configuration diagram of the volume control circuit 22.
[0021]
The volume control circuit 22 includes an upper / lower limit level setting circuit 31, a left audio signal limiting circuit 32L, and a right audio signal limiting circuit 32R.
[0022]
The upper and lower limit level setting circuit 31 includes resistors R11 to R15, a capacitor C11, and differential amplifiers 41 and 42, and is a circuit for setting an upper limit level and a lower limit level.
[0023]
A power supply voltage Vcc1 generated by the power supply circuit 21 is applied to the resistors R11 and R12, and the power supply voltage Vcc1 is divided to generate a reference voltage V0. Note that a capacitor C11 is connected in parallel to the resistor R12 to absorb fluctuations in the power supply voltage Vcc1. The reference voltage V0 generated by dividing by the resistors R11 and R12 is applied to the inverting input terminals of the differential amplifiers 41 and 42.
[0024]
On the other hand, the upper limit level voltage is applied to the non-inverting input terminal of the differential amplifier 41. The differential amplifier 41 outputs a voltage corresponding to the difference between the reference voltage V0 and the upper limit level voltage. The output of the differential amplifier 41 is supplied to the gate of the transistor Q11.
[0025]
The transistor Q11 is composed of a P-channel field effect transistor, and the current flowing through the source and drain is controlled according to the output of the differential amplifier 41. The output current of the transistor Q11 is supplied to resistors R13 and R14 connected in series.
[0026]
A lower limit level voltage is applied to the non-inverting input terminal of the differential amplifier 42. The differential amplifier 42 outputs a voltage corresponding to the difference between the reference voltage V0 and the lower limit level voltage. The output of the differential amplifier 42 is supplied to the gate of the transistor Q12.
[0027]
The transistor Q12 is composed of an N-channel field effect transistor, and the current flowing through the sword-drain is controlled according to the output of the differential amplifier 42. The transistor Q12 controls the current drawn from the resistors R13 and R14 connected in series.
[0028]
Further, currents corresponding to the volume control signal are supplied from the volume control terminal Tvol to the resistors R13 and R14 connected in series via the resistor R15. The voltage across the resistors R13 and R14 is controlled by the volume control signal supplied to the volume control terminal Tvol, and increases as the flowing current increases, and decreases as the flowing current decreases.
[0029]
Of the voltages generated in the resistors R13 and R14 connected in series, the high potential side is supplied as an upper limit level voltage to the left audio signal limiting circuit 32L and the left audio signal limiting circuit 32R, and the low potential side is supplied as a lower limit level voltage to the right audio. The signal is supplied to the signal limiting circuit 32L and the right audio signal limiting circuit 32R.
[0030]
The left audio signal limiting circuit 32L includes differential amplifiers 51L and 52L and transistors Q21 and Q22. The lower limit level voltage is applied from the upper / lower limit level setting circuit 31 to the inverting input terminal of the differential amplifier 51L, and the non-inverting input terminal of the differential amplifier 51L is connected to the left audio signal control terminal Tlcont.
[0031]
The differential amplifier 51L outputs a voltage corresponding to the difference between the left audio signal control terminal Tlcont supplied to the left audio signal control terminal Tlcont and the lower limit level voltage from the upper and lower limit level setting circuit 31. The output voltage of the differential amplifier 51L is applied to the gate of the transistor Q21.
[0032]
The transistor Q21 is composed of a P-channel field effect transistor, and is turned on when the output of the differential amplifier 51L is negative, and supplies a current corresponding to the output voltage of the differential amplifier 51L to the left audio signal control terminal Tlcont.
[0033]
Thus, when the left audio signal level supplied to the left audio signal control terminal Tlcont becomes smaller than the lower limit level voltage, a current is supplied to the left audio signal control terminal Tlcont by the transistor Q21, and the left audio signal level becomes lower than the lower limit level voltage. It is controlled not to become.
[0034]
The upper limit level voltage is applied from the upper / lower limit level setting circuit 31 to the inverting input terminal of the differential amplifier 52L, and the non-inverting input terminal of the differential amplifier 52L is connected to the left audio signal control terminal Tlcont.
[0035]
The differential amplifier 52L outputs a voltage corresponding to the difference between the left audio signal control terminal Tlcont supplied to the left audio signal control terminal Tlcont and the upper limit level voltage from the upper and lower limit level setting circuit 31. The output voltage of the differential amplifier 52L is applied to the gate of the transistor Q22.
[0036]
The transistor Q22 is composed of an N-channel field effect transistor and is turned on when the output of the differential amplifier 52L is positive, and draws a current corresponding to the output voltage of the differential amplifier 52L from the left audio signal control terminal Tlcont.
[0037]
Thus, when the level of the left audio signal supplied to the left audio signal control terminal Tlcont becomes larger than the upper limit level voltage, current is drawn from the left audio signal control terminal Tlcont by the transistor Q22, and the left audio signal level becomes equal to or higher than the upper limit level voltage. It is controlled not to become.
[0038]
3 and 4 show operation waveform diagrams of the volume control circuit 22.
[0039]
FIG. 3 shows the characteristics of the amplitude of the audio signal according to the volume control voltage Vvol. FIG. 4 shows the level change according to the time of the audio signal.
[0040]
When the volume control voltage Vvol supplied to the upper / lower limit level setting circuit 31 is increased and exceeds the threshold voltage Vth, the upper limits supplied to the left audio signal limiting circuit 32L and the right audio signal limiting circuit 32R according to the volume control voltage Vvol. The voltage difference between the level voltage and the lower limit level voltage can be changed. By controlling the volume control voltage Vvol at a threshold voltage Vth or higher, the amplitude of the audio signal can be varied.
[0041]
Further, according to the present embodiment, the audio signal is limited to the predetermined amplitude ΔV (V1−V2) as shown in FIG. 4 by the upper limit level voltage V1 and the lower limit level voltage V2. This eliminates the need to limit the audio signal level. Therefore, the limiter can be deleted.
[0042]
The right audio signal limiting circuit 32R operates with the left audio signal limiting circuit 32L on the right audio signal, and the configuration and operation thereof are the same as those of the left audio signal limiting circuit 32L. Description is omitted.
[0043]
The volume control circuit 22 of this embodiment can execute volume control and level restriction by the same circuit as described above. As a result, the circuit configuration of the audio IC 11 can be simplified.
[0044]
The audio signal controlled by the left audio signal control terminal Tlcont is connected to the terminals Tlcont, Tlin1, Tlin2 of the audio IC 11 and resistors R1L, R2L, capacitors C11L, C12L, C13L externally connected to the ground, and the audio IC11. Is supplied to the mute circuit 24L through an active filter composed of a 1 × amplifier 23L incorporated in the circuit.
[0045]
The mute circuit 24L operates in response to an instruction from the volume control circuit 22 when the volume in the volume control circuit 22 is at a zero level, and stops outputting the left audio signal.
[0046]
The left audio signal that has passed through the mute circuit 24L is supplied to a non-inverting amplifier circuit composed of an operational amplifier circuit 25L and resistors R11L and R12L.
[0047]
The non-inverting amplifier circuit composed of the operational amplifier circuit 25L and the resistors R11L and R12L operates in response to the HP / SP switching control signal from the control circuit 28, and the left audio signal from the mute circuit 24L when headphone driving is selected. Is inverted and supplied to the left audio signal output terminal Tlout. The left actuator 16L of the headphone 16 is connected to the left audio signal output terminal Tlout. The left actuator 16L of the headphone 16 is driven according to the left audio signal from the left audio signal output terminal Tlout, and outputs a sound according to the left audio signal.
[0048]
The audio signal controlled by the right audio signal control terminal Trcont is connected to the terminals Trcont, Trin1, Trin2 of the audio IC 11 and resistors R1R, R2R, capacitors C11R, C12R, C13R externally connected to the ground, and the audio IC11. Is supplied to a mute circuit 24R built in the audio IC 11 through an active filter composed of a 1 × amplifier 23R built in the audio IC. Similar to the mute circuit 24L, the mute circuit 24R stops the output of the right audio signal in response to an instruction from the volume control circuit 22 when the volume in the volume control circuit 22 is at a zero level.
[0049]
The audio signal that has passed through the mute circuit 24R is supplied to a non-inverting amplifier circuit composed of an operational amplifier circuit 25R and resistors R11R and R12R. A non-inverting amplifier circuit composed of an operational amplifier circuit 25R and resistors R11R and R12R operates in response to an HP / SP switching control signal from the control circuit 28, and a mute circuit when a headphone (HP) operation is selected. The audio signal from 24R is non-inverted and amplified and supplied to the right audio signal output terminal Trout. The right actuator 16R of the headphone 16 is connected to the right audio signal output terminal Trout. The right actuator 16R of the headphone 16 is driven according to the right audio signal from the right audio signal output terminal Trout, and outputs a sound according to the right audio signal.
[0050]
The left audio signal output from the mute circuit 24L and the right audio signal output from the mute circuit 24R are supplied to the adder 26. The adder 26 adds the left audio signal from the mute circuit 24L and the right audio signal from the mute circuit 24R.
[0051]
The audio signal added by the adder 26 is supplied to a non-inverting amplifier circuit composed of an operational amplifier circuit 27 and resistors R13 and R14. The non-inverting amplifier circuit composed of the operational amplifier circuit 27 and the resistors R13 and R14 operates according to the HP / SP switching control signal from the control circuit 28, and is added when the speaker (SP) operation is selected. 26 amplifies the audio signal from 26 and supplies it to the speaker output terminal Tspout. A speaker 17 is connected to the speaker output terminal Tspout. The speaker 17 is driven according to an audio signal supplied from a non-inverting amplifier circuit composed of an operational amplifier circuit 27 and resistors R13 and R14 via a speaker output terminal Tspout, and outputs a sound corresponding to the audio signal.
[0052]
The control circuit 28 generates an HP / SP switching signal according to the state of the HP / SP switching terminal Tsw. The HP / SP switching terminal Tsw is grounded via the HP / SP switching switch 18. When the HP / SP switch 18 is on, the HP / SP switch terminal Tsw is set to the ground potential, and when the HP / SP switch 18 is off, the HP / SP switch 18 is opened. For example, when the HP / SP switching terminal Tsw is at the ground potential, the control circuit 28 sets the HP / SP switching control signal supplied to the operational amplifier circuits 25L and 25R to a low level and supplies the operational amplifier circuit 27 with the HP / SP switching control. Set the signal to high level. As a result, the operation of the operational amplifier circuits 25L and 25R is stopped, the operational amplifier circuit 27 enters the operating state, and the speaker (SP) is driven.
[0053]
When the HP / SP switching terminal Tsw is open, the HP / SP switching control signal supplied to the operational amplifier circuits 25L and 25R is set to high level, and the HP / SP switching control signal supplied to the operational amplifier circuit 27 is set to low level. To do. As a result, the operational amplifier circuits 25L and 25R are activated, the operational amplifier circuit 27 is stopped, and the headphone (HP) is driven.
[0054]
In this embodiment, the level control circuit of the present invention is applied as a volume control circuit for an audio IC. However, the present invention is not limited to this, and is generally a level control circuit for limiting the level and amplitude of an input signal. Needless to say, it can be applied.
[0055]
In this embodiment, the circuit is constituted by a CMOS transistor. However, the present invention is not limited to this, and can be constituted by a bipolar transistor.
[0056]
【The invention's effect】
As described above, according to the present invention, since the level control of the input signal and the amplitude limitation can be performed simultaneously, the circuit configuration can be simplified.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram of an embodiment of the present invention.
FIG. 2 is a circuit configuration diagram of a volume control circuit 22;
FIG. 3 is an operation waveform diagram of the volume control circuit 22;
4 is an operation waveform diagram of the volume control circuit 22. FIG.
[Explanation of symbols]
1 Audio System 11 Audio IC
12 Driving power supply, 13L Left audio signal source, 13R Right audio signal source 14L, 14R Bias power supply, 15 Variable DC voltage circuit 16 Headphone, 16L Left actuator, 16R Right actuator 17 Speaker, 18, 19 HP / SP changeover switch 21 Power supply circuit , 22 Volume control circuit 23L, 23R Buffer amplifier, 24L, 24R Mute circuit 25L, 25R, 27 Operation amplifier circuit, 26 Adder, 28 Control circuit 31 Upper / lower limit level setting circuit, 32L Left audio signal limit circuit 32R Right audio signal limit Circuits 41, 42, 51L, 51R, 52L, 52R Differential amplifiers Q11, Q12, Q21, Q22, Q31, Q32 Transistors

Claims (4)

In a level control circuit that controls the level of an input signal that is DC biased by a bias voltage ,
An amplitude limiting circuit for limiting the amplitude of the input signal to an upper limit level and a lower limit level ;
A reference level generation circuit for generating a reference level;
A level control circuit comprising: a limit level control circuit that controls an upper limit level and a lower limit level of the input signal according to a difference between one control signal and the reference level generated by the reference level generation circuit . The limit level control circuit sets an upper limit level and a lower limit level to be limited by the amplitude limit circuit according to the reference level ,
The amplitude limiting circuit detects a difference between the input signal level and the lower limit level, and controls the input signal level to be larger than the lower limit level according to the difference;
2. An upper limit level limiting circuit that detects a difference between the input signal level and the upper limit level and controls the input signal level to be smaller than the upper limit level according to the difference. The level control circuit described. The limit level control circuit includes a first resistor to which the one control signal is supplied at one end;
  A second resistor having one end connected to the other end of the first resistor;
  A third resistor having one end connected to the other end of the second resistor;
  A connection point between the first resistor and the second resistor is connected to a non-inverting input terminal, a reference voltage generated by the reference level generation circuit is applied to an inverting input terminal, and the first resistor and the A first differential amplifier that outputs a voltage corresponding to a difference between a voltage at a connection point with a second resistor and the reference voltage;
  An output of the first differential amplifier is supplied to a gate, and a current corresponding to the output of the first differential amplifier is supplied to a connection point between the first resistor and the second resistor. A transistor,
  A connection point between the second resistor and the third resistor is connected to a non-inverting input terminal, the reference voltage generated by the reference voltage generating circuit is applied to the inverting input terminal, and the second resistor and A second differential amplifier that outputs a voltage corresponding to a difference between a voltage at a connection point with the third resistor and the reference voltage;
  An output of the second differential amplifier is supplied to a gate; and a second transistor that draws a current corresponding to the output of the second differential amplifier from the other end of the third resistor;
  The upper limit level voltage is output from a connection point between the first resistor, the second resistor, and the first transistor, and the lower limit from a connection point between the third resistor and the second transistor. 3. The level control circuit according to claim 2, which outputs a level voltage. The amplitude limiting circuit includes a third differential amplifier in which the lower limit level voltage is supplied to an inverting input terminal;
  A third transistor in which an output of the third differential amplifier is supplied to a gate, and an output current is controlled by the output of the third differential amplifier;
  A fourth differential amplifier in which the upper limit level voltage is supplied to an inverting input terminal;
  An output of the fourth differential amplifier is supplied to the gate, and a fourth transistor draws an output current of the third transistor by the output of the fourth differential amplifier,
  A connection point between the third transistor and the fourth transistor is connected to a non-inverting input terminal of the third and fourth differential amplifiers, and a connection point between the third transistor and the fourth transistor. 4. The level control circuit according to claim 3, wherein the input signal level is controlled within the lower limit level or the upper limit level by a current supplied or drawn.

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