JP4262455B2 - Semiconductor device manufacturing method and manufacturing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a manufacturing technique of an insulated gate field effect transistor (IGFET) using plasma.
[0002]
[Prior art]
As the degree of integration of LSI (Large Scale Integrated Circuit) increases, pattern miniaturization is progressing. In order to faithfully transfer a miniaturized mask pattern to a conductive layer or an insulating layer, anisotropic dry etching using plasma such as reactive ion etching (RIE) or electron cyclotron resonance (ECR) plasma etching is frequently used. .
[0003]
On the other hand, with the miniaturization of semiconductor elements, the thickness of the gate insulating film of the insulated gate field effect transistor has been reduced, and those having a thickness of 10 nm or less are being put into practical use. Thus, the thin gate insulating film is easily damaged even by a small electrical stress.
[0004]
For example, in the plasma process, charges such as ions and electrons are incident on the substrate. When a difference occurs between incident positive and negative charges, the charge is charged up in the conductive layer on the gate insulating film that is electrically separated from the substrate. When a potential difference is generated between the conductive layer and the underlying substrate, a tunnel current can flow through the gate insulating film. Due to the tunnel current, the dielectric characteristics of the gate insulating film change and may cause dielectric breakdown.
[0005]
As described above, a plasma process in which charge-up can occur in a conductive layer on a gate insulating film or a conductive layer connected to a gate electrode (hereinafter referred to as a gate wiring) can damage the gate insulating film. Such processes include patterning the gate wiring layer, opening a contact hole reaching the gate wiring layer, cleaning by sputter etching in the contact hole reaching the gate wiring layer, and plasma on the surface where the gate wiring layer is partially exposed. CVD or the like.
[0006]
When the gate insulating film is damaged, not only the yield of the semiconductor device is reduced due to the breakdown of the gate insulating film or the change in the dielectric characteristics of the gate insulating film, but also the reliability of the gate insulating film, and thus the reliability of the semiconductor device is improved. There are cases where it is damaged. Therefore, it is desirable to sufficiently prevent damage to the gate insulating film caused by the plasma process.
[0007]
If the plasma on the semiconductor substrate is non-uniform, there is a difference between the ion current and the electron current flowing into the semiconductor substrate, and a tunnel current based on this difference may flow through the gate insulating film. In a semiconductor device, the area of a gate wiring (hereinafter referred to as an antenna ratio) with respect to the area of a gate insulating film reaches about 10,000. When such a high antenna ratio conductive film is plasma processed, a large amount of tunnel current may flow through the gate insulating film due to slight plasma non-uniformity.
[0008]
Therefore, attempts have been made to make the plasma used for plasma processing as uniform as possible. More specifically, uniform plasma potential and uniform substrate bias voltage have been proposed. For example, a configuration is proposed in which a magnetic flux crosses over a semiconductor substrate, and the magnetic flux is parallel to the surface everywhere on the substrate.
[0009]
Hereinafter, a conductive layer formed on a thick insulating film and connected to an electrode on a thin insulating film such as a gate insulating film and having a larger area and electrically separated is called an antenna, and is thin (gate). The ratio of the bottom area of the conductive layer on the thick insulating film to the area of the electrode on the insulating film is called the antenna ratio.
[0010]
The uniformity of plasma has been measured by the breakdown rate of the gate insulating film using a gate wiring having a high antenna ratio. For example, it has been determined that the plasma is uniform if the gate wiring having an antenna ratio of 1,000,000 and exposed on the surface (surface exposed type) is plasma treated and the gate insulating film is not destroyed.
[0011]
However, it has been found that even when plasma that is proved to be sufficiently uniform by such measurement is used, the gate insulating film may be damaged depending on the processing pattern. For example, in the patterning of the gate wiring, a photoresist mask pattern is disposed on the gate wiring layer. The ratio of the resist thickness to the opening width in the opening of the photoresist (hereinafter referred to as the aspect ratio) has become larger than 1. When plasma processing is performed on a conductive layer under an insulating pattern having such a high aspect ratio, the gate insulating film can be damaged even if uniform plasma is used. Such an antenna structure having a high aspect ratio insulating film pattern on it is hereinafter referred to as a structured antenna.
[0012]
For example, if an antenna with a structure with an antenna ratio of 10,000 is exposed to ECR plasma that has been proven to be uniform depending on the surface-exposed antenna structure with an antenna ratio of 1,000,000, the gate insulating film may be damaged. .
[0013]
Therefore, even when plasma having uniform properties is used for a flat conductive film having a continuous surface, the gate insulating film is damaged in the manufacturing process of the semiconductor device having a fine pattern.
[0014]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor device manufacturing method capable of preventing damage to a gate insulating film even in processing of a fine pattern.
[0015]
Another object of the present invention is to provide a semiconductor device manufacturing apparatus capable of manufacturing a semiconductor device having a fine pattern while preventing damage to a gate insulating film.
[0016]
[Means for Solving the Problems]
  According to one aspect of the present invention, in plasma processing in the manufacture of a semiconductor device including a transistor having an insulated gate, the electron temperature Te (eV), which is a representative value of the electron energy distribution in the plasma, is the dielectric breakdown voltage B of the insulated gate. Rf to be smaller than (V)Biasedfrequency,Microwave for plasma generationControlling at least one of electric power, magnetic field, pressure, and gas type so that electrons can be put into a conductor pattern existing between insulator patterns having openings having an aspect ratio larger than 1. A method for manufacturing a semiconductor device is provided.
[0017]
  According to another aspect of the invention,( a )A semiconductor layer formed thereon, a withstand voltage of B (V), a gate insulating film having a thickness of 10 nm or less, a conductor layer of an antenna structure formed thereon, and an aspect layer formed thereon; In a plasma processing apparatus, a semiconductor wafer having an insulator pattern having an opening with a ratio greater than 1 is provided.Placed on the susceptorAnd the process of(B)On the entire surface of the semiconductor wafer, the electron temperature Te (eV) isSmaller than withstand voltage B (V)And a method of manufacturing a semiconductor device including a step of processing the semiconductor wafer in plasma.
[0018]
  According to another aspect of the invention,( a )A semiconductor layer, a gate insulating film formed thereon, having a withstand voltage of B (V) and a thickness of 10 nm or less, a conductor layer having an antenna structure formed thereon having an antenna ratio of 500 or more, A semiconductor wafer having an insulator pattern formed thereon and having an opening having an aspect ratio greater than 1 is placed in a plasma processing apparatus.Placed on the susceptorAnd the process of(B)On the entire surface of the semiconductor wafer, the electron temperature Te (eV) isSmaller than withstand voltage B (V)And a method of manufacturing a semiconductor device including a step of etching an opening in the insulating layer in plasma.
[0019]
  According to another aspect of the invention,( a )A semiconductor layer, a gate insulating film formed thereon, having a withstand voltage of B (V) and a thickness of 10 nm or less, a conductor layer having an antenna structure formed thereon having an antenna ratio of 500 or more, A semiconductor wafer having an insulator pattern formed thereon and having an opening having an aspect ratio greater than 1 is placed in a plasma processing apparatus.Placed on the susceptorAnd the process of(B)On the entire surface of the semiconductor wafer, the electron temperature Te (eV) isSmaller than withstand voltage B (V)Processing the semiconductor wafer in plasma;(C) after or before step (b),And a step of processing the semiconductor wafer in a plasma having an electron temperature Teh higher than the electron temperature Te.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The inventor and his colleagues have reported the appearance of structured antennas with high antenna ratios during gate wiring layer etching due to the microloading effect (US patent application 08 / 275,426, column of preferred embodiments). . When a resist pattern is formed on the surface of the gate wiring layer after deposition and etching is performed, the gate wiring layer is initially electrically connected to the substrate, and no antenna structure has appeared. However, due to the microloading effect, even if the etching is finished in the wide opening area, the etching is not finished in the narrow opening area. At this stage, the gate wiring layer has a shape divided by a wide opening width region. At this transition stage, a structured antenna having a high antenna ratio appears.
[0021]
When a bias rf is applied to the substrate to generate an electric field that draws ions in the plasma into the substrate, the ions in the plasma are accelerated toward the substrate. However, the electrons in the plasma are decelerated as they go to the substrate. The force generated by the electric field is in a direction perpendicular to the surface of the substrate and is not decelerated in a direction parallel to the substrate surface.
[0022]
Therefore, it is considered that most of electrons having various motion directions reflecting random motion in the plasma are incident on the substrate obliquely. For this reason, ions hardly collide with the upper side wall of the insulating pattern of the antenna with the structure of the insulating pattern, but a large amount of electrons collide. As a result, negative charges are accumulated on the upper side wall of the insulating pattern.
[0023]
When the electric field due to this negative charge is increased, electrons are repelled and are unlikely to enter the pattern. Therefore, in comparison with the positive charge inflow due to ions, the negative charge inflow due to electrons is insufficient, and as a result, current due to excess positive charge is accumulated in the gate wiring layer and passes through the gate insulating film as a tunnel current, causing damage. It is thought to occur.
[0024]
1A, 1B, and 1C show experiments conducted by the present inventors. FIG. 1A is a plan view showing a state of gate insulating film destruction in each chip on a plasma-treated wafer. FIG. 1B is a schematic plan view showing the insertion direction of the probe used for measuring the electron temperature of plasma. FIG. 1C is a graph showing the electron temperature of plasma obtained by probe measurement as a function of position.
[0025]
2A and 2B are a cross-sectional view and a plan view showing the structure of the sample used in the experiment. On the surface of the silicon substrate 13, a thick field oxide film 14a and a gate oxide film 14b having a thickness of 8 nm formed in a region surrounded by the field oxide film are formed.
[0026]
On these field oxide film and gate insulating film, a gate wiring 15 composed of a stacked layer of a polycrystalline silicon film 15a and an aluminum layer 15b is formed to constitute a MOS capacitor C. A dense wiring pattern 16 of 1.6 μm thick photoresist is formed on the gate wiring 15.
[0027]
As shown in FIG. 2B, the photoresist pattern 16 includes a plurality of wiring patterns having a width w = 0.75 μm arranged in parallel at an interval d = 0.8 μm. The aspect ratio of the opening is 2. These wires are continuously connected to the MOS capacitor C shown in the lower part of the figure.
[0028]
FIG. 3A shows a configuration of a divergent magnetic field ECR plasma etching apparatus obtained by etching such a sample. A gas introduction port 2 and an exhaust port 3 are connected to the reaction chamber 1 that can be evacuated. The gas inlet 2 is connected to a predetermined etching gas source. The exhaust port 3 is connected to an exhaust device. An opening is provided in the upper part of the reaction chamber 1 and is connected to the plasma generation chamber 4. The plasma generation chamber 4 and the reaction chamber 1 constitute an airtight container.
[0029]
Above the reaction chamber 4, a microwave transmission window 6 made of quartz or the like is provided in an airtight manner and is connected to the microwave waveguide 5. The microwave waveguide 5 introduces microwaves from the microwave generation source to the plasma generation chamber 4.
[0030]
A main coil 7 is disposed around the plasma generation chamber 4, and a divergent magnetic field can be generated in the microwave generation chamber 4. This divergent magnetic field forms an ECR condition.
[0031]
A susceptor 8 for placing the substrate 9 is disposed below the reaction chamber 1, and the susceptor 8 is connected to an rf bias source 12. The rf bias source 12 supplies an rf voltage of 13.56 MHz to the susceptor 8. An outer external coil 10 and an inner internal coil 11 are disposed concentrically below the susceptor 8.
[0032]
An etching gas atmosphere is introduced into the reaction chamber 1 and the plasma generation chamber 4 by introducing an etching gas from the gas inlet 2 and exhausting from the exhaust port 3. ECR plasma is generated in the plasma generation chamber 4 by introducing a microwave from the microwave waveguide 5 into the plasma generation chamber 4 while generating a magnetic field by the main coil 7. This plasma drifts in the reaction chamber 1 by the diverging magnetic field and reaches the substrate 9 on the susceptor 8.
[0033]
By applying rf power of 13.56 MHz from the rf bias source 12 to the susceptor 8, the potential of the substrate 9 is controlled, and a bias electric field is generated so as to accelerate ions in the plasma toward the substrate 9. Under such conditions, the sample on the substrate 9 was etched by plasma.
[0034]
Etching conditions are: main coil current 21A, external coil current 8A, internal coil current 8A, etching gas Cl₂+ BCl_ThreeThe pressure was 0.6 Pa, the microwave power was 800 W, and the rf bias power was 180 W.
[0035]
FIG. 1A shows the result of etching a sample formed on each chip 22 on the wafer 9 by etching under this condition. Each chip 22 on the wafer 9 is provided with a MOS capacitor having a gate oxide film thickness of 8 nm to which the antenna shown in FIGS. 2A and 2B is connected. After etching this antenna, the breakdown voltage of the MOS capacitor was measured.
[0036]
White squares represent chips with normal pressure resistance, and hatched squares represent samples with defective pressure resistance, i.e., a breakage during etching. Note that the area indicated by a single right-sloped hatch has an antenna ratio of 10⁶Indicates the area where the sample was destroyed, and the cross-hatched area represents an antenna ratio of 10^FiveShows the area where the sample was destroyed.
[0037]
Antenna ratio 10^FourWas also formed at the same time, but the antenna ratio was 10^Five The sample was destroyed in almost the same area as the destroyed area. FIG. 1A shows that the sample is not destroyed on the entire surface of the wafer, but the sample is destroyed in a certain region. From another viewpoint, the gate insulating film is not destroyed in a certain region on the wafer. In other words, it is considered that in the region indicated by the white square, the plasma can prevent damage to the gate insulating film.
[0038]
Therefore, plasma properties were measured using a Langmuir probe with a compensation electrode. FIG. 1B shows the insertion direction of the probe on the wafer 9. The height of the probe was about 4 cm from the wafer surface.
[0039]
FIG. 3B schematically shows the configuration of the Langmuir probe. A platinum wire having a radius of 0.5 mm and a length of 5 mm was used as the probe 31. Compensation electrodes 32 and 33 made of aluminum are connected to the probe 31 via capacitors 34 and 35. These compensation electrodes 32 and 33 are electrodes for compensating the fluctuating plasma potential.
[0040]
The probe 31 is connected to an ammeter 38 and a variable voltage source 37 through a filter 36 that cuts off the used rf frequency. The other pole of the variable voltage source 37 and the outer wall of the reaction chamber 1 are grounded.
[0041]
The position of the probe 31 was moved on the wafer 9 as shown in FIG. 1B, and the current I flowing by sweeping the voltage V of the variable voltage source 37 at each point was measured with an ammeter 38. From the obtained V-I characteristics, ΔV / ΔlnI near the floating potential where the current value becomes “0” was calculated, and the electron temperature was determined in units of eV by a well-known method.
[0042]
FIG. 1C shows the relationship between the obtained electron temperature (eV) and the radial position on the wafer 9. Corresponding to the region where the sample was destroyed, the electron temperature distribution shows a clear change. That is, in the region where the sample is broken, the electron temperature is as high as about 10 eV or more, and in the region where no breakage occurs, the electron temperature is as low as about 7 eV. From this result, it can be seen that when the electron temperature in the plasma is high, the gate insulating film having the structured antenna is easily broken.
[0043]
Note that the gate insulating film in the sample is a silicon oxide film having a thickness of 8 nm, and the withstand voltage of the silicon oxide film is about 8V. Therefore, the sample is not damaged in the electron temperature region lower than the withstand voltage of the gate insulating film, typically about 1 eV or more.
[0044]
Conversely, the gate insulating film is damaged in an electron temperature region that is higher than the breakdown voltage of the gate insulating film, typically about 2 eV or more. Therefore, in order to prevent damage to the gate insulating film, it is desirable to make the electron temperature of the plasma lower than the breakdown voltage of the gate insulating film.
[0045]
Note that the gate insulating film is easily damaged when the thickness of the gate insulating film is 10 nm or less, the antenna ratio is 500 or more, and the aspect ratio is 1 or more. In particular, damage is likely to occur when the wafer diameter is 8 inches or more.
[0046]
As described above, it has been found that even if a plasma with uniform characteristics on a flat surface is used, damage that can occur in processing of a fine pattern can be prevented by controlling the plasma electron temperature on the entire wafer surface low. This mechanism can be considered as follows.
[0047]
First, the following model can be considered as a mechanism for causing damage to the structured antenna even when uniform plasma is used. As shown in FIG. 4A, when bias rf power is supplied to the substrate, the substrate is biased to a negative potential relative to the plasma. Positive ions in the plasma are accelerated toward the substrate by an electric field formed between the substrate and the plasma, and enter the substrate almost perpendicularly. The electric field between the plasma and the substrate periodically changes depending on the bias rf power applied to the substrate, but its direction (sign) does not change. Therefore, it can be considered that positive ions are incident on the substrate throughout the entire period.
[0048]
As shown in FIG. 4B, this electric field exerts a deceleration action on electrons. Therefore, the electrons are decelerated by the electric field, reflecting the random motion in the plasma, and most of them are considered to be incident on the substrate obliquely. When electrons are incident on the substrate at an angle, the electrons are incident on the sidewall of the insulating pattern on the substrate. Electrons incident on the non-conductive region charge up that region.
[0049]
That is, ions hardly collide with the upper side wall of the insulator pattern of the structured antenna, and only electrons collide. As a result, negative charges are accumulated on the sidewall. The accumulated negative charge further forms an electric field that repels electrons. Depending on the strength of the electric field, electrons cannot enter the pattern. It can be considered that the accumulation of negative charges on the upper side wall of the insulator pattern is governed by the lateral velocity of electrons in the plasma.
[0050]
The lateral velocity of the electrons depends on the electron temperature. If the proportion of electrons having a high lateral velocity is high, the negative charge accumulated on the side wall of the insulator pattern increases, and the electron current cannot be balanced against the positive charge inflow of ions incident throughout the entire period. As a result, it is considered that excessive positive current passes through the gate insulating film and is damaged.
[0051]
When the electron temperature is lowered, the average kinetic energy of the electrons is lowered and the number of high energy electrons is also reduced. The movement of electrons is random. As shown in FIG. 4 (C), the velocity component v is a velocity component perpendicular to the substrate._yAnd velocity component v parallel to substrate surface_xWhen external force does not work when considering_xDistribution and v_yThe distribution of is equal. When an electric field perpendicular to the substrate is generated, the vertical component v_yIs accelerated / decelerated by the electric field between the plasma and the substrate, but the horizontal component v_xIs hardly affected by the electric field. When the electron temperature is lowered, the lateral velocity component of the electron v_xIt is considered that the negative charge accumulated on the upper side wall of the insulator pattern is reduced. Electron vertical velocity component v_yIf the electron temperature is considered to be maintained at a substantially constant value by the interaction with the electric field, the lower the electron temperature, the smaller the charge-up amount on the sidewall and the higher the electron current flowing into the substrate. it can. By such a mechanism, it is considered that excess of positive charges incident on the substrate when the electron temperature is lowered can be suppressed.
[0052]
Note that the incidence of electrons on the substrate is not uniform over the entire period. When the bias electric field between the plasma and the substrate is strong, electrons are repelled by the electric field and cannot approach the substrate. The bias electric field between the plasma and the substrate becomes weak, and it is considered that the electrons are incident on the substrate only during a period in which the electrons approach the substrate. When the substrate bias is rf bias, the electric field formed between the plasma and the substrate varies according to the frequency of the rf bias.
[0053]
In the ECR plasma etching apparatus shown in FIG. 2A, the frequency of the rf bias source 12 was changed from 13.56 MHz to 400 kHz. As a result, the gate insulating film was not damaged on the entire wafer surface. This phenomenon can be considered as follows.
[0054]
By reducing the frequency, the period during which the electric field formed between the plasma and the substrate is strong becomes longer. During a period when the electric field is strong, positive charges due to ions are incident on the substrate. As a result, the amount of positive charges accumulated on the substrate within one cycle increases. According to the calculation by the inventor, the amount of positive charge accumulated in the substrate within one cycle is not so large as to damage the gate insulating film even if it increases.
[0055]
When the amount of positive charge accumulated on the substrate increases, the period during which the potential of the substrate approaches the plasma potential becomes longer when the electric field becomes weaker. In addition, the absolute value of the electric field during this period also becomes smaller, and the substrate potential becomes closer to the plasma potential. As a result, even lower energy electrons are incident on the substrate. Considering only the electrons incident on the substrate, the effective electron temperature of the incident electrons decreases.
[0056]
That is, reducing the electron temperature is effective in preventing damage to the substrate, but this electron temperature is the electron temperature of electrons that are effectively incident on the substrate, and the electron temperature is not necessarily in the period when electrons are not incident on the substrate. It doesn't have to be low.
[0057]
The electron temperature could also be lowered by increasing the pressure in the plasma atmosphere, lowering the microwave power, or adding a gas with a low ionization potential.
[0058]
In the ECR plasma apparatus of FIG. 3A, when the coil current of the internal coil 11 was changed from + 8A to −8A, the entire surface of the wafer was not damaged.
[0059]
Further, when the rf bias power was set to 0 W, the damage was completely eliminated. Even under these conditions, it is considered that the electron temperature of electrons incident on the substrate is effectively lowered.
[0060]
Note that only electrons with high kinetic energy can contribute to the current I near the floating potential. Therefore, it can be said that the electron temperature obtained in this potential region reflects a high energy component. It is considered that the process of accumulating negative charges on the upper side wall of the insulating film pattern is mainly governed by high kinetic energy electrons. Therefore, it is considered preferable to control the electron temperature for an electronic component with high kinetic energy.
[0061]
In the above experiment, a gate insulating film having a thickness of 8 nm was used. However, when a thinner gate insulating film is used, it is considered that the potential of the antenna conductor rises to a value almost close to the withstand voltage of the insulating film. When the antenna potential increases, electrons are considered to be drawn, and electrons are easily drawn by lowering the electron temperature. Therefore, it can be estimated that damage can be suppressed if the upper limit of the electron temperature is lowered in accordance with the withstand voltage, which is an allowable potential. Therefore, it is preferable that the electron temperature of the plasma be equal to or lower than the withstand voltage of the insulating film.
[0062]
By the way, when the input energy to the plasma is modulated, the electron temperature is considered to change over time according to the modulation of the input energy. Hereinafter, an inductively coupled plasma etching apparatus will be described as an example.
[0063]
FIG. 5 is a schematic sectional view showing an inductively coupled plasma etching apparatus according to an embodiment of the present invention. A ceramic bell jar 62 is disposed on an outer container 61 such as stainless steel, and constitutes an airtight reaction chamber 51. A gas introduction port 52 and an exhaust port 53 are connected to the reaction chamber 51. An etching gas source EG is connected to the gas introduction port 52, and an exhaust device EVAC is connected to the exhaust port 53.
[0064]
A two-turn coil 60 is arranged around the ceramic bell jar 62 and connected to the rf source power source 58 via the matching circuit 59. The rf power of 13.56 MHz is supplied from the source power source 58 to the coil 60, and the rf power is inductively introduced into the reaction chamber 51. An etching gas is introduced into the reaction chamber 51 from the gas introduction port 52, exhausted from the exhaust port 53 to maintain the reaction chamber 51 at a predetermined pressure, and 13.56 MHz rf power is input to the reaction chamber 51. Plasma can be generated in the reaction chamber 51. This plasma reaches the substrate 55 placed on the susceptor 54.
[0065]
The susceptor 54 is connected to an rf bias source 56 incorporating a matching circuit. By applying rf power of a desired frequency (typically 66.7 kHz) from the rf bias source 56, the potential of the substrate 55 is controlled, and ions in the plasma are accelerated to a desired energy to collide with the substrate 55. Can be made.
[0066]
An rf signal similar to the rf output waveform is extracted from the rf bias source 56 and supplied to the pulse generator 57. The pulse generator 57 generates a pulse having a desired ON period synchronized with a desired phase at the same repetition period as the input rf signal. This pulse signal is input to the source power supply 58 and ON / OFF-modulates the 13.56 MHz rf power according to the pulse. That is, the plasma excitation power is ON / OFF modulated in synchronization with the substrate bias.
[0067]
In the reaction chamber 51, an ON / OFF modulated plasma is generated, and an rf bias synchronized with the ON / OFF modulation of the plasma is applied to the substrate 55. An inner container 63 whose temperature can be controlled by a heater 64 is disposed around the susceptor 54. The plasma composition can be controlled by controlling the temperature. Further, the inner vessel 63 is grounded, and the rf bias applied to the susceptor 54 is prevented from changing the plasma potential.
[0068]
FIG. 6 is a waveform diagram for explaining the operation of the above plasma generator. A waveform (a) schematically shows an input power waveform when the source power for plasma excitation is continuously input.
[0069]
Waveform (b) schematically shows the voltage waveform of the rf bias. Particularly when the source power is not synchronized, the waveform of the rf bias appears in various phases as shown in the figure.
[0070]
A waveform (c) schematically shows a power waveform when the source power is ON / OFF modulated as described above. While the power is turned on, excitation energy is given to the plasma, but during the period when the power is turned off, the plasma input power becomes “0”.
[0071]
The waveform (d) schematically shows the electron temperature in the plasma excited by the waveform (c). While source power is applied, electrons are accelerated and the electron temperature rises. Assume that the source power is turned off while the electron temperature is rising. When the source power is turned off, the electrons in the plasma are no longer accelerated, and the electrons inelastically collide with atoms, molecules, ions and reaction vessel walls in the plasma and lose energy. For this reason, the electron temperature gradually decreases. Thus, when the source power is ON / OFF modulated, the electron temperature rises / falls in synchronization with the ON / OFF of the source power.
[0072]
Waveform (e) shows the waveform of the rf bias tuned to the source power modulation so as to reach the maximum potential when the source power changes from off to on. If the inflow of electrons to the substrate occurs when the rf bias is highest, the electron temperature is lowest at this time. That is, the effective electron temperature of electrons flowing into the substrate is selected to be the lowest. Waveform (f) shows the electron current that flows from the plasma to the substrate when the rf bias of waveform (e) is applied.
[0073]
As shown in the waveform (b), if the rf bias is made asynchronous with the ON / OFF of the source power, the timing at which electrons flow into the substrate is irrelevant to the modulation of the source power, and the effective electron temperature is the waveform (d ) Will be the average value. Alternatively, it may be controlled by the maximum value of the waveform (d).
[0074]
In order to verify the above consideration, an experiment described below was conducted. FIG. 7 shows the structure of the sample used in the experiment. FIG. 7A is a cross-sectional view of a sample. A thick field oxide film 14 a formed by LOCOS is formed on the surface of the silicon substrate 13. A gate oxide film 14b having a thickness of 6 nm is formed in the opening defined by the field oxide film 14a. A gate wiring layer 15 is formed on the gate oxide film 14b and the field oxide film 14a.
[0075]
The gate wiring layer 15 is formed by stacking a polycrystalline silicon layer and an aluminum layer, similarly to the gate wiring layer shown in FIG. A resist mask 16 is formed on the gate wiring layer 15. The resist mask 16 has a thickness of 1.2 μm, and has a width w = 0.6 μm, a distance d = 0.6 μm, and is formed by stripes parallel to each other, as shown in FIG. 7B. The aspect ratio of the opening is 2.
[0076]
As shown in FIG. 7B, a part of the gate wiring layer 15 protrudes downward, and a MOS capacitor C is formed in this part. Note that the cross-sectional view of FIG. 7A is schematic and does not exactly match the plan view of FIG.
[0077]
FIG. 8 shows the phase relationship between the ON / OFF modulation of the source power used in the experiment and the synchronous rf bias. The timing at which the source power is turned on is set to 0 °, and the angle (advance angle) at which the maximum potential of the rf bias advances from the phase at which the source power is turned on is defined as the phase angle θ. θ was set to 0 °, 90 °, 180 °, and 270 °. Note that in the ON / OFF modulation of the source power, the on period was 5 μsec and the off period was 10 μsec. Therefore, when the maximum potential of the rf bias is synchronized at the end of the ON period, the phase angle is 240 °.
[0078]
In addition, in the experiment, the case of continuous discharge shown in FIG. An experiment was also conducted in the case of asynchronous (the waveform of FIG. 6B) in which the rf bias is not synchronized with ON / OFF of the source power.
[0079]
In the case of using a sample to which a surface-exposed antenna was connected, damage in the plasma processing apparatus was not detected even at an antenna ratio of 1000000. As the plasma treatment conditions, Ar gas having a pressure of 0.53 Pa was used, the average value of the source power was 100 W, and the rf bias power was 22 W. At this time, the ion current density obtained by the Langmuir probe measurement is 1 mA / cm.²It was about.
[0080]
In the source power ON / OFF modulation experiment of FIG. 8, the on period was 5 μsec and the off period was 10 μsec. Therefore, the repetition frequency is 66.7 kHz. The asynchronous rf bias was 60 kHz. In addition, the source power during the on period was 300 W, and an average of 100 W was realized.
[0081]
FIG. 9 is a graph showing experimental results. The horizontal axis indicates the type of discharge, and the vertical axis indicates the capacitor breakdown rate in%. In addition, the sample which measured the capacitor destruction rate has an antenna ratio of 10^FiveIt is. In the case of continuous discharge, the capacitor breakdown rate was 90% or more, indicating a probability of nearly 100%. When the source power is modulated on / off, the breakdown rate is reduced to about 70%. It is considered that the average value of the electron temperature is lowered by the ON / OFF modulation.
[0082]
When the synchronous rf bias was applied at a phase of 0 °, the breakdown rate decreased to about 5%. This is a significant improvement that cannot be expected when using asynchronous rf bias. As the phase is increased from 0 °, the destruction rate increases.
[0083]
Since the time lengths of the on period and the off period are different, the phase 180 ° is included in the off period. The measurement results of 0 °, 90 °, and 180 ° included in the off period indicate that the capacitor breakdown rate gradually increases as the advance angle of the rf bias during the off period advances.
[0084]
The phase 270 ° is within the ON period, and the conditions are slightly different from the data of other phase angles. The capacitor breakdown rate obtained was close to the phase 180 ° breakdown rate. The reason why the capacitor breakdown rates at the four phase angles are all lower than the capacitor breakdown rates in the case of non-synchronization is not known so far.
[0085]
From the above experimental results, when the plasma excitation power is modulated, the electron temperature decreases according to the degree of input power, and when the rf bias is synchronized with ON / OFF modulation, the phase of the rf bias changes within one cycle. Correspondingly, it is assumed that the electron temperature changes. The electron temperature is lowest when the plasma excitation power changes from off to on.
[0086]
The repetition frequency of the “on” and “off” cycle is not necessarily the same as the frequency of the rf bias. For example, it may be 1/2 or 1/4 of the rf bias frequency.
[0087]
The repetition frequency is preferably selected in the frequency range of 5-500 kHz from the viewpoint of thermal relaxation of electrons and plasma maintenance. The plasma excitation power preferably has a frequency that is at least five times the repetition frequency. The plasma excitation power preferably has 3 cycles or more in each “on” period.
[0088]
The period during which electrons are injected is not actually “0” and has a certain time width. Therefore, the above-mentioned “timing at which the rf bias becomes maximum” should be considered strictly as a period during which the main part (typically 90%) of the electron current is injected. It is preferable to control so that the average electron temperature within this period becomes the lowest. For example, as shown in FIG. 6, in the case of ON / OFF modulation in which the ON period and the OFF period are different, the optimum rf bias phase is an angle slightly advanced from 0 °. In practice, the phase of the rf bias will preferably be in the range of -30 ° to + 60 °.
[0089]
Further, the electron temperature can be considered as a practical minimum value from the minimum value Temin to 30% above the amplitude. The substrate potential can be considered as a substantial maximum value from the maximum value to 10% below the amplitude.
[0090]
In this experiment, Ar gas was used for convenience such as Langmuir probe measurement. In an actual semiconductor device manufacturing process, other gases are used.
[0091]
For example, C_FourF₈Using gas, SiO₂The film can be etched. Using the apparatus shown in FIG. 5, a MOS capacitor to which the same structured antenna as described above was connected was processed. When applying a source power of 2.5 kw and an rf bias power of 250 W in continuous discharge, SiO₂The film could be etched at an etching rate of 500 nm / min. When the above sample is treated with this plasma, 10⁶The antenna showed a breakdown rate of 93%.
[0092]
When the ON / OFF time is 5 μsec / 5 μsec, the source power in the ON period is 2.5 kW, the synchronous rf bias is 100 kHz, 250 W, SiO 2₂The film could be etched at an etch rate of 330 nm / min. In this case, the destruction rate was 88%.
[0093]
When the ON / OFF time is 5 μsec / 10 μsec, the source power during the ON period is 2.5 kW, the synchronous rf bias is 66.7 kHz, 250 W, SiO 2₂The film could be etched at an etching rate of 210 nm / min, and the destruction rate was 4%.
[0094]
Damage was significantly reduced by increasing the off time. It is considered that when the off-time is lengthened, the time during which the electron temperature falls is lengthened, and the electron temperature at the end of the period is further lowered. The significant reduction in damage is believed to depend at least on this reduction in electron temperature.
[0095]
However, in this example, strictly speaking, it is considered that the average value of the source power changes and the ion current density also changes. Therefore, it will not show only off-time effects.
[0096]
If the off time is too long, the frequency of the rf bias becomes too low and it becomes difficult to apply the bias. If the source power is increased and the plasma density becomes too high, the increase in substrate potential may be clamped. This is presumably because the impedance between the substrate and the plasma when the substrate potential rises becomes small, and the impedance between the substrate and the rf bias power source becomes relatively large. This phenomenon tends to be prominent when the substrate is attracted using an electrostatic chuck.
[0097]
In such a case, the superficial optimum phase changes, and the vicinity of 180 ° may be optimum. However, if the actual potential change of the substrate is measured and the impedance between the substrate and the rf bias power supply is made sufficiently small so that a state close to a sine wave can be obtained at a desired repetition frequency, the optimum optimum phase is optimal. An effect could be obtained.
[0098]
FIG. 10 shows various modulation methods of plasma excitation energy. The sine wave shown at the top is the waveform of the rf bias, and the waveforms (a) to (e) shown below are the modulation waveforms of the plasma excitation energy.
[0099]
Waveforms (a) and (b) show changes from phase 0 ° in the case of the above-described ON / OFF modulation. When the maximum value of the rf bias enters during the on period of the plasma excitation power, the allowable range of the phase angle is about −30 ° to 0 °. As shown in the waveform (b), when the maximum value of the rf bias potential enters during the off period of the plasma excitation power, the allowable range of the phase angle is approximately 0 ° to 60 °. In general, the phase angle θ is preferably −30 ° ≦ θ ≦ + 60 °.
[0100]
In the above example, the plasma excitation power is ON / OFF modulated. It is not always necessary to completely shut off the plasma excitation power during the off period. By switching the plasma excitation power between two levels, the electron temperature can be lowered during periods when the plasma excitation power is weak.
[0101]
Waveform (c) shows an example of this case. The plasma excitation power is modulated in two steps of strength and weakness, and the maximum potential of the rf bias is generated at the timing when the plasma excitation power changes from a weak state to a strong state.
[0102]
Waveforms (d) and (e) show yet another variation. Waveform (d) shows the case where plasma excitation power having a time constant for rising and falling is used. In this case, it is preferable to control the phase of the rf bias according to the rising speed. For example, when the plasma excitation power is about to rise by 10% or more, the rf bias is selected to show the maximum value.
[0103]
In the case of the waveform (e), the plasma excitation power changes almost sinusoidally. Also in this case, it is preferable that the rf bias takes a maximum value in accordance with a state in which the plasma excitation power gradually increases from a weak state. For example, when the plasma excitation power is 25% or more of the maximum value, the rf bias voltage is selected to take the maximum value.
[0104]
FIG. 11 is a block diagram schematically showing a plasma processing apparatus according to another embodiment of the present invention. A susceptor 102 is grounded in an airtight container 101, and a substrate 103 is electrostatically adsorbed thereon. The temperature of the susceptor 102 is controlled, and helium gas is introduced between the substrate 103 and the susceptor 102. The substrate is heated / cooled via helium gas and held at the same temperature as the susceptor. A process gas whose flow rate is controlled by the mass flow controllers 104 and 105 is introduced into the container 101. This gas system can be increased to 3 systems or more as needed, or can be made into one system. The container 101 is connected to a vacuum pump via an auto pressure controller 106, and evacuates by controlling the pressure.
[0105]
The high frequency (or microwave) power from the high frequency (or microwave) oscillator 111 is introduced into the gas in the container 101 via the matching unit or coupling means 112, and the gas is turned into plasma. The following plasma can be generated by the coupling means and input power: capacitively coupled plasma using parallel plate electrodes, inductively coupled plasma using a coil wound around the container 101, and a flat plate coil (TCP coil) installed on the container 101. Inductively coupled plasma used, helicon wave plasma using both high frequency and magnetic field, ECR plasma using microwave and magnetic field, surface wave excited plasma using microwave and dielectric line, etc.
[0106]
On the other hand, high frequency power is applied to the susceptor 102. In the configuration shown in the figure, a sine wave signal from one of the two-channel arbitrary waveform generator 113 is power amplified by a high frequency amplifier 114 and applied to the susceptor 102 via a matching unit 115. A rectangular wave is supplied from the other channel of the arbitrary waveform generator 113 to a high frequency (or microwave) oscillator. Oscillator 111 is amplitude-modulated by this rectangular wave.
[0107]
An optical fiber 122 is connected to the container 101 through a window 121, and plasma emission is introduced into the end point detector 123. A change in the intensity of light having a wavelength corresponding to the end point detector setting is detected, and the progress of the process is monitored.
[0108]
The system controller 131 includes a transport system for the substrate 103 and controls the operation of the entire apparatus. The mass flow controllers 104 and 105 are sent with set values of the respective gases, and receive readings of the actual gas flow rates. The auto pressure controller 106 is supplied with the pressure setpoint and returns the actual pressure reading. The source power set value is sent to the high frequency (or microwave) oscillator 111, and the rf bias power set value is sent to the high frequency amplifier 114, and each net power reading is returned. Note that readings are often returned from matchers 112 and 115.
[0109]
The arbitrary waveform generator 113 is sent with the phase difference of each channel. A parameter group, for example, a detection wavelength, a detection condition, and the like are sent to the end point detector 123, and an end point signal is returned. The system controller 131 has a built-in clock and can proceed with the operation according to the set time. By setting a series of processing conditions in the system controller 131 in advance, the plasma processing of the substrate 103 can be automatically performed.
[0110]
In this way, the two-channel arbitrary waveform generator 113 is used, the high frequency oscillator 111 is amplitude-modulated by the output waveform, and the power is amplified by the high frequency amplifier 114. These modulations and amplifications can be automatically set and changed by the system controller along with other processing parameters. Thereby, the plasma generation conditions and the rf bias conditions can be switched arbitrarily during the plasma processing.
[0111]
Instead of the arbitrary waveform generator 113, a single sine wave generator may be used, and whether to modulate the source power according to the output thereof may be selected by a signal from the system controller. In this case, the trigger level and pulse width can be set, and the phase and ON / OFF time can be made variable. Alternatively, it may be possible to select whether to generate a rectangular wave and modulate the source power, amplify only the fundamental wave component of the rectangular wave, and use the rf bias by shifting the phase.
[0112]
FIG. 12 shows a process for performing a two-stage process. The flow rate of gas 1 and gas 2 and the pressure in the reaction vessel are set, and after stabilizing under the set conditions, the pulse off time is set to “0”, that is, continuous output, and the source power is turned on. Subsequently, the rf bias power is turned on. When a predetermined time elapses (or when an end point is detected), the rf bias power and the source power are sequentially turned off.
[0113]
Next, the setting is changed to the gas flow rate and pressure in the second stage. When the set condition is stabilized, for example, a pulse off time of 10 μsec is used, and the arbitrary waveform generator 113 generates a pulse waveform and a synchronized sine wave. If the pulse-on time is, for example, 5 μsec, the sine wave is 66.7 kHz. In accordance with these signals, the source power and the rf bias power are turned on again to perform the second stage plasma processing. When a predetermined time has elapsed, the power is turned off, the gas is stopped, the exhaust is performed, and then the process is terminated.
[0114]
The operation sequence is not limited to that described above. It is not always necessary to change all the parameters at each stage, and changes in three or more stages can be set. The on-time of the pulse can be changed in the middle, and the increase or decrease of each value can be changed optimally as necessary.
[0115]
The above-described methods include, for example, etching of a gate electrode, etching of a contact hole on the gate electrode, etching of a wiring connected to the gate electrode, etching of a via hole on this wiring, plasma cleaning in the contact hole or via hole, or gate electrode or It can be used for film formation by plasma CVD on the gate wiring.
[0116]
In the patterning of the gate electrode and wiring, damage occurs near the end point of the process. Since the conductor remains only between patterns with a narrow interval and etching is completed with a wide pattern interval, the antenna structure is connected to the gate electrode or the like. During the period in which the conductors exist between the patterns with wide intervals, the conductive layer is often electrically connected to the substrate at any position, and there is often no problem even if the electron temperature is high. Therefore, when continuous discharge is preferable from the viewpoint of processing performance and the like, continuous discharge is performed immediately before the etching end point, and a combination of ON / OFF modulation and synchronous bias is used immediately before the etching end point. Alternatively, it is possible to use both ON / OFF modulation and synchronous bias only before and after the end point.
[0117]
In the case of contact hole or via hole formation, damage occurs during the period in which the conductor is exposed near the process end point. Therefore, it is possible to switch from continuous discharge to ON / OFF modulation and synchronous bias application before the end point of the process. In this case, there is a possibility that the processing performance can be improved.
[0118]
For example, in the case of via-hole etching, charging damage can be reduced without significantly reducing throughput by starting with continuous discharge in this order and moving to an operation using pulse-modulated plasma and synchronous bias immediately before the etching end point. . In the case of wiring etching, after the end point is sufficiently passed, the continuous discharge may be resumed.
[0119]
In this way, in order to be able to switch conditions in the middle of the process, the system controller of the plasma apparatus can switch between continuous / modulation and set the pulse width with respect to the source power supply, and switch the frequency for the rf bias source It is preferable that control such as switching of preset values can be performed for each matching circuit.
[0120]
In film formation by plasma CVD, a phenomenon similar to etching damage was observed at the initial stage of film formation. In the initial stage of film formation, the film is formed earlier in the upper part of the pattern. When an insulating film is deposited on a pattern formed of a conductor by CVD, only the upper part of the pattern is covered with the insulating film in the initial stage of the process, and negative charges of electrons are accumulated. At this time, the inflow of ions becomes excessive under the pattern. For this reason, it may occur that excess ionic charges damage the gate insulating film in the initial stage of deposition. In such plasma CVD, it is desired to reduce the imbalance of charges flowing into the substrate at the initial stage of the process.
[0121]
For example, in the case of plasma CVD, pulse modulation and synchronous rf bias are used at the initial stage of film formation. In this case, it is possible to reduce charging damage without reducing the throughput so much that continuous discharge is performed from the middle. Flattening characteristics can also be obtained by applying an rf bias.
[0122]
Further, the source power source may be configured by an rf amplifier instead of an rf oscillator that can be modulated. By applying a continuous or pulse-modulated high frequency signal to the rf amplifier, a similar output can be obtained.
[0123]
Thus, various forms can be taken as means for modulation, synchronization, and phase control. When plasma is generated by microwaves, the generation of microwaves is modulated on / off, and the rf bias is synchronized with this modulation. The same applies to the case where plasma is generated by light excitation.
[0124]
In these embodiments, it is important that the electron temperature decays during the period when the plasma excitation power is turned off. The attenuation characteristic of the electron temperature is considered to vary depending on the type of gas. Therefore, an optimal effect will be obtained by selecting a sufficient off time according to the type of gas.
[0125]
When the aspect ratio of the opening of the insulating film is larger, the distance between the antenna conductor and the upper part of the insulating film pattern becomes larger, so that electrons are repelled even with less charge accumulation. Therefore, it is necessary to control to a lower electron temperature in order to prevent damage.
[0126]
Moreover, although the case where the film thickness of the gate insulating film is 6 nm and 8 nm is shown, in the case of manufacturing a semiconductor device having a thinner insulating film, the potential of the antenna conductor is lowered, so that it is difficult to draw electrons. Since the potential of the antenna conductor rises to a value almost close to the withstand voltage of the insulating film, it can be considered that electrons can be drawn in by controlling the electron temperature below this level and damage can be prevented.
[0127]
As described above, the ECR plasma apparatus and the inductively coupled plasma apparatus have been mainly described as examples. However, as long as the characteristics of plasma are used, the same principle can be applied to other apparatuses. For example, the present invention can be applied to an RIE apparatus, a helicon wave plasma apparatus, and the like.
[0128]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0129]
【The invention's effect】
As described above, according to the present invention, damage to the gate insulating film due to plasma can be prevented in plasma processing having a dense and fine pattern.
[Brief description of the drawings]
FIG. 1 is a plan view and a graph for explaining an experiment conducted by the inventor.
FIG. 2 is a cross-sectional view and a plan view of a sample used in the experiment.
FIG. 3 is a schematic cross-sectional view and a schematic view for explaining an ECR plasma apparatus and a Langmuir probe used in the experiment.
FIG. 4 is a schematic view for explaining charge-up of a substrate in a plasma process.
FIG. 5 is a block diagram showing an inductively coupled plasma apparatus used in the experiment.
FIG. 6 is a graph showing waveforms of power and potential in the plasma apparatus used in the experiment.
FIG. 7 is a cross-sectional view and a plan view of a sample used in the experiment.
FIG. 8 is a schematic diagram showing waveforms of electric power and potential in the plasma apparatus.
FIG. 9 is a graph showing experimental results.
FIG. 10 is a graph showing a modified example of the plasma processing method.
FIG. 11 is a block diagram of a plasma processing apparatus according to another embodiment of the present invention.
12 is a graph for explaining a plasma processing process using the apparatus of FIG. 11 according to another embodiment of the present invention.
[Explanation of symbols]
1 reaction chamber
2 Gas inlet
3 Exhaust port
4 Plasma generation chamber
5 Microwave waveguide
6 Microwave transmission window
7 Main coil
8 Susceptor
9 Board
10 External coil
11 Internal coil
12 rf bias source
31 Probe
32, 33 Compensation electrode
37 Variable voltage source
38 Current source
51 reaction chamber
52 Gas inlet
53 Exhaust vent
54 Susceptor
55 substrates
56 rf bias source
57 Pulse generator
58 source power
59 Matching circuit
60 coils
61 Outer container
62 Berja
63 Inner container
64 heaters

Claims (4)

(A) A semiconductor layer, a gate insulating film formed thereon and having a withstand voltage B (V) and a thickness of 10 nm or less, a conductor layer of an antenna structure formed thereon, and formed thereon And placing a semiconductor wafer having an insulator pattern having an opening with an aspect ratio greater than 1 on a susceptor in the plasma processing apparatus;
(B) A method of manufacturing a semiconductor device, comprising: etching the semiconductor wafer in a plasma having an electron temperature Te (eV) lower than a dielectric breakdown voltage B (V) over the entire surface of the semiconductor wafer. The insulator pattern is a resist pattern, said step (b) is a method of manufacturing a semiconductor device according to claim 1, wherein the step of etching the conductive layer. The semiconductor wafer, further comprising an insulating layer between the insulator pattern and the conductor layer, said step (b) of the semiconductor device according to claim 1, wherein the step of etching an opening in the insulating layer Production method. (A) A semiconductor layer, a gate insulating film formed on the semiconductor layer, having a withstand voltage of B (V), having a thickness of 10 nm or less, and an antenna structure having an antenna ratio of 500 or more formed thereon. Placing a semiconductor wafer having a body layer and an insulator pattern formed thereon and having an opening with an aspect ratio greater than 1 on a susceptor in the plasma processing apparatus;
A step of electron temperature Te (eV) is to etch the semiconductor wafer in a small plasma than the dielectric strength B (V) (b) In the semiconductor wafer over the entire surface,
(C) before the step (b), etching the semiconductor wafer in plasma having an electron temperature Teh higher than the electron temperature Te;
A method of manufacturing a semiconductor device including:

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