JP2003133297A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of preventing damages to a gate insulating film even during a fine pattern process with respect to the manufacturing technology of an insulating gate field effect transistor (IGFET) using plasma. SOLUTION: This method for manufacturing the semiconductor device comprises a step for transporting a semiconductor wafer into a plasma treatment apparatus, the semiconductor wafer having a semiconductor layer, a gate insulating film that is formed on the semiconductor layer, has a breakdown voltage of B (V) and has a thickness of 10 nm or thinner, a conductive layer of a structured antenna formed on the gate insulating film, and an insulating material pattern having an opening with an aspect ratio larger than 1 formed on the conductive layer, and a step for processing the semiconductor wafer in plasma having an electron temperature of Te (eV)<B across the entire surface of the semiconductor wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a manufacturing technique of an insulated gate field effect transistor (IGFET) using plasma.

[0002]

2. Description of the Related Art As the degree of integration of LSIs (Large Scale Integrated Circuits) is improved, the patterns are becoming finer. In order to faithfully transfer the miniaturized mask pattern to the conductive layer and insulating layer,
Anisotropic dry etching using plasma such as reactive ion etching (RIE) and electron cyclotron resonance (ECR) plasma etching is often used.

On the other hand, with the miniaturization of semiconductor elements, the thickness of the gate insulating film of the insulated gate field effect transistor has become thinner, and those having a thickness of 10 nm or less are being put to practical use. Thus, the thin gate insulating film is easily damaged by a small electric stress.

For example, in the plasma process,
Charges such as ions and electrons are incident on the substrate. Incident positive
When a difference is generated in the negative charges, the charges are charged up in the conductive layer on the gate insulating film that is electrically separated from the substrate. When a potential difference occurs between the conductive layer and the underlying substrate, a tunnel current may flow through the gate insulating film. The tunnel current may change the dielectric characteristics of the gate insulating film and cause dielectric breakdown.

As described above, the plasma process in which charge-up may occur in the conductive layer on the gate insulating film or the conductive layer connected to the gate electrode (these are referred to as gate wirings hereinafter) damages the gate insulating film. Can be given. Such processes include patterning of the gate wiring layer, opening of contact holes reaching the gate wiring layer, cleaning by sputter etching in the contact holes reaching the gate wiring layer, plasma on the surface where the gate wiring layer is partially exposed. CVD or the like.

When the gate insulating film is damaged, the yield of the semiconductor device is deteriorated due to the breakdown of the gate insulating film or the change of the dielectric property of the gate insulating film, and the reliability of the gate insulating film, and consequently the semiconductor device is improved. In some cases, reliability is lost. Therefore, it is desired to sufficiently prevent the plasma process from damaging the gate insulating film.

When the plasma on the semiconductor substrate is non-uniform, a difference occurs between the ion current and the electron current flowing into the semiconductor substrate, and a tunnel current based on this difference may flow through the gate insulating film. In a semiconductor device, the area of the gate wiring with respect to the area of the gate insulating film (hereinafter referred to as the antenna ratio) reaches about 10,000. When a conductive film having such a high antenna ratio is plasma-processed, a large amount of tunnel current may flow through the gate insulating film due to slight nonuniformity of plasma.

Therefore, it has been attempted to make the plasma used for plasma processing as uniform as possible. More specifically, it has been proposed to make the plasma potential uniform and the substrate bias voltage uniform. For example, a structure has been proposed in which a magnetic flux crosses a semiconductor substrate and the magnetic flux is parallel to the surface everywhere on the substrate.

Hereinafter, a conductive layer which is formed on a thick insulating film and is connected to an electrode on a thin insulating film such as a gate insulating film and has a larger area and which is electrically isolated is called an antenna and is thin. The ratio of the bottom area of the conductive layer on the thick insulating film to the area of the electrode on the (gate) insulating film is called the antenna ratio.

The uniformity of plasma has been measured by a gate insulating film breakdown rate, which is usually achieved by using a gate wiring having a high antenna ratio. For example, the antenna ratio is 100
It has been determined that the plasma is uniform if a gate wiring having a surface area of 10,000 and exposed on the surface (surface exposed type) is subjected to plasma treatment and the gate insulating film is not destroyed.

However, it has been found that the gate insulating film may be damaged depending on the processing pattern even if the plasma proved to be sufficiently uniform by such measurement is used. For example, in patterning the gate wiring, a photoresist mask pattern is arranged on the gate wiring layer. The ratio of the resist thickness to the opening width in the opening of the photoresist (hereinafter referred to as the aspect ratio) has become larger than 1.
When the conductive layer under the insulating pattern having such a high aspect ratio is plasma-treated, the gate insulating film may be damaged even if uniform plasma is used. An antenna structure having such an insulating film pattern having a high aspect ratio on the top is hereinafter referred to as a structured antenna.

For example, the antenna ratio is 1,000,000.
The ECR plasma proved to be uniform depending on the surface exposed antenna structure of
If the structured antenna is exposed, the gate insulating film may be damaged.

Therefore, even if a plasma having a uniform property is used for a flat conductive film having a continuous surface, in the manufacturing process of a semiconductor device having a fine pattern,
The gate insulating film will be damaged.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing damage to a gate insulating film even when processing a fine pattern.

Another object of the present invention is to provide a semiconductor device manufacturing apparatus capable of manufacturing a semiconductor device having a fine pattern while preventing damage to the gate insulating film.

[0016]

According to one aspect of the present invention, in plasma processing in the manufacture of a semiconductor device including a transistor having an insulated gate, an electron temperature Te (eV), which is a typical value of electron energy distribution in plasma, is used. ) Is smaller than the withstand voltage B (V) of the insulated gate, and at least one of rf frequency, power, magnetic field, pressure, and gas species is controlled so that electrons are present between the high aspect ratio insulator patterns. A method of manufacturing a semiconductor device is provided, which is characterized in that it is placed in an existing conductor pattern.

According to another aspect of the present invention, the semiconductor layer is formed on the semiconductor layer, has a withstand voltage of B (V) and a thickness of 1.
A gate insulating film having a thickness of 0 nm or less, a conductor layer of an antenna structure formed on the gate insulating film, and a semiconductor wafer having an insulator pattern formed on the conductor layer having an aspect ratio larger than 1 are provided in a plasma processing apparatus. The process of loading into
An electron temperature Te (eV) is applied on the entire surface of the semiconductor wafer.
And a step of processing the semiconductor wafer in plasma where Te <B.

According to another aspect of the present invention, the semiconductor layer is formed on the semiconductor layer, has a withstand voltage of B (V), and a thickness of 1.
A gate insulating film having a thickness of 0 nm or less and an antenna structure conductor layer having an antenna ratio of 500 or more formed thereon;
An insulating layer formed on the conductor layer, formed on the insulating layer,
A step of loading a semiconductor wafer having an insulator pattern having an opening having an aspect ratio of more than 1 into a plasma processing apparatus, and an electron temperature T on the entire surface of the semiconductor wafer.
and a step of etching an opening in the insulating layer in a plasma in which e (eV) is Te ≦ B.

According to another aspect of the present invention, the semiconductor layer is formed on the semiconductor layer, has a withstand voltage of B (V), and a thickness of 1.
A gate insulating film having a thickness of 0 nm or less and an antenna structure conductor layer having an antenna ratio of 500 or more formed thereon;
A step of loading a semiconductor wafer having an insulator pattern having an opening with an aspect ratio of greater than 1 formed thereon, into the plasma processing apparatus; and an electron temperature Te (eV) of Te ≦ e on the entire surface of the semiconductor wafer. A method for manufacturing a semiconductor device is provided, which includes a step of processing the semiconductor wafer in a plasma of B and a step of processing the semiconductor wafer in a plasma of an electron temperature Teh higher than the electron temperature Te.

[0020]

DETAILED DESCRIPTION OF THE INVENTION The inventor and his co-workers reported the emergence of structured antennas with a high antenna ratio during gate wiring layer etching due to the microloading effect (US patent application Ser. No. 08 / 275,426). ,
Section of the preferred embodiment). When the resist pattern is formed on the surface of the gate wiring layer after deposition and etching is performed, the gate wiring layer is initially electrically connected to the substrate, and no antenna structure appears. However, due to the micro-loading effect, even if the etching is finished in the wide opening region, the etching is not finished in the narrow opening region. At this stage, the gate wiring layer has a divided shape in a region with a wide opening. At this transition stage, a structured antenna with a high antenna ratio appears.

When a bias rf is applied to the substrate to generate an electric field that attracts the ions in the plasma to the substrate, the ions in the plasma are accelerated toward the substrate. However, the electrons in the plasma are decelerated as they travel toward the substrate. The force due to this electric field is perpendicular to the surface of the substrate, and is not decelerated in the direction parallel to the surface of the substrate.

Therefore, it is considered that most of the electrons, which reflect the random motion in the plasma and have various motion directions, are obliquely incident on the substrate. Therefore, while the ions hardly collide with the upper side wall of the insulating pattern of the structured antenna having the insulating pattern, a large amount of electrons collide. As a result, negative charges are accumulated on the sidewalls of the insulating pattern.

It is considered that when the electric field due to this negative charge becomes large, electrons are repelled and it is difficult to enter the inside of the pattern. Therefore, as compared with the positive charge inflow by the ions, the negative charge inflow by the electrons is insufficient, and as a result, the current due to the excess positive charge is accumulated in the gate wiring layer, passes through the gate insulating film as a tunnel current, and is damaged. It is thought to occur.

FIGS. 1A, 1B and 1C show the experiments conducted by the present inventor. FIG. 1A is a plan view showing how the gate insulating film is destroyed in each chip on the plasma-processed wafer. FIG. 1B is a schematic plan view showing the insertion direction of the probe used for measuring the electron temperature of plasma. FIG. 1C is a graph showing the electron temperature of plasma obtained by probe measurement as a function of position.

2A and 2B are a sectional view and a plan view showing the structure of a sample used in the experiment. On the surface of the silicon substrate 13, a thick field oxide film 14a and a gate oxide film 14b having a thickness of 8 nm formed in a region surrounded by the field oxide film are formed.

A polycrystalline silicon film 15a and an aluminum layer 1 are formed on the field oxide film and the gate insulating film.
The gate wiring 15 is formed by stacking 5b
It constitutes a capacitor C. A dense wiring pattern 16 made of photoresist having a thickness of 1.6 μm is formed on the gate wiring 15.

As shown in FIG. 2B, in the photoresist pattern 16, a plurality of wiring patterns having a width w = 0.75 μm are arranged in parallel with a space d = 0.8 μm. The aspect ratio of the opening is 2. These wirings are continuously connected to the MOS capacitor C shown in the lower part of the figure.

FIG. 3A shows the structure of a divergent magnetic field ECR plasma etching apparatus in which such a sample is etched. A gas inlet 2 and an exhaust port 3 are connected to the reaction chamber 1 that can be evacuated. The gas inlet 2 is connected to a predetermined etching gas source. The exhaust port 3 is connected to an exhaust device. An opening is provided in the upper part of the reaction chamber 1 and is connected to the plasma generation chamber 4. The plasma generation chamber 4 and the reaction chamber 1 form an airtight container.

A microwave transmission window 6 made of quartz or the like is airtightly provided above the reaction chamber 4, and the microwave waveguide 5 is provided.
It is connected to the. The microwave waveguide 5 introduces microwaves from the microwave generation source into the plasma generation chamber 4.

Around the plasma generating chamber 4, a main coil 7 is provided.
Are arranged to generate a divergent magnetic field in the microwave generation chamber 4. The divergent magnetic field forms the ECR condition.

A susceptor 8 for mounting a substrate 9 is arranged below the reaction chamber 1, and the susceptor 8 is connected to an rf bias source 12. The rf bias source 12 is 1
An rf voltage of 3.56 MHz is supplied to the susceptor 8. An outer coil 10 on the outer side and an inner coil 11 on the inner side are concentrically arranged under the susceptor 8.

An etching gas is introduced from the gas introduction port 2 and exhausted from the exhaust port 3 to form an etching gas atmosphere of a predetermined pressure in the reaction chamber 1 and the plasma generation chamber 4. ECR plasma is generated in the plasma generation chamber 4 by introducing microwaves from the microwave waveguide 5 into the plasma generation chamber 4 while generating a magnetic field by the main coil 7. This plasma drifts in the reaction chamber 1 due to the diverging magnetic field and reaches the substrate 9 on the susceptor 8.

13.56 MHz from rf bias source 12
Of rf power to the susceptor 8
Is controlled to generate a bias electric field so as to accelerate the ions in the plasma toward the substrate 9. Under such conditions, the sample on the substrate 9 was subjected to plasma etching.

The main coil current 21 is the etching condition.
A, external coil current 8A, internal coil current 8A, etching gas Cl ₂ + BCl ₃ , pressure 0.6 Pa, microwave power 800 W, and rf bias power 180 W.

FIG. 1A shows the result of etching the sample formed on each chip 22 on the wafer 9 by the etching under this condition. On each chip 22 on the wafer 9, a MOS capacitor having a gate oxide film thickness of 8 nm, to which the antenna shown in FIGS. 2A and 2B is connected, is formed. After etching this antenna, the breakdown voltage of the MOS capacitor was measured.

White squares represent chips having a normal breakdown voltage, and hatched squares represent samples having a poor breakdown voltage, that is, a sample that was broken during etching. The region shown by a single hatch on the lower right shows the region where the sample with the antenna ratio of 10 ⁶ was destroyed, and the cross-hatched region shows the region where the sample with the antenna ratio of 10 ⁵ was destroyed.

A sample with an antenna ratio of 10 ⁴ was also formed at the same time, but it was destroyed in almost the same region as the destroyed region of the sample with an antenna ratio of 10 ⁵ . From FIG. 1 (A),
It can be seen that the sample was not destroyed on the entire surface of the wafer, but the sample was destroyed in a certain area. From another point of view, the gate insulating film is not destroyed in a certain region on the wafer. That is, it is considered that the region shown by the white square has a plasma that can prevent damage to the gate insulating film.

Therefore, the properties of plasma were measured using a Langmuir probe with a compensation electrode. FIG. 1B shows the insertion direction of the probe on the wafer 9. The height of the probe was about 4 cm from the wafer surface.

FIG. 3B schematically shows the structure of the Langmuir probe. A platinum wire having a radius of 0.5 mm and a length of 5 mm was used as the probe 31. In the probe 31, the compensation electrodes 32 and 33 made of aluminum are provided in the capacitor 3
4, 35 are connected. These compensation electrodes 3
Reference numerals 2 and 33 are electrodes for compensating the fluctuating plasma potential.

The probe 31 includes an ammeter 38 and a variable voltage source 3 through a filter 36 that cuts off the used rf frequency.
Connected to 7. The other pole of the variable voltage source 37 and the outer wall of the reaction chamber 1 are grounded.

The position of the probe 31 was moved on the wafer 9 as shown in FIG. 1 (B), and the current I flowing by sweeping the voltage V of the variable voltage source 37 at each point was measured by the ammeter 38.
From the obtained VI characteristic, ΔV / ΔlnI near the floating potential at which the current value becomes “0” was calculated, and the electron temperature was obtained in units of eV by a known method.

FIG. 1C shows the obtained electron temperature (eV).
Shows the relationship with respect to the radial position on the wafer 9. The electron temperature distribution shows a clear change corresponding to the region where the sample is destroyed. That is, the electron temperature is as high as about 10 eV or more in the region where the sample is destroyed, and the electron temperature is about 7 eV in the region where the sample is not destroyed.
Low as below. From this result, it is understood that when the electron temperature in the plasma is high, the gate insulating film having the structured antenna is easily broken.

The gate insulating film in the sample is a silicon oxide film having a thickness of 8 nm, and the withstand voltage of this silicon oxide film is about 8V. Therefore, the sample is not damaged in the electron temperature region lower than the withstand voltage of the gate insulating film, typically about 1 eV or more.

On the contrary, the gate insulating film is damaged in the electron temperature region higher than the breakdown voltage of the gate insulating film, typically higher than about 2 eV. Therefore, in order to prevent damage to the gate insulating film, it is desirable that the electron temperature of plasma be lower than the breakdown voltage of the gate insulating film.

Damage to the gate insulating film is likely to occur when the film thickness of the gate insulating film is 10 nm or less, the antenna ratio is 500 or more, and the aspect ratio is 1 or more. In particular, damage is likely to occur when the wafer diameter is 8 inches or more.

As described above, it can be understood that even if the plasma having the uniform characteristics on the flat surface is used, the damage that may occur in the processing of the fine pattern can be prevented by controlling the electron temperature of plasma on the entire surface of the wafer to be low. It was This mechanism could be thought of as follows.

First, the following model is conceivable as a mechanism for causing damage to the structured antenna even when uniform plasma is used. As shown in FIG. 4A, a bias r is applied to the substrate.
When the f power is supplied, the substrate is biased to a negative potential relative to the plasma. The positive ions in the plasma are accelerated toward the substrate by the electric field formed between the substrate and the plasma, and enter the substrate almost vertically. The electric field between the plasma and the substrate changes periodically according to the bias rf power applied to the substrate, but its direction (sign) does not change. Therefore, it can be considered that positive ions are incident on the substrate throughout the entire period.

As shown in FIG. 4B, this electric field has a moderating effect on the electrons. Therefore, the electrons are slowed down by the electric field, reflecting the random motion in the plasma,
It is considered that most of the light is incident on the substrate obliquely. When the electrons are obliquely incident on the substrate, the electrons are incident on the side wall of the insulating pattern on the substrate. The electrons incident on the non-conductive area charge up the area.

That is, almost no ions collide with the upper side wall of the insulator pattern of the structured antenna, but only electrons collide. As a result, negative charges are accumulated on the side wall. The accumulated negative charges form an electric field that repels electrons. According to the strength of this electric field, electrons cannot enter the pattern. It can be considered that the accumulation of negative charges on the upper sidewall of the insulator pattern is dominated by the lateral velocity of electrons in the plasma.

The lateral velocity of this electron depends on the electron temperature. If the proportion of electrons having a high lateral velocity is high, the negative charges accumulated on the sidewalls of the insulator pattern become large, and the electron current cannot be balanced against the positive charge inflow of the incident ions throughout the entire period. As a result, excess positive current is considered to pass through the gate insulating film and cause damage.

When the electron temperature is lowered, the average kinetic energy of electrons is lowered and the number of high energy electrons is also reduced. The movement of electrons is random. As shown in FIG. 4 (C), when the velocity of electrons is decomposed into a velocity component v _y perpendicular to the substrate and a velocity component v _x parallel to the substrate surface and considered, the distribution of v _x when no external force works The distributions of v _y are equal. When an electric field perpendicular to the substrate is generated, the vertical component v _y is accelerated / decelerated by the electric field between the plasma and the substrate, while the horizontal component v _x is hardly affected by the electric field. It is considered that when the electron temperature is lowered, the lateral velocity component v _{x of the} electron is lowered and the negative charge accumulated on the upper side wall of the insulator pattern is reduced.
Assuming that the vertical velocity component v _y of the electron is maintained at a substantially constant value due to the interaction with the electric field regardless of the electron temperature, the lower the electron temperature, the smaller the amount of charge-up on the side wall, and the more it flows into the substrate. The electron current generated can be increased.
It is considered that such a mechanism can suppress an excess of positive charges that enter the substrate when the electron temperature is lowered.

The incidence of electrons on the substrate is not uniform over the entire period. When the bias electric field between the plasma and the substrate is strong, the electrons are repelled by the electric field and cannot reach the substrate. It is considered that the bias electric field between the plasma and the substrate becomes weak and the electrons enter the substrate only during the period when the electrons approach the substrate. When the substrate bias is the rf bias, the electric field formed between the plasma and the substrate varies according to the frequency of the rf bias.

In the ECR plasma etching apparatus shown in FIG. 2A, the frequency of the rf bias source 12 was set to 13.
It was changed from 56 MHz to 400 kHz. as a result,
The gate insulating film was not damaged on the entire surface of the wafer. This phenomenon can be considered as follows.

By reducing the frequency, the period during which the electric field formed between the plasma and the substrate is strong becomes longer. During the period when the electric field is strong, positive charges due to ions are incident on the substrate. As a result, the amount of positive charges accumulated on the substrate in one cycle increases. According to the calculation by the inventor,
The amount of positive charges accumulated on the substrate in one cycle is not enough to damage the gate insulating film even if it increases.

When the amount of positive charges accumulated on the substrate increases, the period in which the potential of the substrate approaches the plasma potential becomes longer when the electric field weakens. In addition, the absolute value of the electric field in this period also becomes small, and the substrate potential approaches the plasma potential. As a result, even lower energy electrons will be incident on the substrate. Considering only the electrons incident on the substrate, the effective electron temperature of the incident electrons is lowered.

That is, it is effective to prevent damage to the substrate by lowering the electron temperature, but this electron temperature is the electron temperature of the electrons that are effectively incident on the substrate, and the electron temperature is the electron temperature when no electrons are incident on the substrate. The temperature does not necessarily have to be low.

The electron temperature could be lowered by raising the pressure of the plasma atmosphere, lowering the microwave power, or adding a gas having a low ionization potential.

In the ECR plasma apparatus of FIG. 3A, when the coil current of the internal coil 11 was changed from + 8A to -8A, the wafer was completely free from damage.

When the rf bias power was set to 0 W, no damage was found on the entire surface. It is considered that even under these conditions, the electron temperature of the electrons incident on the substrate was effectively lowered.

Note that only electrons with high kinetic energy can contribute to the current I near the floating potential. Therefore, it can be said that the electron temperature obtained in this potential region reflects the high energy component. It is considered that the process of accumulating the negative charges on the upper sidewall of the insulating film pattern is mainly controlled by the high kinetic energy electrons. Therefore, it is considered preferable to control the electron temperature by targeting the electron component of high kinetic energy.

In the above experiment, the gate insulating film having a thickness of 8 nm was used, but when a thinner gate insulating film is used, it is considered that the potential of the antenna conductor rises to a value almost close to the withstand voltage of the insulating film. It is considered that the electrons are drawn in when the antenna potential rises, and the electrons are easily drawn in by lowering the electron temperature. Therefore, it can be estimated that the damage can be suppressed by lowering the upper limit of the electron temperature in accordance with the withstand voltage which is the allowable potential. Therefore, it is preferable that the electron temperature of the plasma be lower than the withstand voltage of the insulating film.

By the way, when the energy input to the plasma is modulated, it is considered that the electron temperature also changes with time according to the modulation of the energy input. Hereinafter, an inductively coupled plasma etching apparatus will be described as an example.

FIG. 5 is a schematic sectional view showing an inductively coupled plasma etching apparatus according to an embodiment of the present invention. A ceramic bell jar 6 is placed on an outer container 61 such as stainless steel.
2 are arranged to form an airtight reaction chamber 51. A gas introduction port 52 and an exhaust port 53 are connected to the reaction chamber 51. An etching gas source EG is connected to the gas inlet 52, and an exhaust device EVAC is connected to the exhaust port 53.

Around the bell jar 62 made of ceramics,
A two-turn coil 60 is arranged and connected to the rf source power supply 58 via a matching circuit 59. The rf power of 13.56 MHz is supplied from the source power source 58 to the coil 60, and the rf power is inductively input into the reaction chamber 51. By introducing the etching gas into the reaction chamber 51 through the gas introduction port 52, exhausting the gas through the exhaust port 53 to maintain the inside of the reaction chamber 51 at a predetermined pressure, and supplying rf power of 13.56 MHz to the reaction chamber 51. Plasma can be generated in the reaction chamber 51. This plasma is susceptor 54
It reaches the substrate 55 placed on it.

The susceptor 54 is connected to an rf bias source 56 containing a matching circuit. desired frequency from rf bias source 56 (typically 66.7 kHz)
It is possible to control the potential of the substrate 55 and accelerate the ions in the plasma to a desired energy so that the ions collide with the substrate 55.

An rf signal similar to the rf output waveform is taken out from the rf bias source 56 and supplied to the pulse generator 57. The pulse generator 57 generates a pulse having a desired ON period in synchronization with a desired phase at the same repetition period as the input rf signal. This pulse signal is input to the source power supply 58, and rf power of 13.56 MHz is ON / OFF-modulated according to the pulse. That is, the plasma excitation power is ON / OFF modulated in synchronization with the substrate bias.

In the reaction chamber 51, ON / OFF-modulated plasma is generated, and an rf bias synchronized with the ON / OFF modulation of this plasma is applied to the substrate 55. An inner container 63 whose temperature can be controlled by a heater 64 is arranged around the susceptor 54. The plasma composition can be controlled by controlling the temperature. In addition, the inner container 63 is grounded to prevent the rf bias applied to the susceptor 54 from changing the plasma potential.

FIG. 6 is a waveform diagram for explaining the operation of the plasma generator described above. Waveform (a) schematically shows the input power waveform when the source power for plasma excitation is continuously input.

Waveform (b) schematically shows the voltage waveform of the rf bias. In particular, when not synchronized with the source power, the rf bias waveform appears in various phases as shown in the figure.

Waveform (c) schematically shows a power waveform when the source power is ON / OFF-modulated as described above.
Excitation energy is applied to the plasma while the power is being supplied, but the plasma supply power is "0" while the power is off.

The waveform (d) schematically shows the electron temperature in the plasma excited by the waveform (c). While the source power is being applied, the electrons are accelerated and the electron temperature rises. Suppose the source power is turned off while the electron temperature is rising. When the source power is turned off, the electrons in the plasma are not accelerated, and the electrons inelastically collide with atoms, molecules, ions in the plasma and the wall of the reaction vessel, and lose energy. Therefore, the electron temperature gradually decreases. In this way, when the source power is ON / OFF-modulated, the electron temperature rises / falls in synchronization with the ON / OFF of the source power.

The waveform (e) shows the waveform of the rf bias tuned to the source power modulation so as to have the highest potential when the source power changes from OFF to ON. If the inflow of electrons into the substrate occurs at the maximum rf bias,
At this time, the electron temperature is the lowest. That is, the effective electron temperature of the electrons flowing into the substrate is selected to be the lowest.
Waveform (f) shows the electron current flowing from the plasma to the substrate when the rf bias of waveform (e) is applied.

As shown in the waveform (b), if the rf bias is asynchronous with the ON / OFF of the source power, the timing at which the electrons flow into the substrate has nothing to do with the modulation of the source power, and the effective electron temperature is It will be the average value of waveform (d). Alternatively, it may be dominated by the maximum value of the waveform (d).

In order to verify the above consideration, the following experiment was conducted. FIG. 7 shows the structure of the sample used in the experiment. FIG. 7A is a cross-sectional view of the sample. A thick field oxide film 14a formed by LOCOS is formed on the surface of the silicon substrate 13. The opening defined by the field oxide film 14a has a thickness of 6 n
m gate oxide film 14b is formed. A gate wiring layer 15 is formed on the gate oxide film 14b and the field oxide film 14a.

Similar to the gate wiring layer shown in FIG. 2A, gate wiring layer 15 is formed by stacking a polycrystalline silicon layer and an aluminum layer. A resist mask 16 is formed on the gate wiring layer 15. Resist mask 16
Has a thickness of 1.2 μm, has a width w = 0.6 μm and a distance d = 0.6 μm, and is formed in parallel stripes, as shown in FIG. 7B. Aspect ratio of opening is 2
Is.

As shown in FIG. 7B, the gate wiring layer 1
A part of 5 projects to the lower part, and the MOS capacitor C is formed in this part. Note that the cross-sectional view of FIG. 7A is schematic and does not exactly match the plan view of FIG. 7B.

FIG. 8 shows ON / OFF of the source power used in the experiment.
The phase relationship between OFF modulation and synchronous rf bias is shown. The timing at which the source power was turned on was 0 °, and the angle (advance) at which the maximum potential of the rf bias advanced from the phase at which the source power was turned on was taken as the phase angle θ. θ is 0 °, 90 °, 180
270 ° was set. In addition, the source power ON / O
The FF modulation has an on period of 5 μsec and an off period of 1
It was set to 0 μsec. Therefore, if the maximum potential of the rf bias is synchronized at the end of the on period, its phase angle is 24
It becomes 0 °.

In the experiment, for comparison, FIG.
The continuous discharge shown in (A) was also measured. Also, an experiment was performed in the case of asynchronous (waveform in FIG. 6B) in which the rf bias was not synchronized with ON / OFF of the source power.

When the sample to which the surface-exposed antenna was connected was used, no damage was detected in the plasma processing apparatus even when the antenna ratio was 1,000,000. As the plasma processing conditions, Ar gas having a pressure of 0.53 Pa was used, the average value of the source power was 100 W, and the rf bias power was 22 W. At this time, the ion current density determined by Langmuir probe measurement was about 1 mA / cm ² .

In the ON / OFF modulation experiment of the source power of FIG. 8, the ON period is 5 μsec and the OFF period is 10 μs.
ec. Therefore, the repetition frequency is 66.7k
It becomes Hz. The asynchronous rf bias was 60 kHz. Further, the source power during the on period was set to 300 W, and an average of 100 W was realized.

FIG. 9 is a graph showing the experimental results. The horizontal axis represents the type of discharge, and the vertical axis represents the capacitor destruction rate in%. In addition, the sample that measured the capacitor destruction rate,
The antenna ratio is 10 ⁵ . In the case of continuous discharge, the capacitor destruction rate was 90% or more, which was close to 100%. When the source power is ON / OFF modulated, the destruction rate is 7
It has dropped to about 0%. It is considered that the average value of the electron temperature decreased due to the ON / OFF modulation.

When the synchronous rf bias was applied with a phase of 0 °, the destruction rate decreased to about 5%. This is a significant improvement that cannot be expected when using the asynchronous rf bias. The breakdown rate increases as the phase increases from 0 °.

Since the time lengths of the ON period and the OFF period are different, the phase 180 ° is included in the OFF period. The measurement results of 0 °, 90 °, and 180 ° included in the off period indicate that the capacitor breakdown rate gradually increases as the advance angle of the rf bias during the off period advances.

The phase 270 ° is within the ON period, and the conditions are slightly different from the data of other phase angles. The obtained destruction rate of the capacitor was close to the destruction rate of the phase of 180 °.
The reason why the capacitor destruction rates at the four phase angles are all lower than those in the case of non-synchronization is not known so far.

From the above experimental results, when the plasma excitation power is modulated, the electron temperature decreases according to the level of the applied power, and if the rf bias is synchronized with the ON / OFF modulation, the phase of the rf bias within one cycle. It is inferred that the electron temperature changes in accordance with the change of. The lowest electron temperature occurs when the plasma excitation power changes from off to on.

The repetition frequency of "on" and "off" cycles does not necessarily have to be the same as the frequency of the rf bias. For example, 1/2 or 1 / of the rf bias frequency
4 is acceptable.

The repetition frequency is preferably selected in the frequency range of 5-500 kHz from the viewpoint of thermal relaxation of electrons and plasma maintenance. The plasma excitation power preferably has a frequency that is 5 times or more the repetition frequency. The plasma excitation power preferably has 3 or more cycles in each "on" period.

The period in which the electrons are injected is not "0" in practice but has a certain time width. Therefore, the above "r
Strictly speaking, the "timing at which the f bias is maximized" should be considered as a period in which a main portion (typically 90% thereof) of the electron current is injected. It is preferable to control the average electron temperature within this period to be the lowest. For example, as shown in FIG. 6, O having different on and off periods
In the case of N / OFF modulation, the optimum rf bias phase is 0
It is an angle slightly advanced from °. In practice, the phase of the rf bias would preferably be in the range -30 ° to + 60 °.

Further, the electron temperature can be considered to be a practical minimum value from the minimum value Temin to 30% above the amplitude. The substrate potential can be considered to be a substantially maximum value from the maximum value to 10% below the amplitude.

In this experiment, Ar gas was used for convenience of Langmuir probe measurement and the like. Other gases are used in the actual semiconductor device manufacturing process.

For example, using C ₄ F ₈ gas, SiO ₂
The film can be etched. Using the device shown in FIG. 5, a MOS to which an antenna with a structure similar to that described above is connected
The capacitor was processed. Source power 2.5k with continuous discharge
w, rf When bias power of 250 W is applied, SiO ₂
The film could be etched at an etching rate of 500 nm / min. Treatment of the above sample with this plasma results in 10
^{The 6} antennas showed a destruction rate of 93%.

ON / OFF time is 5 μsec / 5 μse
c, the source power during the ON period was 2.5 kW, the synchronous rf bias was 100 kHz, and 250 W, the SiO ₂ film could be etched at an etching rate of 330 nm / min.
In this case, the destruction rate was 88%.

ON / OFF time is 5 μsec / 10 μs
ec, the source power during the ON period is 2.5 kw, and the synchronization is r
If the f bias is 66.7 kHz and 250 W, Si
The O ₂ film could be etched at an etching rate of 210 nm / min, and the destruction rate was 4%.

Damage was significantly reduced by increasing the off-time. It is considered that when the off time is lengthened, the electron temperature lowers longer, and the electron temperature at the end of the period is further lowered. It is believed that the significant reduction in damage depends at least on this reduction in electron temperature.

However, strictly speaking, in this example, it is considered that the average value of the source power is changing and the ion current density is also changing. Therefore, it may not be the only off-time effect.

If the off-time is made longer, the frequency of the rf bias becomes too low and it becomes difficult to apply the bias. If the source power is increased and the plasma density becomes too high, the rise in substrate potential may be clamped. It is considered that this is because the impedance between the substrate and the plasma becomes small when the substrate potential rises, and the impedance between the substrate and the rf bias power supply becomes relatively large. This phenomenon tends to be remarkable when the substrate is attracted by using the electrostatic chuck.

In such a case, the superficial optimum phase may change, and the optimum phase may be around 180 °. However, if the actual potential change of the substrate is measured and the impedance between the substrate and the rf bias power supply is made sufficiently small so that a state close to a sine wave can be obtained at the desired repetition frequency, the optimum phase at the original optimum phase can be obtained. You can get the effect.

FIG. 10 shows various methods of modulating the plasma excitation energy. The sine wave shown at the top is an rf bias waveform, and the waveforms (a) to (e) shown below are shown.
Is the modulation waveform of the plasma excitation energy.

The waveforms (a) and (b) are the above-mentioned ON / OF.
A change from a phase of 0 ° in the case of F modulation is shown. When the maximum value of the rf bias is entered during the ON period of the plasma excitation power, the allowable range of the phase angle is approximately −30 ° to 0 °. As shown in the waveform (b), when the maximum value of the rf bias potential enters during the off period of the plasma excitation power, the allowable range of the phase angle is approximately 0 ° to 60 °. Generally, the phase angle θ is preferably −30 ° ≦ θ ≦ + 60 °.

In the above example, the plasma excitation power is ON / OFF modulated. It is not always necessary to cut off the plasma excitation power during the off period. By switching the plasma excitation power to two levels, the electron temperature can be lowered during the period when the plasma excitation power is weak.

Waveform (c) shows an example of this case. The plasma excitation power is modulated in two levels, that is, the maximum potential of the rf bias is generated at the timing when the plasma excitation power changes from the weak state to the strong state.

Waveforms (d) and (e) show further variations. The waveform (d) shows the case where the plasma excitation power having the time constants at the rising edge and the falling edge is used. In this case, it is preferable to control the phase of the rf bias according to the rising speed. For example, when the plasma excitation power is about to rise 10% or more, r
The f bias is selected so that it exhibits the maximum value.

In the case of the waveform (e), the plasma excitation power changes almost sinusoidally. Also in this case, it is preferable that the rf bias takes the maximum value in accordance with the state in which the plasma excitation power is gradually weakened and gradually increased. For example, the rf bias voltage is selected to have the maximum value when the plasma excitation power reaches 25% or more of the maximum value.

FIG. 11 is a block diagram schematically showing a plasma processing apparatus according to another embodiment of the present invention. The susceptor 102 is grounded in the airtight container 101, and the substrate 103 is electrostatically adsorbed thereon. The temperature of the susceptor 102 is controlled, and helium gas is introduced between the substrate 103 and the susceptor 102. The substrate is heated / cooled via helium gas and kept at the same temperature as the susceptor. Container 101
A process gas whose flow rate is controlled by the mass flow controllers 104 and 105 is introduced therein. This gas system can be increased to three or more systems or one system as required. The container 101 is connected to a vacuum pump via an auto pressure controller 106, and controls the pressure to exhaust.

High frequency (or microwave) oscillator 11
The high frequency (or microwave) electric power from 1 is introduced into the gas in the container 101 through the matching device or the coupling means 112 to turn the gas into plasma. The following plasmas can be generated by the coupling means and the input power: capacitively coupled plasma by parallel plate electrodes, inductively coupled plasma using a coil wound around the container 101, and a flat coil (TCP coil) installed on the container 101. Inductively coupled plasma used,
Helicon wave plasma using both high frequency and magnetic field, ECR plasma using microwave and magnetic field, surface wave excited plasma using microwave and dielectric line, etc.

On the other hand, high frequency power is applied to the susceptor 102. In the configuration shown in the figure, the sine wave signal from one of the two-channel arbitrary waveform generator 113 is power-amplified by the high-frequency amplifier 114 and applied to the susceptor 102 via the matching unit 115. A rectangular wave is supplied to the high-frequency (or microwave) oscillator from the other channel of the arbitrary waveform generator 113. This rectangular wave allows the oscillator 1
11 is amplitude-modulated.

An optical fiber 122 is connected to the container 101 through a window 121, and plasma emission is introduced into the end point detector 123. The progress of the process is monitored by detecting the intensity change of the light of the wavelength corresponding to the end point detector setting.

The system controller 131 includes the board 10
It controls the operation of the entire apparatus including the transportation system of No. 3. The mass flow controllers 104 and 105 are supplied with set values for each gas and receive a reading of the flow rate of the gas that is actually flowing.
The pressure setpoint is supplied to the autopressure controller 106 and the actual pressure reading is returned. The high frequency (or microwave) oscillator 111 has a source power setting value,
The rf bias power setpoint is sent to the high frequency amplifier 114 and each net power reading is returned. Note that readings are often returned by the matchers 112, 115.

The phase difference of each channel is sent to the arbitrary waveform generator 113. A parameter group such as a detection wavelength and a detection condition is sent to the end point detector 123, and an end point signal is returned. The system controller 131 has a built-in clock so that the operation can proceed according to a set time.
By presetting a series of processing conditions in the system controller 131, plasma processing of the substrate 103 can be performed automatically.

As described above, the 2-channel arbitrary waveform generator 113 is used, and the high-frequency oscillator 11 is generated by the output waveform thereof.
1 is amplitude-modulated and power is amplified by the high frequency amplifier 114. These modulations and amplifications can be automatically set and changed by the system controller along with other processing parameters. Thereby, the plasma generation condition and the rf bias condition can be arbitrarily switched during the plasma processing.

Instead of the arbitrary waveform generator 113, a single sine wave generator may be used, and whether to modulate the source power by its output may be selected by a signal from the system controller. In this case, the trigger level and pulse width can be set, and the phase and ON / OFF time can be made variable. Alternatively, it may be possible to select whether to generate a rectangular wave and modulate the source power, amplify only the fundamental wave component of the rectangular wave, shift the phase, and use the rf bias.

FIG. 12 shows a process for performing a two-step process. After setting the flow rates of gas 1 and gas 2 and the pressure in the reaction vessel to stabilize under the set conditions, pulse off time "
0 ", that is, continuous output is set, and the source power is turned on. Then, the rf bias power is turned on. After a predetermined time has passed (or when the end point is detected), rf
Bias power and source power are turned off sequentially.

Next, the setting is changed to the second stage gas flow rate and pressure. When the set conditions stabilize, for example, 10 μsec
The pulse waveform is synchronized with the pulse waveform from the arbitrary waveform generator 113 using the pulse off time of. If the pulse on time is, for example, 5 μsec, the sine wave will be 66.7
It becomes kHz. According to these signals, the source power, rf
Bias power is turned on again to perform the second-stage plasma processing. When the predetermined time has passed, the power is turned off, the gas is stopped, the gas is exhausted, and then the process is terminated.

The operation sequence is not limited to that described above. It is not always necessary to change all parameters at each stage, and changes in three or more stages can be set. The on-time of the pulse can be changed on the way, and the increase / decrease of each value can be changed optimally as necessary.

The above-described method is, for example, etching of a gate electrode, etching of a contact hole on a gate electrode, etching of a wiring connected to the gate electrode, etching of a via hole on this wiring, plasma cleaning of a contact hole or a via hole, or It can be used for film formation by plasma CVD on a gate electrode or a gate wiring.

Damage occurs when patterning the gate electrode and the wiring near the end point of the process. Since the conductor remains only between the patterns with a narrow interval and the etching is completed with a wide pattern interval, the antenna structure is connected to the gate electrode or the like. The conductive layer is often electrically connected to the substrate at any position during the period in which the conductors are present even between the patterns having wide intervals, and there is often no problem even if the electron temperature is high. Therefore, when continuous discharge is preferable in terms of processing performance, continuous discharge is performed until just before the etching end point, and ON / OF is made just before the etching end point.
A combination of F modulation and synchronous bias is used. Alternatively, it is possible to use the ON / OFF modulation and the synchronous bias together only before and after the end point.

In the case of forming a contact hole or a via hole, damage occurs during the period when the conductor is exposed near the process end point. Therefore, it is possible to switch from continuous discharge to ON / OFF modulation and synchronous bias application before the end of the process. In this case, processing performance may be improved.

For example, in the case of via hole etching,
Starting from continuous discharge in the order as in this example, and moving to the operation using the pulse-modulated plasma and the synchronous bias immediately before the etching end point, without significantly lowering the throughput,
Charging damage can be reduced. In the case of wiring etching, continuous discharge may be resumed after the end point is sufficiently passed.

As described above, in order to make it possible to switch the conditions during the process, the system controller of the plasma apparatus can switch continuous / modulation with respect to the source power supply and set the pulse width, and the rf bias source can be set. It is preferable to be able to perform control such as frequency switching and preset value switching for each matching circuit.

In film formation by plasma CVD, a phenomenon similar to etching damage was observed at the initial stage of film formation. In the initial stage of film formation, the film is formed earlier on the pattern. When depositing an insulating film on a pattern made of a conductor by CVD, only the upper part of the pattern is covered with the insulating film at the beginning of the process, and negative charges of electrons are accumulated. At this time, the inflow of ions becomes excessive under the pattern. Therefore, excess ionic charges may damage the gate insulating film at the early stage of deposition. In such plasma CVD, it is desired to reduce the imbalance of the charges flowing into the substrate at the beginning of the process.

For example, in the case of plasma CVD, pulse modulation and synchronous rf bias are used at the initial stage of film formation. In this case, it is possible to reduce the charging damage without causing the throughput to be lowered so much that the discharge is continuously performed from the middle. It is possible to obtain the flattening characteristic by the way of applying the rf bias.

Further, the source power supply may not be composed of an rf oscillator capable of modulation but may be composed of an rf amplifier. Apply a continuous or pulse-modulated high frequency signal to this rf amplifier,
Similar output can be obtained.

As described above, various forms can be used as means for modulation, synchronization and phase control. When plasma is generated by microwave, generation of microwave is
N / OFF modulation may be performed, and the rf bias may be synchronized with this modulation. The same applies when plasma is generated by excitation with light.

In these examples, it is important that the electron temperature is attenuated during the period when the plasma excitation power is off. It is considered that the decay characteristic of the electron temperature changes depending on the type of gas. Therefore, the optimum effect will be obtained by selecting a sufficient off time according to the type of gas.

When the aspect ratio of the opening of the insulating film is larger, the distance between the antenna conductor and the upper portion of the insulating film pattern becomes large, so that electrons are repelled by a smaller amount of charge storage. Therefore, in order to prevent damage, it is necessary to control the electron temperature to be lower.

The thickness of the gate insulating film is 6 nm and 8n.
Although the case of m is shown, in the case of manufacturing a semiconductor device having a thinner insulating film, the potential of the antenna conductor is lowered, so that it becomes difficult to attract electrons. Since the electric potential of the antenna conductor rises to a value almost close to the withstand voltage of the insulating film, it is considered that the electrons can be drawn in and the damage can be prevented by controlling the electron temperature below this level.

Although the ECR plasma device and the inductively coupled plasma device have been mainly described above as examples, the same principle can be applied to other devices as long as the properties of plasma are utilized. For example, it can be applied to an RIE device, a helicon wave plasma device, and the like.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0129]

As described above, according to the present invention,
In plasma processing having a dense and fine pattern, damage to the gate insulating film due to plasma can be prevented.

[Brief description of drawings]

FIG. 1 is a plan view and a graph for explaining an experiment conducted by the present inventor.

2A and 2B are a cross-sectional view and a plan view of a sample used for an experiment.

FIG. 3 is a schematic cross-sectional view and a schematic diagram for explaining an ECR plasma device and a Langmuir probe used in an experiment.

FIG. 4 is a schematic diagram for explaining charge-up of a substrate in a plasma process.

FIG. 5 is a block diagram showing an inductively coupled plasma device used in the experiment.

FIG. 6 is a graph showing waveforms of electric power and potential in the plasma device used in the experiment.

7A and 7B are a cross-sectional view and a plan view of a sample used for an experiment.

FIG. 8 is a schematic diagram showing waveforms of electric power and potential in the plasma device.

FIG. 9 is a graph showing experimental results.

FIG. 10 is a graph showing a modification of the plasma processing method.

FIG. 11 is a block diagram of a plasma processing apparatus according to another embodiment of the present invention.

12 is a graph illustrating a plasma processing process using the apparatus of FIG. 11 according to another embodiment of the present invention.

[Explanation of symbols]

1 reaction chamber 2 gas inlet 3 exhaust port 4 Plasma generation chamber 5 microwave waveguide 6 microwave transparent window 7 Main coil 8 susceptor 9 substrates 10 external coil 11 Internal coil 12 rf bias source 31 probes 32, 33 Compensation electrode 37 Variable voltage source 38 Current source 51 Reaction Chamber 52 Gas inlet 53 Exhaust port 54 susceptor 55 substrate 56 rf bias source 57 pulse generator 58 source power 59 Matching circuit 60 coils 61 outer container 62 Berja 63 Inner container 64 heater

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Konobu Hikosaka             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited (72) Inventor Akihiro Hasegawa             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F-term (reference) 5F004 AA16 BA01 BB18 BD04 CA03                       DA00 DB03 DB08                 5F033 QQ12 VV06 XX31                 5F140 AA00 AA26 AA38 BA01 BF04                       BF11 BF15 BF58 BG38 BG46                       CA02 CA03 CB01 CE00

Claims (10)

[Claims] 1. In a plasma treatment in manufacturing a semiconductor device including a transistor having an insulated gate, an electron temperature Te which is a representative value of electron energy distribution in plasma.
At least one of rf frequency, electric power, magnetic field, pressure, and gas species is controlled so that (eV) becomes smaller than the withstand voltage B (V) of the insulated gate, so that the electron has a high aspect ratio insulator pattern. A method of manufacturing a semiconductor device, characterized in that it is inserted in a conductor pattern existing between them. 2. A semiconductor layer, a gate insulating film formed on the semiconductor layer, having a withstand voltage of B (V) and a thickness of 10 nm or less, and a conductor layer of an antenna structure formed on the gate insulating film. A step of loading a semiconductor wafer having an insulator pattern having an opening with an aspect ratio greater than 1 into the plasma processing apparatus, and (b) electron temperature Te (eV) over the entire surface of the semiconductor wafer. ), The step of processing the semiconductor wafer in plasma where Te <B is satisfied. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the insulator pattern is a resist pattern, and the step (b) is a step of etching the conductor layer. 4. The semiconductor wafer further has an insulating layer between the conductive layer and the insulating pattern, and the step (b) is a step of etching an opening in the insulating layer. A method for manufacturing a semiconductor device as described above. 5. A semiconductor layer, a gate insulating film formed on the semiconductor layer, having a withstand voltage of B (V) and a thickness of 10 nm or less, and having an antenna ratio of 500 or more formed on the gate insulating film. A semiconductor wafer having a conductor layer of an antenna structure, an insulating layer formed on the conductor layer, and an insulator pattern formed on the conductor layer and having an opening with an aspect ratio of greater than 1 is placed in a plasma processing apparatus. And (b) electron temperature Te on the entire surface of the semiconductor wafer.
And (eV) Te ≦ B. Etching an opening in the insulating layer in a plasma. 6. A semiconductor layer, a gate insulating film formed on the semiconductor layer, having a withstand voltage of B (V) and a thickness of 10 nm or less, and having an antenna ratio of 500 or more formed on the gate insulating film. A conductor layer of an antenna structure, formed on it,
A step of loading a semiconductor wafer having an insulator pattern having an opening with an aspect ratio larger than 1 into a plasma processing apparatus; (b) an electron temperature Te on the entire surface of the semiconductor wafer.
A semiconductor including: a step of processing the semiconductor wafer in a plasma having (eV) Te ≦ B; and (c) a step of processing the semiconductor wafer in a plasma having an electron temperature Teh higher than the electron temperature Te. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 6, wherein Teh> B. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the step (c) is performed before the step (b), and the steps (b) and (c) are etching steps. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the step (c) is performed after the step (b), and the steps (b) and (c) are deposition steps. 10. The method of manufacturing a semiconductor device according to claim 6, wherein the step (c) and the step (b) are alternately performed.