JP4260157B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4260157B2
JP4260157B2 JP2005329002A JP2005329002A JP4260157B2 JP 4260157 B2 JP4260157 B2 JP 4260157B2 JP 2005329002 A JP2005329002 A JP 2005329002A JP 2005329002 A JP2005329002 A JP 2005329002A JP 4260157 B2 JP4260157 B2 JP 4260157B2
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chip
semiconductor
bump
dummy
film
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JP2006060262A (en
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純一 疋田
吾郎 仲谷
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Description

この発明は、たとえば、半導体チップの表面に他の半導体チップを重ね合わせて接合するチップ・オン・チップ構造を有する半導体装置に関する。   The present invention relates to a semiconductor device having a chip-on-chip structure in which, for example, another semiconductor chip is overlapped and bonded to the surface of a semiconductor chip.

たとえば、半導体装置の小型化を図るための構造として、複数個の半導体チップを表面同士が対向するように重ね合わせて接合する、いわゆるチップ・オン・チップ構造がある。このチップ・オン・チップ構造では、図４に示すように、対向する半導体チップ９１，９２は、半導体チップ９１，９２間に設けられた複数個のバンプ９３によって、所定間隔を保つように連結され、かつ、互いに電気的に接続されている。そして、重ね合わされた複数個の半導体チップ９１，９２は、モールド樹脂９４などで樹脂封止されている。
特開平１１−１６３０５１号公報 For example, as a structure for reducing the size of a semiconductor device, there is a so-called chip-on-chip structure in which a plurality of semiconductor chips are overlapped and bonded so that their surfaces face each other. In this chip-on-chip structure, as shown in FIG. 4, the opposing semiconductor chips 91, 92 are connected by a plurality of bumps 93 provided between the semiconductor chips 91, 92 so as to maintain a predetermined interval. And electrically connected to each other. The plurality of stacked semiconductor chips 91 and 92 are resin-sealed with a mold resin 94 or the like.
Japanese Patent Laid-Open No. 11-163051

モールド樹脂９４による封止の際、半導体チップ９１，９２は、モールド樹脂９４から比較的大きな圧力を受ける。また、半導体チップ９１，９２の熱膨張率が異なる場合には、樹脂封止時において大きな熱量が与えられると、半導体チップ９１，９２に応力歪みが生じる。そのため、バンプ９３によって支持されていない部分において、半導体チップ９１，９２の変形が生じ、その結果、半導体チップ９１，９２に形成された素子の特性が劣化するといった問題があった。   During sealing with the mold resin 94, the semiconductor chips 91 and 92 receive a relatively large pressure from the mold resin 94. Further, when the thermal expansion coefficients of the semiconductor chips 91 and 92 are different, stress distortion occurs in the semiconductor chips 91 and 92 when a large amount of heat is applied during resin sealing. Therefore, there is a problem that the semiconductor chips 91 and 92 are deformed in the portions not supported by the bumps 93, and as a result, the characteristics of the elements formed on the semiconductor chips 91 and 92 are deteriorated.

そこで、本願発明者は、半導体チップ９１，９２間に、半導体チップ９１，９２の内部配線に接続していないダミーバンプを形成して、このダミーバンプによってモールド樹脂９４から受ける応力を緩和することを考えた。しかしながら、このようなダミーバンプを設けると、このダミーバンプがアンテナとなって、外部ノイズを受信し、半導体チップ９１，９２に形成された素子に悪影響を与えるおそれがあった。   Therefore, the present inventor considered that a dummy bump not connected to the internal wiring of the semiconductor chips 91 and 92 is formed between the semiconductor chips 91 and 92 and the stress received from the mold resin 94 by the dummy bumps is relieved. . However, when such dummy bumps are provided, the dummy bumps serve as antennas and receive external noise, which may adversely affect the elements formed on the semiconductor chips 91 and 92.

そこで、この発明の目的は、上術の技術的課題を解決し、機械的応力および圧力歪みを低減でき、かつ、安定した素子特性を発揮できる半導体装置を提供することである。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device that can solve the technical problems of the above operation, reduce mechanical stress and pressure strain, and exhibit stable element characteristics.

上記の目的を達成するための請求項１記載の発明は、半導体チップの表面に他の半導体チップの表面を対向させて接合するチップ・オン・チップ構造を有する半導体装置であって、少なくとも一方の前記半導体チップは、当該半導体チップの基体をなす半導体基板と、前記半導体基板上に形成された絶縁膜と、前記絶縁膜上に隆起した状態に設けられ、両半導体チップを所定の間隔を保った状態で支持するとともに、両半導体チップを電気的に接続するための機能バンプと、前記絶縁膜上に隆起した状態に設けられ、両半導体チップを所定の間隔を保った状態で支持し、両半導体チップの電気接続に寄与しないダミーバンプとを備え、前記ダミーバンプは、前記絶縁膜の表面にシード膜を積層し、このシード膜上に選択的にメッキを施すことにより形成されており、その一部が除去されることにより前記絶縁膜の表面に選択的に残された前記シード膜を介して、前記絶縁膜が除去されることにより露出した、前記半導体基板のスクライブラインに接続されていることを特徴とする、半導体装置である。 The invention according to claim 1 for achieving the above object is a semiconductor device having a chip-on-chip structure in which the surface of another semiconductor chip is bonded to the surface of the semiconductor chip so as to face the surface. The semiconductor chip is provided in a state in which a semiconductor substrate that forms the base of the semiconductor chip, an insulating film formed on the semiconductor substrate, and a raised state on the insulating film , and the two semiconductor chips are maintained at a predetermined interval. The semiconductor bumps are supported in a state and are provided in a raised state on the insulating film with functional bumps for electrically connecting the two semiconductor chips, and the two semiconductor chips are supported with a predetermined distance therebetween. and a dummy bump that does not contribute to chip electrical connection, the dummy bumps, the seed layer is deposited on the surface of the insulating film is selectively applying plating on the seed film Are more formed, via the seed film selectively left on the surface of the insulating film by a portion is removed, exposed by the insulating film is removed, the semiconductor substrate The semiconductor device is connected to a scribe line.

この構成によれば、ダミーバンプが設けられているので、樹脂封止などのために半導体チップに作用する力を分散することができ、機械的圧力や応力歪みなどに起因する半導体チップの変形を防止することができる。また、ダミーバンプは低インピーダンス部に接続されているので、ダミーバンプがアンテナとなって、半導体チップ内に外部ノイズが取り込まれるおそれがない。したがって、安定した素子特性を発揮することができる。   According to this configuration, since the dummy bumps are provided, the force acting on the semiconductor chip for resin sealing or the like can be dispersed, and deformation of the semiconductor chip due to mechanical pressure or stress strain is prevented. can do. Further, since the dummy bump is connected to the low impedance portion, the dummy bump becomes an antenna and there is no possibility that external noise is taken into the semiconductor chip. Therefore, stable element characteristics can be exhibited.

通常、スクライブラインには、表面保護膜などが設けられておらず、半導体基板の表面が露出している。したがって、この発明のように、ダミーバンプをシード膜を介してスクライブラインに接続しておくことにより、ダミーバンプを簡単に半導体基板に接続することができる。
また、請求項２記載の発明は、前記半導体基板における前記ダミーバンプとの接続部分には、低抵抗化処理が施されていることを特徴とする、請求項１記載の半導体装置である。 Usually, the scribe line is not provided with a surface protective film or the like, and the surface of the semiconductor substrate is exposed. Therefore, by connecting the dummy bumps to the scribe line via the seed film as in the present invention, the dummy bumps can be easily connected to the semiconductor substrate.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a resistance reduction process is applied to a connection portion of the semiconductor substrate with the dummy bump.

この構成によれば、半導体基板の低インピーダンス部との接続部分に低抵抗化処理が施されているので、低インピーダンス部の抵抗をさらに下げることができ、外部ノイズによる悪影響が及ぼされることをより良好に防止できる。   According to this configuration, since the resistance reduction processing is applied to the connection portion of the semiconductor substrate with the low impedance portion, the resistance of the low impedance portion can be further lowered, and the adverse effect due to external noise is exerted more. It can prevent well.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、この発明の参考例に係る半導体装置の概略構成を示す図解的な断面図である。この半導体装置は、いわゆるチップ・オン・チップ構造を有しており、親チップ１の表面１１に子チップ２の表面２１を対向させて接合した後、これらを樹脂封止してパッケージ３に納めることによって構成されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view showing a schematic configuration of a semiconductor device according to a reference example of the present invention. This semiconductor device has a so-called chip-on-chip structure. After the surface 21 of the child chip 2 is bonded to the surface 11 of the parent chip 1 so as to face each other, these are sealed with resin and stored in the package 3. Is made up of.

親チップ１は、たとえばシリコンチップからなっている。親チップ１の表面１１は、半導体基板においてトランジスタなどの機能素子が形成された活性表層領域側の表面であり、最表面は、たとえば窒化シリコンで構成される表面保護膜で覆われている。この表面保護膜上には、外部接続用の複数のパッド１２が、ほぼ矩形の平面形状を有する親チップ１の表面１１の周縁付近に露出して配置されている。外部接続用パッド１２は、ボンディングワイヤ１３によってリードフレーム１４に接続されている。   The parent chip 1 is made of, for example, a silicon chip. The surface 11 of the parent chip 1 is a surface on the active surface layer region side where functional elements such as transistors are formed on the semiconductor substrate, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. On this surface protective film, a plurality of pads 12 for external connection are disposed in the vicinity of the periphery of the surface 11 of the parent chip 1 having a substantially rectangular planar shape. The external connection pad 12 is connected to the lead frame 14 by a bonding wire 13.

子チップ２は、たとえばシリコンチップからなっている。子チップ２の表面２１は、半導体基板においてトランジスタなどの機能素子が形成された活性表層領域側の表面であり、最表面は、たとえば窒化シリコンで構成される表面保護膜で覆われている。子チップ２は、表面２１を親チップ１の表面１１に対向させた、いわゆるフェースダウン方式で親チップ１に接合されており、親チップ１との間に設けられた複数のバンプによって支持されている。具体的に説明すると、子チップ２の表面２１には、複数の子側バンプＢ２が隆起して形成されており、親チップ１の表面１１には、子側バンプＢ２に対応した位置にそれぞれ親側バンプＢ１が隆起して形成されている。そして、子チップ２は、子側バンプＢ２がそれぞれ対応する親側バンプＢ１に接続されることにより、親チップ１の上方に支持されている。   The child chip 2 is made of, for example, a silicon chip. The surface 21 of the child chip 2 is a surface on the active surface layer region side where a functional element such as a transistor is formed on a semiconductor substrate, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. The child chip 2 is joined to the parent chip 1 by a so-called face-down method in which the surface 21 is opposed to the surface 11 of the parent chip 1, and is supported by a plurality of bumps provided between the child chip 2 and the parent chip 1. Yes. More specifically, a plurality of child-side bumps B2 are formed on the surface 21 of the child chip 2 so as to rise, and the surface 11 of the parent chip 1 has a parent corresponding to the position corresponding to the child-side bump B2. The side bump B1 is formed to be raised. The child chip 2 is supported above the parent chip 1 by connecting the child-side bumps B2 to the corresponding parent-side bumps B1.

子側バンプＢ２には、子チップ２の内部の配線に接続された機能バンプＢＦと、子チップ２の内部の配線と絶縁されたダミーバンプＢＤとが含まれている。一方、親側バンプＢ１にも、子チップ２の内部の配線に接続された機能バンプＢＦと、子チップ２の内部の配線と絶縁されたダミーバンプＢＤとが含まれている。親チップ１の機能バンプＢＦと子チップ２の機能バンプＢＦとは、互いに対向して設けられており、この機能バンプＢＦ同士が接続されることにより、親チップ１の内部の配線と子チップ２の内部の配線とが電気接続されている。これに対し、親チップ１のダミーバンプＢＤと子チップ２のダミーバンプＢＤとは、互いに対向して設けられており、このダミーバンプＢＤ同士の接続は、親チップ１の内部の配線と子チップ２の内部の配線との電気接続には寄与していない。   The child-side bump B2 includes a functional bump BF connected to the wiring inside the child chip 2, and a dummy bump BD insulated from the wiring inside the child chip 2. On the other hand, the parent-side bump B1 also includes a functional bump BF connected to the wiring inside the child chip 2, and a dummy bump BD insulated from the wiring inside the child chip 2. The functional bump BF of the parent chip 1 and the functional bump BF of the child chip 2 are provided to face each other, and the wiring inside the parent chip 1 and the child chip 2 are connected by connecting the functional bumps BF to each other. Are electrically connected to the internal wiring. On the other hand, the dummy bump BD of the parent chip 1 and the dummy bump BD of the child chip 2 are provided so as to face each other, and the connection between the dummy bumps BD is the wiring inside the parent chip 1 and the inside of the child chip 2. It does not contribute to the electrical connection with the wiring.

図２は、子チップ２の構成を拡大して示す断面図である。子チップ２の半導体基板２２上には、酸化シリコン膜２３が形成されており、この酸化シリコン膜２３上に、たとえばアルミニウムで構成される配線２４が配設されている。配線２４は、酸化シリコン膜２３に形成された複数のコンタクトホール２５を介して半導体基板２２に接続されている。酸化シリコン膜２３および配線２４の表面は、表面保護膜２６で覆われており、この表面保護膜２６に形成された開口部２７に、耐酸化性の金属（たとえば金、鉛、プラチナ、銀またはイリジウムなど）からなる機能バンプＢＦが形成されている。   FIG. 2 is an enlarged cross-sectional view showing the configuration of the child chip 2. A silicon oxide film 23 is formed on the semiconductor substrate 22 of the child chip 2, and a wiring 24 made of, for example, aluminum is disposed on the silicon oxide film 23. The wiring 24 is connected to the semiconductor substrate 22 through a plurality of contact holes 25 formed in the silicon oxide film 23. The surfaces of the silicon oxide film 23 and the wiring 24 are covered with a surface protective film 26, and an oxidation-resistant metal (for example, gold, lead, platinum, silver or the like) is formed in the opening 27 formed in the surface protective film 26. A functional bump BF made of iridium or the like is formed.

一方、ダミーバンプＢＤは、表面保護膜２６上に隆起した状態に設けられており、表面保護膜２６に形成された開口部２８および酸化シリコン膜２３に形成されたコンタクトホール２９を介して、半導体基板２２に接続されている。
機能バンプＢＦおよびダミーバンプＢＤは、半導体基板２２がウエハの状態で形成される。また、ダミーバンプＢＤは、機能バンプＢＦと同じ材料を用いて形成されており、機能バンプＢＦと同じ工程で形成することができる。すなわち、酸化シリコン膜２３にコンタクトホール２５を形成する工程において、コンタクトホール２５と同時にコンタクトホール２９を形成する。そして、このコンタクトホール２５，２９が形成された酸化シリコン膜２３上に配線２４を形成する工程において、コンタクトホール２９の内部に、配線２４と同一材料で構成される金属膜３０を形成する。その後、酸化シリコン膜２３上に表面保護膜２６を堆積させ、その表面保護膜２６の配線２４および金属膜３０に臨む部分に、それぞれ開口部２７，２８を形成する。次いで、この開口部２７，２８が形成された表面保護膜２６の表面にシード膜３１を形成し、開口部２７，２８外のシード膜３１上にレジスト膜を形成した後、機能バンプＢＦおよびダミーバンプＢＤの材料を用いたメッキを行う。その後、シード膜２７上のレジスト膜を除去し、さらにレジスト膜の除去によって露出したシード膜２７を除去することにより、機能バンプＢＦと、開口部２８およびコンタクトホール２９を介して半導体基板２２に接続されたダミーバンプＢＤとを得ることができる。 On the other hand, the dummy bump BD is provided in a raised state on the surface protective film 26, and the semiconductor substrate is interposed through the opening 28 formed in the surface protective film 26 and the contact hole 29 formed in the silicon oxide film 23. 22 is connected.
The functional bump BF and the dummy bump BD are formed with the semiconductor substrate 22 in a wafer state. Further, the dummy bump BD is formed using the same material as the functional bump BF, and can be formed in the same process as the functional bump BF. That is, in the step of forming the contact hole 25 in the silicon oxide film 23, the contact hole 29 is formed simultaneously with the contact hole 25. Then, in the step of forming the wiring 24 on the silicon oxide film 23 in which the contact holes 25 and 29 are formed, a metal film 30 made of the same material as the wiring 24 is formed inside the contact hole 29. Thereafter, a surface protective film 26 is deposited on the silicon oxide film 23, and openings 27 and 28 are formed in portions of the surface protective film 26 facing the wiring 24 and the metal film 30, respectively. Next, a seed film 31 is formed on the surface of the surface protection film 26 in which the openings 27 and 28 are formed, a resist film is formed on the seed film 31 outside the openings 27 and 28, and then the functional bumps BF and dummy bumps are formed. Plating using BD material is performed. Thereafter, the resist film on the seed film 27 is removed, and the seed film 27 exposed by removing the resist film is removed, so that the functional bump BF is connected to the semiconductor substrate 22 through the opening 28 and the contact hole 29. The dummy bumps BD thus obtained can be obtained.

なお、上記シード膜３１は、たとえば、機能バンプＢＦおよびダミーバンプＢＤをＡｕ（金）で構成する場合には、表面保護膜２６上にスパッタ法でＴｉＷ（チタンタングステン）膜を形成し、そのＴｉＷ膜上にスパッタ法でＡｕを堆積させることにより形成されるとよい。
半導体基板２２のコンタクトホール２９に臨む領域２２ａには、この部分の抵抗を下げるための低抵抗化処理が施されている。この低抵抗化処理は、領域２２ａに不純物イオンを打ち込むイオン注入処理であってもよい。この場合、トランジスタなどの機能素子のソース・ドレインを形成する工程において、ソース・ドレインの形成と同時に行うことができる。 For example, when the functional bump BF and the dummy bump BD are made of Au (gold), the seed film 31 is formed by forming a TiW (titanium tungsten) film on the surface protective film 26 by sputtering, and then forming the TiW film. It may be formed by depositing Au on the top by sputtering.
The region 22a facing the contact hole 29 of the semiconductor substrate 22 is subjected to a resistance reduction process for reducing the resistance of this portion. This resistance reduction process may be an ion implantation process for implanting impurity ions into the region 22a. In this case, the step of forming the source / drain of the functional element such as a transistor can be performed simultaneously with the formation of the source / drain.

また、低抵抗化処理は、酸化シリコン膜２３を低抵抗化するために、酸化シリコン膜２３に不純物を拡散させる際に、この不純物拡散に先立って酸化シリコン膜２３に形成された開口部を介して、半導体基板２２の領域２２ａにも不純物を拡散させることにより達成されてもよい。
さらにまた、低抵抗化処理は、いわゆるサリサイド処理であってもよい。このサリサイド処理では、酸化シリコン膜２３の領域２２ａに対向する部分を除去した後、表面全域にチタンをスパッタ蒸着させる。そして、たとえば約８００度の熱処理を２回施すことにより、チタンと領域２２ａのシリコンとを反応させた後、たとえばアンモニア水で未反応のチタンを除去する。これにより、チタンと反応した領域２２ａがシリサイド化され、この領域２２ａが低抵抗となる。 Further, in the resistance reduction treatment, when an impurity is diffused in the silicon oxide film 23 in order to reduce the resistance of the silicon oxide film 23, the opening is formed through the opening formed in the silicon oxide film 23 prior to the impurity diffusion. In addition, this may be achieved by diffusing impurities also in the region 22a of the semiconductor substrate 22.
Furthermore, the resistance reduction process may be a so-called salicide process. In this salicide treatment, after removing the portion of the silicon oxide film 23 facing the region 22a, titanium is sputter-deposited over the entire surface. Then, for example, by applying heat treatment of about 800 degrees twice to react titanium with silicon in the region 22a, unreacted titanium is removed with, for example, ammonia water. As a result, the region 22a reacted with titanium is silicided, and the region 22a has a low resistance.

以上のような構成によれば、親チップ１と子チップ２とを電気接続するための機能バンプＢＦの他に、親チップ１と子チップ２との電気接続に寄与しないダミーバンプＢＤが設けられているので、樹脂封止時などに親チップ１または子チップ２に作用する力を分散することができ、機械的圧力や応力歪みなどに起因する親チップ１または子チップ２の変形を防止することができる。これにより、親チップ１または子チップ２の変形に起因する素子特性の劣化を防止できる。   According to the above configuration, in addition to the functional bump BF for electrically connecting the parent chip 1 and the child chip 2, the dummy bump BD that does not contribute to the electrical connection between the parent chip 1 and the child chip 2 is provided. Therefore, it is possible to disperse the force acting on the parent chip 1 or the child chip 2 at the time of resin sealing or the like, and to prevent the deformation of the parent chip 1 or the child chip 2 due to mechanical pressure or stress distortion. Can do. Thereby, it is possible to prevent deterioration of element characteristics due to deformation of the parent chip 1 or the child chip 2.

また、ダミーバンプＢＤは電位の安定した低インピーダンス部である半導体基板２２に接続されているので、ダミーバンプＢＤから半導体装置内に外部ノイズを取り込まれるおそれがない。したがって、親チップ１および子チップ２の機能素子は、安定した素子特性を発揮することができる。
さらに、半導体基板２２のダミーバンプＢＤとの接続領域２２ａに低抵抗化処理が施されていれば、ダミーバンプＢＤから外部ノイズが取り込まれるおそれをさらになくすことができ、より安定した素子特性を発揮することができる。 Further, since the dummy bump BD is connected to the semiconductor substrate 22 which is a low impedance portion with a stable potential, there is no possibility that external noise is taken into the semiconductor device from the dummy bump BD. Therefore, the functional elements of the parent chip 1 and the child chip 2 can exhibit stable element characteristics.
Furthermore, if the resistance reduction process is applied to the connection region 22a of the semiconductor substrate 22 with the dummy bump BD, the possibility of external noise being taken in from the dummy bump BD can be further eliminated, and more stable element characteristics can be exhibited. Can do.

なお、この実施形態では、子チップ２のダミーバンプＢＤが半導体基板２２（低インピーダンス部）に接続されているが、この発明が親チップ１に適用されて、親チップ１のダミーバンプＢＤが低インピーダンス部に接続されていてもよい。また、親チップ１および子チップ２の両方のダミーバンプＢＤが、低インピーダンス部に接続されていてもよい。
さらに、親チップ１および子チップ２にそれぞれ親側バンプＢ１および子側バンプＢ２を設けているが、親チップ１または子チップ２の一方のチップのみにバンプを設けて、このバンプを他方のチップの表面に接続することによりチップ・オン・チップ接合がなされてもよい。また、親側バンプＢ１または子側バンプＢ２の一方は、バンプほど高く隆起していない金属パッドで構成されてもよい。 In this embodiment, the dummy bumps BD of the child chip 2 are connected to the semiconductor substrate 22 (low impedance part). However, the present invention is applied to the parent chip 1 and the dummy bumps BD of the parent chip 1 are low impedance parts. It may be connected to. Further, the dummy bumps BD of both the parent chip 1 and the child chip 2 may be connected to the low impedance part.
Further, although the parent-side bump B1 and the child-side bump B2 are provided on the parent chip 1 and the child chip 2, respectively, the bump is provided only on one chip of the parent chip 1 or the child chip 2, and this bump is used as the other chip. Chip-on-chip bonding may be achieved by connecting to the surface. Further, one of the parent-side bump B1 and the child-side bump B2 may be formed of a metal pad that does not rise as high as the bump.

さらには、機能バンプＢＦとダミーバンプＢＤとを同一材料で構成するとしているが、機能バンプＢＦとダミーバンプＢＤとを異なる材料で構成してもよい。この場合、ダミーバンプＢＤは、機能バンプＢＦと別の工程で形成することになる。
図３は、この発明の実施形態に係る半導体チップの要部の構成を示す断面図である。この図３において、図２に示す各部に相当する部分については、同一の参照符号を付して示すこととし、その詳細な説明を省略する。 Furthermore, although the functional bump BF and the dummy bump BD are made of the same material, the functional bump BF and the dummy bump BD may be made of different materials. In this case, the dummy bump BD is formed in a separate process from the functional bump BF.
FIG. 3 is a cross-sectional view showing the configuration of the main part of the semiconductor chip according to the embodiment of the present invention. In FIG. 3, portions corresponding to the respective portions shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

この実施形態では、シード膜３１上にダミーバンプＢＤの材料を用いたメッキを行った後、シード膜３１のダミーバンプＢＤと接触していない部分をすべて除去するのではなく、シード膜３１を選択的に残しておくことにより、ダミーバンプＢＤは、そのシード膜３１の残留部分を介して、子チップ２と子チップ２に隣接する他のチップ４との間に設けられたスクライブラインＳＣに接続されている。   In this embodiment, after plating using the material of the dummy bump BD on the seed film 31, the seed film 31 is selectively removed instead of removing all portions of the seed film 31 that are not in contact with the dummy bump BD. By leaving the dummy bump BD, the dummy bump BD is connected to a scribe line SC provided between the child chip 2 and another chip 4 adjacent to the child chip 2 through the remaining portion of the seed film 31. .

スクライブラインＳＣは、ウエハ状態の半導体基板２２から各チップを切り出す際にダイシングソーＤＳで切断するための領域であり、このスクライブラインＳＣにおいて、半導体基板２２上のシリコン酸化膜２３や表面保護膜２６は除去されており、半導体基板２２の表面は露出している。したがって、このスクライブラインＳＣとダミーバンプＢＤとが接続されるようにシード膜３１を残しておくことにより、ダミーバンプＢＤを低インピーダンス部としての半導体基板２２に接続することができる。ゆえに、この子チップ２を適用した半導体装置は、ダミーバンプＢＤから外部ノイズが取り込まれるおそれがないので、安定した素子特性を発揮することができる。   The scribe line SC is an area for cutting with a dicing saw DS when each chip is cut out from the semiconductor substrate 22 in a wafer state. In the scribe line SC, the silicon oxide film 23 and the surface protective film 26 on the semiconductor substrate 22 are cut. Is removed, and the surface of the semiconductor substrate 22 is exposed. Therefore, by leaving the seed film 31 so that the scribe line SC and the dummy bump BD are connected, the dummy bump BD can be connected to the semiconductor substrate 22 as a low impedance portion. Therefore, the semiconductor device to which the child chip 2 is applied can exhibit stable element characteristics because there is no possibility that external noise is taken in from the dummy bump BD.

なお、半導体基板２２におけるシード膜３１との接続部分に、低抵抗化処理が施されていてもよい。低抵抗化処理が施されていれば、ダミーバンプＢＤから外部ノイズが取り込まれるおそれをさらになくすことができ、より安定した素子特性を発揮することができる。
以上、この発明の実施形態について説明したが、この発明は、上述の実施形態に限定されるものではない。たとえば、上述の実施形態では、親チップ１および子チップ２は、いずれもシリコンからなるチップであるとしたが、シリコンの他にも、ガリウム砒素半導体やゲルマニウム半導体などの他の任意の半導体材料を用いた半導体チップであってもよい。この場合に、親チップ１の半導体材料と子チップ２の半導体材料は、同じでもよいし異なっていてもよい。 Note that a resistance reduction process may be performed on a connection portion of the semiconductor substrate 22 with the seed film 31. If the resistance reduction process is performed, the possibility that external noise is taken in from the dummy bumps BD can be further eliminated, and more stable element characteristics can be exhibited.
As mentioned above, although embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment. For example, in the above-described embodiment, the parent chip 1 and the child chip 2 are both chips made of silicon. However, in addition to silicon, other arbitrary semiconductor materials such as a gallium arsenide semiconductor and a germanium semiconductor are used. The semiconductor chip used may be used. In this case, the semiconductor material of the parent chip 1 and the semiconductor material of the child chip 2 may be the same or different.

その他、特許請求の範囲に記載された事項の範囲内で、種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of the matters described in the claims.

この発明の参考例に係る半導体装置の概略構成を示す図解的な断面図である。1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to a reference example of the present invention. 子チップの構成を拡大して示す断面図である。It is sectional drawing which expands and shows the structure of a child chip | tip. この発明の実施形態に係る半導体チップの要部の構成を示す断面図である。It is sectional drawing which shows the structure of the principal part of the semiconductor chip which concerns on embodiment of this invention. 従来のチップ・オン・チップ構造の問題点を説明するための図解的な断面図である。It is an illustrative sectional view for explaining problems of a conventional chip-on-chip structure.

符号の説明Explanation of symbols

１ 親チップ（半導体チップ）
２ 子チップ（半導体チップ）
１１ 表面
２１ 表面
２２ 半導体基板
３１ シード膜
ＢＤ ダミーバンプ
ＢＦ 機能バンプ
ＳＣ スクライブライン 1 Parent chip (semiconductor chip)
2 Child chip (semiconductor chip)
11 surface 21 surface 22 semiconductor substrate 31 seed film BD dummy bump BF functional bump SC scribe line

Claims (2)

半導体チップの表面に他の半導体チップの表面を対向させて接合するチップ・オン・チップ構造を有する半導体装置であって、
少なくとも一方の前記半導体チップは、
当該半導体チップの基体をなす半導体基板と、
前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に隆起した状態に設けられ、両半導体チップを所定の間隔を保った状態で支持するとともに、両半導体チップを電気的に接続するための機能バンプと、
前記絶縁膜上に隆起した状態に設けられ、両半導体チップを所定の間隔を保った状態で支持し、両半導体チップの電気接続に寄与しないダミーバンプとを備え、
前記ダミーバンプは、前記絶縁膜の表面にシード膜を積層し、このシード膜上に選択的にメッキを施すことにより形成されており、その一部が除去されることにより前記絶縁膜の表面に選択的に残された前記シード膜を介して、前記絶縁膜が除去されることにより露出した、前記半導体基板のスクライブラインに接続されていることを特徴とする、半導体装置。 A semiconductor device having a chip-on-chip structure in which the surface of another semiconductor chip is bonded to the surface of the semiconductor chip,
At least one of the semiconductor chips is
A semiconductor substrate that forms the base of the semiconductor chip; and
An insulating film formed on the semiconductor substrate;
Provided in a raised state on the insulating film , supporting both semiconductor chips in a state of maintaining a predetermined interval, and functional bumps for electrically connecting both semiconductor chips,
Provided in a raised state on the insulating film , supporting both semiconductor chips in a state of maintaining a predetermined interval, and provided with dummy bumps that do not contribute to the electrical connection of both semiconductor chips,
The dummy bump is formed by laminating a seed film on the surface of the insulating film and selectively plating on the seed film, and a part of the dummy bump is removed to select the surface of the insulating film. The semiconductor device is connected to a scribe line of the semiconductor substrate exposed by removing the insulating film through the seed film left behind . 前記半導体基板における前記ダミーバンプとの接続部分には、低抵抗化処理が施されていることを特徴とする、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein a resistance reduction process is performed on a connection portion of the semiconductor substrate with the dummy bump.
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