JP4258660B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4258660B2 JP4258660B2 JP2005090415A JP2005090415A JP4258660B2 JP 4258660 B2 JP4258660 B2 JP 4258660B2 JP 2005090415 A JP2005090415 A JP 2005090415A JP 2005090415 A JP2005090415 A JP 2005090415A JP 4258660 B2 JP4258660 B2 JP 4258660B2
- Authority
- JP
- Japan
- Prior art keywords
- stress
- wiring
- layer
- stress relaxation
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005090415A JP4258660B2 (ja) | 1997-01-17 | 2005-03-28 | 半導体装置 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991597 | 1997-01-17 | ||
| JP2005090415A JP4258660B2 (ja) | 1997-01-17 | 2005-03-28 | 半導体装置 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53270398A Division JP3811957B2 (ja) | 1997-01-17 | 1998-01-16 | 電子部品及び半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008247471A Division JP2009027185A (ja) | 1997-01-17 | 2008-09-26 | 電子部品および半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005191605A JP2005191605A (ja) | 2005-07-14 |
| JP2005191605A5 JP2005191605A5 (enExample) | 2007-03-08 |
| JP4258660B2 true JP4258660B2 (ja) | 2009-04-30 |
Family
ID=34796884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005090415A Expired - Lifetime JP4258660B2 (ja) | 1997-01-17 | 2005-03-28 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4258660B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW448524B (en) * | 1997-01-17 | 2001-08-01 | Seiko Epson Corp | Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment |
| KR100759309B1 (ko) | 2005-08-08 | 2007-09-17 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 |
| JP4235835B2 (ja) | 2005-08-08 | 2009-03-11 | セイコーエプソン株式会社 | 半導体装置 |
| JP4997848B2 (ja) * | 2006-07-04 | 2012-08-08 | Tdk株式会社 | 電子部品 |
| JP5284125B2 (ja) * | 2009-01-23 | 2013-09-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
-
2005
- 2005-03-28 JP JP2005090415A patent/JP4258660B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005191605A (ja) | 2005-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3811957B2 (ja) | 電子部品及び半導体装置 | |
| JPWO1998032170A1 (ja) | 電子部品、半導体装置、これらの製造方法、回路基板及び電子機器 | |
| US6900548B2 (en) | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument | |
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| JP3905032B2 (ja) | 半導体装置、および、その製造方法 | |
| JP4310647B2 (ja) | 半導体装置及びその製造方法 | |
| JP4258660B2 (ja) | 半導体装置 | |
| KR101009158B1 (ko) | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 | |
| JPH11220069A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
| WO1999049511A1 (en) | Semiconductor device, manufacture of semiconductor device, circuit board and electronic device |
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