JP4252602B2 - VCO drive circuit and frequency synthesizer - Google Patents

Description

  The present invention relates to a circuit for driving a VCO (Voltage Controlled Oscillator) of a frequency synthesizer. In particular, the impedance viewed from the control terminal of the VCO is lowered to prevent the VCO phase noise characteristics from being deteriorated and the VCO. The present invention relates to a VCO driving circuit that keeps a natural frequency at a constant value with respect to solid state variations and temperature changes, and a frequency synthesizer using the same.

As one of standard signal generators, there is a frequency synthesizer applying a PLL (Phase Locked Loop).
[Conventional frequency synthesizer: Fig. 15]
A conventional frequency synthesizer will be described with reference to FIG. FIG. 15 is a schematic configuration diagram of a conventional frequency synthesizer.
As shown in FIG. 15, the conventional frequency synthesizer includes an oscillator 21 that oscillates a reference frequency signal fref, a frequency divider 22 that divides the frequency signal by 1 / M, and a reference signal from the frequency divider 22. A phase comparator (PLL IC) 23 that compares the phase with the output signal from the frequency divider 27 and outputs a phase difference signal; a charge pump 24 that outputs the phase difference as a pulse width voltage; An LPF (Low Pass Filter) 25 that smoothes the output voltage from the charge pump 24, a VCO 26 that oscillates at a desired frequency by changing the frequency according to the control voltage from the LPF 25, and an output frequency from the VCO 26 is branched and input. The frequency divider 27 is basically composed of a frequency divider 27 that divides the frequency into 1 / N and outputs it to the phase comparator 23.

The phase comparator 23 is realized by a PLL IC. Further, as the frequency dividers 22 and 27, normal counters are used.
In general, a lag filter or a lag reed filter is used for the LPF 25.
The lag filter is a filter composed of a resistor R and a capacitor C.
The lag reed filter is a filter composed of two resistors R and one capacitor C.

The frequency synthesizer in FIG. 15 is a PLL oscillator that performs feedback control by detecting a phase difference with the phase comparator 23 so that the phase of the VCO 26 is constant with respect to the phase of the reference signal.
Normally, a device is configured by preparing a plurality of the above-described configurations.
As a prior art of such a frequency synthesizer, for example, there is JP-A-2004-274673 (Patent Document 1).

  Japanese Patent Application Laid-Open No. 05-90993 discloses a PLL frequency synthesizer circuit that includes two loop filters and alternately switches between them when high-speed switching of the output high-frequency signal frequency is performed (Patent Document 2).

  Japanese Patent Application Laid-Open No. 10-173521 discloses that a normal VCO is used to reduce the number of external parts and that the pull-in operation can be performed even if the oscillation frequency of the VCO shifts due to manufacturing variations. A purpose is to insert a multiplexer between the phase comparator and the loop filter, and to generate a PWM-L signal having a low duty and a PWM-H signal having a high duty based on the reference clock, and a reference clock based on the reference clock. A frequency determination circuit is provided for determining whether the frequency-divided signal frequency is within a predetermined frequency range and sending a switching signal according to the determination result to the multiplexer. If the frequency-divided signal frequency is within the predetermined range, the output of the phase comparator A PLL circuit that supplies a PWM-L signal to a loop filter if it is higher than a predetermined range and a PWM-H signal if it is lower is described. Are (Patent Document 3).

  Japanese Patent Application Laid-Open No. 11-185395 discloses that one of the inputs of a differential amplifier is designed to prevent the PLL lock from being removed due to temperature and to generate the reference voltage itself with a finer resolution than the phase error signal. Is inputted with a phase error signal of 8 bits in the phase comparator, and the reference data having a resolution of 12 bits is inputted to the other input after being modulated in the time axis direction by the data modulation circuit, and substantially 12 bits are inputted. A clock recovery PLL device that generates a control voltage based on a reference voltage having a resolution of 1 is described (Patent Document 4).

JP 2004-274673 A JP 05-90993 A Japanese Patent Laid-Open No. 10-173521 Japanese Patent Laid-Open No. 11-185395

  However, in the above conventional frequency synthesizer, when the drive circuit such as the charge pump 24 and the LPF 25 connected to the control terminal of the VCO 26 has a high impedance, the phase noise characteristics of the VCO 26 may deteriorate when the offset frequency is several kHz or less. When the VCO 26 is driven with high impedance, there is a problem in that it cannot be suppressed even when a PLL is applied.

  In this case, since the high impedance is several hundred Ω, it cannot be dealt with by a normal lag lead filter.

  The present invention has been made in view of the above circumstances, and lowers the impedance viewed from the control terminal of the VCO to prevent the deterioration of the phase noise characteristics of the VCO. An object of the present invention is to provide a VCO driving circuit and a frequency synthesizer that can maintain a constant value.

The present invention for solving the problems of the above conventional example is a VCO driving circuit for inputting a control signal to a control terminal of a voltage controlled oscillator, which outputs digital data for coarse tuning frequency and digital data for fine tuning frequency. From the control circuit to input the coarse adjustment frequency digital data and output the analog signal, the fine adjustment DAC to input the fine adjustment frequency digital data and output the analog signal, and the coarse adjustment DAC a first LPF shall be the input to the control terminal of the voltage controlled oscillator to remove noise from the output, and converts the output from the fine adjustment DAC to a voltage, a second LPF intends line smoothing signal, a resistor connecting the input stage of the input stage and the second LPF of the first LPF, the capacitor for capacitive coupling so that the output of the second LPF is added to the output of the first LPF, the second LPF Provided on the output side, it has a voltage control means for the voltage variable, the first LPF has a frequency pass characteristic of not only low frequency pass with respect to the frequency pass characteristic of the second LPF, the second LPF, characterized in Rukoto that having a frequency pass characteristic of passing to a higher frequency for frequency pass characteristic of the first LPF of.

  In the VCO driving circuit according to the present invention, the first LPF includes a resistor and a capacitor, a coil and a capacitor or a resistor, a coil and a capacitor, and the second LPF includes a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil. And the capacitor, and the value of the resistor connecting the input stage of the first LPF and the input stage of the second LPF is made larger than the sum of the values of the resistors constituting the second LPF, and voltage control is performed. The means is constituted by a variable resistor.

The present invention is a VCO driving circuit for inputting a control signal to a control terminal of a voltage controlled oscillator, a control circuit for outputting digital data for coarse adjustment frequency and digital data for fine adjustment frequency, and digital data for coarse adjustment frequency type and a DAC for rough tuning for outputting an analog signal, and inputs the digital data of the fine tuning frequency, the first LPF remove the fine-adjustment DAC that outputs an analog signal, the noise of the output from the coarse adjustment DAC for And a voltage dividing means for dividing the output voltage from the fine adjustment DAC, a resistor connecting the input stage of the first LPF and the input stage of the voltage dividing means, and the output signal from the first LPF is smoothed A third LPF that is input to the control terminal of the voltage controlled oscillator, a capacitor that is capacitively coupled so that the voltage divided by the voltage dividing means is applied to the output of the first LPF, Provided stage, have a voltage control means for the voltage variable, characterized Rukoto the first LPF is having a frequency pass characteristic of not only low frequency pass with respect to the frequency pass characteristic of the third LPF And

  In the VCO driving circuit according to the present invention, the first LPF includes a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil and a capacitor. The third LPF includes a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil. The voltage dividing means is constituted by a resistor and a variable resistor, and the value of the resistor connecting the input stage of the first LPF and the input stage of the voltage dividing means constitutes the voltage dividing means. It is characterized by being larger than the sum of the resistance values.

  According to the present invention, in the VCO driving circuit, the control circuit stores the control value of the voltage control means in the VCO driving circuit for keeping the natural frequency constant corresponding to the solid variation of the voltage controlled oscillator. The control value is supplied to the means.

The present invention provides a voltage in a VCO driving circuit that is provided in the vicinity of a voltage controlled oscillator, includes temperature measuring means for measuring temperature, and the control circuit keeps the natural frequency constant in response to a temperature change of the voltage controlled oscillator. The control value of the control means is stored, and the control value is supplied to the voltage control means with respect to the temperature value input from the temperature measuring means.

  The present invention is characterized in that, in the VCO driving circuit, the control circuit has a memory for storing a control value for keeping the natural frequency constant as a table with respect to a fluctuating temperature value.

  The present invention provides a switch for connecting or disconnecting the input stage and the output stage of the first LPF in the VCO driving circuit, and the switch is temporarily turned on when the power is turned on or when the frequency is variable. Thus, charging and discharging of a capacitor that is capacitively coupled as a connected state is performed.

  The present invention is characterized in that, in the VCO driving circuit, the switch is turned off after a specified time has elapsed to be disconnected, and the charged capacitor is discharged.

  In the frequency synthesizer, the present invention provides a voltage controlled oscillator that oscillates a desired frequency, a reference frequency oscillation circuit that oscillates a reference frequency, and a first frequency divider that divides the oscillated reference frequency by 1 / M. A second frequency divider that feeds back the output of the voltage controlled oscillator and divides the output into 1 / N, and the VCO drive circuit, and the control circuit in the VCO drive circuit is supplied from the first frequency divider. The signal and the signal from the second frequency divider are input and compared, and the digital data for the coarse adjustment frequency and the digital data for the fine adjustment frequency are output based on the difference between the two signals.

According to the present invention, a control circuit that outputs digital data for coarse adjustment frequency and digital data for fine adjustment frequency, a coarse adjustment DAC that inputs digital data for coarse adjustment frequency and outputs an analog signal, and a fine adjustment frequency digital data type and a fine adjustment DAC that outputs an analog signal, a first LPF noise output from the coarse adjustment DAC for removing shall be the input to the control terminal of the voltage controlled oscillator, the fine adjustment DAC of It converts the output voltage from the second LPF intends row smoothing the signal, a resistor connecting the input stage of an input stage and a second LPF of the first LPF, the output of first LPF a capacitor the output of the second LPF is capacitive coupling to be added to, provided on the output side of the second LPF, have a voltage control means for the voltage variable, the first LPF, the second LPF frequency communication Has a frequency pass characteristic which does not only pass low frequencies for the characteristic, the second LPF has a VCO driving circuit that having a frequency pass characteristic of passing up to a frequency higher than the frequency pass characteristic of the first LPF Therefore, the impedance viewed from the control terminal of the voltage controlled oscillator can be lowered to prevent the deterioration of the phase noise characteristic of the voltage controlled oscillator, and the natural frequency can be kept constant with respect to the VCO individual variation and temperature change. effective.

  According to the present invention, the first LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil and a capacitor, and the second LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil and a capacitor. The value of the resistor connecting the input stage of the first LPF and the input stage of the second LPF is made larger than the sum of the values of the resistors constituting the second LPF, and the voltage control means is variable Since the VCO driving circuit is composed of a resistor, there is an effect that the DC component of the voltage of the fine tuning DAC can be prevented from affecting the voltage controlled oscillator.

According to the present invention, a control circuit that outputs digital data for coarse adjustment frequency and digital data for fine adjustment frequency, a coarse adjustment DAC that inputs digital data for coarse adjustment frequency and outputs an analog signal, and a fine adjustment frequency enter the digital data, the fine-adjustment DAC that outputs an analog signal, a first LPF to eliminate noise output from the coarse adjustment DAC for a voltage divider for dividing the voltage of the output from the fine adjustment DAC A resistor that connects the input stage of the first LPF and the input stage of the voltage dividing means, and a third LPF that smoothes the output signal from the first LPF and inputs it to the control terminal of the voltage controlled oscillator a capacitor for capacitive coupling to the first voltage divided by the voltage divider to the output of the LPF is applied, it provided the voltage divider, to have a voltage control means for the voltage variable, 1st L F is, since the VCO driving circuit that having a frequency pass characteristic of not only low frequency pass with respect to the frequency pass characteristic of the third LPF, to lower the impedance as viewed from the control terminal of the voltage controlled oscillator, a voltage controlled oscillator The phase noise characteristic is prevented from deteriorating, and the natural frequency can be maintained at a constant value with respect to the solid variation of the VCO and the temperature change.

  According to the present invention, the first LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil and a capacitor, and the third LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, and a coil and a capacitor. The voltage dividing means is composed of a resistor and a variable resistor, and the value of the resistor connecting the input stage of the first LPF and the input stage of the voltage dividing means is the value of the resistance constituting the voltage dividing means. Since the VCO driving circuit is larger than the sum, there is an effect that the DC component of the voltage of the fine tuning DAC can be prevented from affecting the voltage controlled oscillator.

  According to the present invention, the control circuit stores the control value of the voltage control means in the VCO driving circuit for keeping the natural frequency constant corresponding to the solid variation of the voltage controlled oscillator or the temperature change, and the voltage control means Since the VCO driving circuit supplies the control value to the VCO, the impedance viewed from the control terminal of the voltage controlled oscillator is lowered to prevent the phase noise characteristic of the voltage controlled oscillator from deteriorating, and the VCO varies with individual variations and temperature changes. On the other hand, there is an effect that the natural frequency can be easily maintained at a constant value.

  According to the present invention, a switch for connecting or disconnecting the input stage and the output stage of the first LPF is provided, and the switch is temporarily turned on and connected when the power is turned on or when the frequency is variable. As described above, the above-mentioned VCO drive circuit that charges and discharges a capacitor to be capacitively coupled is effective in that the lock time can be shortened by instantaneously charging and discharging the capacitor that is capacitively coupled when the power is turned on or when the frequency is variable.

  According to the present invention, the switch is turned off after a specified time to be in a non-connected state, and the VCO driving circuit that discharges the charged capacitor is used. Therefore, there is an effect that normal drive control can be realized quickly.

  According to the present invention, a voltage controlled oscillator that oscillates a desired frequency, a reference frequency oscillation circuit that oscillates a reference frequency, a first frequency divider that divides the oscillated reference frequency by 1 / M, a voltage A second frequency divider that feeds back the output of the controlled oscillator and divides the frequency by 1 / N; and the VCO driving circuit, wherein the control circuit in the VCO driving circuit is configured to receive a signal from the first frequency divider, Since the signal from the second frequency divider is input and compared, and the frequency synthesizer outputs the coarse adjustment frequency digital data and the fine adjustment frequency digital data based on the difference between the two signals, the voltage controlled oscillator The impedance seen from the control terminal is lowered to prevent deterioration of the phase noise characteristics of the voltage controlled oscillator, and the natural frequency can be maintained at a constant value against the VCO individual variation and temperature change. .

Embodiments of the present invention will be described with reference to the drawings.
[Outline of the embodiment]
A VCO driving circuit according to an embodiment of the present invention is a VCO driving circuit that inputs a control signal to a control terminal of a VCO, and a control circuit that outputs digital data for a coarse tuning frequency and digital data for a fine tuning frequency; The coarse adjustment frequency digital data is input by inputting the coarse adjustment frequency digital data, the fine adjustment frequency digital data is input by inputting the fine adjustment frequency digital data, and the output noise from the coarse adjustment DAC is output. The first LPF having a frequency passing characteristic (low response speed) that passes only a low frequency and is input to the control terminal of the VCO, and the output from the fine-tuning DAC are converted into a voltage to smooth the signal. A second LPF having a frequency pass characteristic (high response speed) that allows a high frequency to pass, and an input stage of the first LPF and an input of the second LPF A resistor for connecting the stage, and a capacitor that is capacitively coupled so that the output of the second LPF is added to the output of the first LPF, and the second LPF is provided with voltage control means, The impedance seen from the control terminal of the VCO can be lowered to prevent the deterioration of the phase noise characteristics of the VCO, and the natural frequency can be maintained at a constant value with respect to the VCO solid variation and temperature change. is there.

  The VCO drive circuit according to the embodiment of the present invention is a VCO drive circuit that inputs a control signal to the control terminal of the VCO, and controls to output digital data for coarse adjustment frequency and digital data for fine adjustment frequency. The circuit, the coarse adjustment DAC for inputting the coarse adjustment frequency digital data and outputting the analog signal, the fine adjustment DAC for inputting the fine adjustment frequency digital data and outputting the analog signal, and the output from the coarse adjustment DAC A first LPF having a frequency passing characteristic (low response speed) that removes noise and passing only a low frequency, a voltage dividing unit that divides the voltage of the output from the fine-tuning DAC, and an input stage of the first LPF And a third LPF (smoothed LP) that smoothes the output signal from the first LPF and inputs it to the control terminal of the VCO. ) And a capacitor that is capacitively coupled so that the voltage divided by the voltage dividing means is applied to the output of the first LPF, and the voltage control means is provided in the voltage dividing means to control the VCO. The impedance viewed from the terminal can be lowered to prevent the deterioration of the phase noise characteristics of the VCO, and the natural frequency can be maintained at a constant value with respect to the solid variation of the VCO and the temperature change.

  The frequency synthesizer according to the embodiment of the present invention includes a VCO that oscillates a desired frequency, a reference frequency oscillation circuit that oscillates a reference frequency, and a first frequency that divides the oscillated reference frequency by 1 / M. A frequency divider, a second frequency divider that feeds back an output of the VCO, and divides the frequency to 1 / N; and the VCO drive circuit, and the control circuit in the VCO drive circuit includes the first frequency divider And the signal from the second frequency divider are input and compared, and based on the difference between the two signals, the coarse adjustment frequency digital data and the fine adjustment frequency digital data are output. Since the impedance viewed from the control terminal can be lowered, it is possible to prevent the deterioration of the VCO phase noise characteristics, and it is possible to keep the natural frequency at a constant value against the VCO solid variation and temperature change.

[Schematic configuration of frequency synthesizer: Fig. 1]
A frequency synthesizer according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic configuration diagram of a frequency synthesizer according to an embodiment of the present invention.
As shown in FIG. 1, a frequency synthesizer according to an embodiment of the present invention includes an oscillation circuit 1 that oscillates a reference frequency fref, and a frequency divider (first frequency) that divides the frequency by 1 / M. 1), the signal from the frequency divider 2 and the signal fed back from the VCO 9 and frequency-divided by 1 / N by the frequency divider 10, and the coarse adjustment data based on the difference A control circuit 3 that outputs fine adjustment data, a coarse adjustment DA converter (DAC) 4 that converts coarse adjustment data from a digital signal to an analog signal, and an LPF (first filter) that passes a low frequency signal from the coarse adjustment DAC 4 LPF) 5, a fine adjustment DA converter (DAC) 6 that converts fine adjustment data from a digital signal to an analog signal, and an LPF that passes a low frequency through the signal from the fine adjustment DAC 6 LPF) 7, a synthesizer 8 that synthesizes signals from both LPFs 5, 7, a voltage controlled oscillator (VCO) 9 that oscillates based on the voltage of the signal from synthesizer 8, and an output from VCO 9 is branched. And a frequency divider (second frequency divider) 10 that divides the frequency into 1 / N and outputs the result to the control circuit 3.

The control circuit 3 is configured by an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or the like, and outputs frequency data for coarse adjustment to the coarse adjustment DAC 4. An operation of outputting frequency data for adjustment to the fine-tuning DAC 6 is performed.
In other words, the frequency is coarsely set by the frequency data for coarse adjustment, and the frequency is finely set by the frequency data for fine adjustment, and the control voltage of the VCO 9 is quickly adjusted by synthesizing the fine adjustment frequency voltage with the coarse adjustment frequency voltage. is doing.

Here, the control circuit 3, coarse adjustment DAC4, LPF5, fine adjustment DAC6, LPF7, and synthesizer 8 constitute a VCO drive circuit, and the coarse adjustment DAC4 roughly outputs a VCO output frequency voltage (coarse adjustment frequency), The fine tuning DAC 6 outputs the fine tuning frequency voltage, and the synthesizer 8 synthesizes the fine tuning voltage with the coarse tuning voltage, thereby adjusting the coarse tuning frequency voltage with the fine tuning frequency voltage, and the adjusted control voltage is Input to the VCO 9.
That is, the entire PLL is composed of the fine tuning DAC 6, the LPF 7, and the synthesizer 8.

[Specific Configuration of VCO Drive Circuit (First VCO Drive Circuit): FIG. 2]
Next, a specific configuration of the VCO driving circuit will be described with reference to FIG. FIG. 2 is a configuration diagram of the VCO drive circuit according to the first embodiment of the present invention.
As shown in FIG. 2, the VCO drive circuit (first VCO drive circuit) according to the first embodiment of the present invention receives digital data of coarse adjustment frequency from the control circuit 3 and the control circuit 3. Pulse width modulation (PWM: Pulse Width Modulation) is input with coarse adjustment DAC 4 to be converted into analog data, operational amplifier 11 for amplifying the output from coarse adjustment DAC 4 several times, and fine adjustment frequency digital data from control circuit 3. ) A pulse width modulation circuit (PWM) 12, a fine adjustment DAC 6 that converts digital data from the pulse width modulation circuit 12 into analog data, an LPF 5 that smoothes the output from the operational amplifier 11, and an output from the fine adjustment DAC 6 And a synthesizing means for combining the coarse adjustment frequency voltage and the fine adjustment frequency voltage and outputting them to the VCO 9, the resistor R and the capacitor C. It is constituted by.

  Specifically, the synthesizing means will be described. When the output from the operational amplifier 11 is a coarse adjustment line and the output from the fine adjustment DAC 6 is a fine adjustment line, resistors R5 and LPF5 are connected in series to the coarse adjustment line. Input to the control terminal of the VCO 9.

  Further, the LPF 7 and the variable resistor R4 are connected in series to the fine adjustment system line, and the end of the variable resistor R4 is grounded.

  The coarse adjustment line and the fine adjustment line are connected via a resistor R6 between a point between the resistor R5 and the LPF5 and a point between the DAC 6 for fine adjustment and the LPF7, and further between the LPF5 and the VCO9. The point and the point between the LPF 7 and the variable resistor R4 are coupled via a capacitor C8.

  The variable resistor R4 is a resistor that can be varied by a digital signal such as a digital potentiometer. The variable resistance value of the variable resistor R4 is controlled by the control circuit 3. The variable resistor R4 is a voltage control means because it controls the voltage by changing the value of the variable resistor.

The first VCO driving circuit has a current output type output from the fine tuning DAC 6. That is, the coarse adjustment line is voltage driven, but the fine adjustment line has a configuration in which the fine adjustment frequency is adjusted by the output current from the fine adjustment DAC 6.
The output from the coarse adjustment DAC 4 provides a voltage for determining a rough VCO output frequency to the control terminal of the VCO 9.

  As the PLL, the voltage for controlling the VCO 9 is the current of the PWM signal from the fine tuning DAC 6, and this PWM signal is smoothed by the LPF 7 and coupled to the output from the coarse tuning DAC 4 amplified by the operational amplifier 11 by the capacitor C 8. Are added and applied to the control terminal of the VCO 9.

  The LPF may be an RC filter that is a combination of a resistor R and a capacitor C, an LC filter that is a combination of a coil L and a capacitor C, and a filter that is a combination of a resistor R, a coil L, and a capacitor C. .

Due to the DC component of the output of the fine adjustment DAC 6, the voltage V1 at the output stage of the fine adjustment DAC 6 = (resistance value of LPF7 + R4) I (current) and the voltage V2 at the input stage of the variable resistor R4 = R4I.
In order to prevent the DC component of the fine tuning DAC 6 from affecting the DC component of the input stage of the VCO 9, the output from the fine tuning DAC 6 is connected to the output from the coarse tuning DAC 4 via the resistor R6. At this time, as a condition of each resistor, (LPF7 resistance value + R4) << R6. By making the resistance R6 very large compared to the resistance value + R4 of the LPF 7, the DC component of the fine tuning DAC 6 does not affect the DC component of the coarse tuning DAC 4.

Since the resistor R6 is connected, the coarse voltage applied to the VCO control terminal is divided by the resistance values of the resistors R5, R6 and LPF7 from the output voltage from the operational amplifier 11, but the value of the resistor R6 is Since it is large, it becomes {R6 / (R5 + R6)} V (voltage).
The resistance value of the LPF 7 is a resistor for converting the output of the fine tuning DAC 6 into a voltage, and operates as an LPF that smoothes the PWM signal by adding a capacitor C of the LPF 7.

  Since the noise of the voltage applied to the VCO control terminal causes a spurious (unnecessary wave) to the output of the VCO 9, the LPF 5 has a frequency that allows only a low frequency to pass in order to remove the noise of the output of the coarse adjustment DAC 4. It is an LPF (rough tuning LPF) with a large time constant having pass characteristics (slow response speed). On the other hand, the LPF 7 and the variable resistor R4 are low-pass LPFs (fine tuning LPFs) having a frequency passing characteristic (fast response speed) that allows a high frequency to pass.

Since the control voltage range of the wideband VCO 9 is about 0 to 20 V and may be higher than the power supply voltage of the DAC, amplification by the operational amplifier 11 requires the LPF having a large time constant described above.
Since the operational amplifier 11 is used to amplify the voltage, it may not be used when the control voltage of the VCO 9 is low.

  In the first VCO driving circuit, since the impedance viewed from the control terminal of the VCO is determined by the capacitor C8 and the variable resistor R4, the impedance can be lowered by reducing the variable resistor R4. Here, by setting the variable resistor R4 to several tens, the impedance can be reduced and the deterioration of the phase noise characteristic of the VCO can be prevented.

Next, the variable resistor R4, which is a characteristic part of the first VCO drive circuit, will be specifically described.
The VF sensitivity Kv of the VCO 9 may vary due to individual variations of the VCO 9 and the like. The variable resistor R4 is adapted to keep the VF sensitivity as seen from the VCO 9 constant so that the natural frequency fn when the PLL is applied is kept constant.
The resistance value (control value) of the variable resistor R4 is controlled from the control circuit 3 according to the solid variation of the VCO 9 and the temperature change. The resistance value to be controlled is set so that the VF sensitivity of the VCO 9 is measured by experiment and the VF sensitivity is constant.

[Second VCO drive circuit: FIG. 3]
Further, a VCO driving circuit according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a configuration diagram of a VCO drive circuit according to the second embodiment of the present invention.
The VCO drive circuit (second VCO drive circuit) according to the second embodiment of the present invention is basically the same as the first VCO drive circuit as shown in FIG. A temperature sensor 14 connected to the VCO 9 is provided, and the temperature sensor 14 is provided in the vicinity of the VCO 9.
In the second VCO drive circuit, the temperature is measured by the temperature sensor, and the measured temperature value is output to the control circuit 3 as digital data. The temperature sensor 14 can be referred to as a temperature measuring unit.

  In the VCO 9, the VF sensitivity Kv of the VCO 9 may fluctuate due to temperature changes. As in FIG. 2, the variable resistor R4 is adjusted so as to keep the VF sensitivity as seen from the fine tuning DAC 6 constant so that the natural frequency fn when the PLL is applied is kept constant.

[Relationship between variable resistance R4 and VF sensitivity: Fig. 4]
Next, an example in which the VF sensitivity viewed from the output of the fine adjustment DAC 6 is made variable by making the variable resistor R4 variable will be described with reference to FIG. FIG. 4 is a diagram showing the relationship between the variable resistor R4 and the VF sensitivity.
In FIG. 4, for example, assuming that the VF sensitivity Kv of the VCO 9 is 30 MHz / V at room temperature and the output (1) of the fine tuning DAC 6 is controlled at 0 to 0.8 V, the first example [ 1], when the resistance value of the LPF 7 is 10 and the variable resistor R4 is 10, and the output of the fine tuning DAC 6 is controlled to 0 V, the voltage (2) applied to the capacitor C8 side terminal of the variable resistor R4 becomes 0 V. When the output of the fine tuning DAC 6 is controlled to 0.8V, the voltage (2) is assumed to be 0.2V.

  Therefore, the amount of change in the VCO frequency is VF sensitivity Kv voltage (2) = 30 MHz / V0.2 V = 6.0 MHz. Further, the VF sensitivity viewed from the output of the fine adjustment DAC 6 is 30 MHz / V (0.2 V / 0.8 V) = 7.5 MHz / V.

  In the second example [2], when the resistance value of the LPF 7 is set to 10 and the variable resistor R4 is set to 5, the voltage applied to the capacitor C8 side terminal of the variable resistor R4 when the output of the fine tuning DAC 6 is controlled to 0V. (2) is 0 V, and it is assumed that the voltage (2) becomes 0.11 V when the output of the fine tuning DAC 6 is controlled to 0.8 V.

  Therefore, the amount of change in the VCO frequency is VF sensitivity Kv voltage (2) = 30 MHz / V0.11 V = 3.3 MHz. Further, the VF sensitivity viewed from the output of the fine adjustment DAC 6 is 30 MHz / V (0.11 V / 0.8 V) ≈4.1 MHz / V.

[Relationship between VF sensitivity and R4 resistance against temperature: Fig. 5]
Based on the above characteristics, a control method in the second VCO driving circuit will be described with reference to FIG. FIG. 5 is a graph showing the relationship between the VF sensitivity and the R4 resistance value with respect to temperature.
As shown in FIG. 5, as the temperature rises, the actual VF sensitivity of the VCO 9 decreases. On the other hand, by gradually increasing the resistance value of the variable resistor R4 corresponding to the temperature rise, the VF sensitivity viewed from the fine adjustment DAC 6 can be made constant. As a result, the PLL natural frequency fn can also be maintained at a constant value.

  That is, the temperature characteristic of the VF sensitivity Kv of the VCO 9 is measured and grasped in advance, and an appropriate R4 corresponding to the VF sensitivity with respect to the temperature is stored in a memory (for example, a ROM table) provided in the control circuit 3. The relationship between the resistance values) is stored as data, and the control circuit 3 searches the memory so that the VF sensitivity viewed from the VCO 9 becomes the target VF sensitivity from the temperature detected by the temperature sensor 14. Read the appropriate resistance value and set the resistance value (control value) of the variable resistor R4.

[VCO phase noise characteristics: Fig. 6]
FIG. 6 shows the phase noise characteristics of the VCO in the first and second VCO drive circuits. FIG. 6 is a diagram showing the phase noise characteristics of the VCO. In FIG. 6, the horizontal axis indicates the offset frequency (detuning frequency), and the vertical axis indicates the phase noise. The characteristics are different when the voltage sensitivity is low and when the voltage sensitivity is high.

[VCO phase noise characteristics with temperature: Fig. 7 and Fig. 8]
FIG. 7 shows the phase noise characteristics of the VCO when the temperature is low, and FIG. 8 shows the phase noise characteristics of the VCO when the temperature is high.
For example, if the natural frequency is 30 kHz at room temperature (25 ° C.), as shown in FIG. 7, the natural frequency is 18 kHz when the temperature is high, and the temperature is low when the temperature is low. As shown in FIG. 8, the natural frequency is 40 kHz. 7 and 8, the horizontal axis represents the offset frequency and the vertical axis represents the phase noise.

  According to the first VCO drive circuit, by adjusting the solid variation of the VCO 9 with the variable resistor R4, the VF sensitivity seen from the VCO 9 can be made constant, and the PLL natural frequency fn can be kept at a constant value. .

  According to the second VCO drive circuit, by adjusting the temperature change of the VCO 9 with the variable resistor R4, the VF sensitivity seen from the VCO 9 can be made constant, and the PLL natural frequency fn can be kept constant. .

Note that a VCO driving circuit in which the first VCO driving circuit and the second VCO driving circuit are integrated may be used.
In addition, by using a synthesizer including the first VCO drive circuit and the second VCO drive circuit, the PLL natural frequency fn can be maintained at a constant value, and there is an effect that stability can be ensured.

[Third VCO drive circuit: FIG. 9]
Next, a VCO drive circuit (third VCO drive circuit) according to a third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a configuration diagram of a VCO drive circuit according to the third embodiment of the present invention.
As shown in FIG. 9, the third VCO driving circuit includes a switch 13 that connects the point between the resistor R5 and the LPF5 and the point between the LPF5 and the VCO9 with respect to the first VCO driving circuit. The switch 13 is opened and closed under the control of the control circuit 3.

  When the switch 13 is opened, the two points are not connected, and the capacitor C8 is charged with the charge via the LPF 5. When the switch 13 is closed, the two points are connected, and the resistor R5 The subsequent voltage is applied to the input side of the VCO 9, and the charge is instantaneously accumulated in the capacitor C8.

By providing the switch 13 and turning it on (closed) instantaneously (several μsec) at the initial stage of voltage application to the VCO 9, the response time can be shortened.
This is because the output of the coarse adjustment DAC 4 is an LPF having a large time constant, and the lock time is delayed. Therefore, the switch 13 is provided to shorten the lock time.

[Fourth VCO Drive Circuit: FIG. 10]
Next, a VCO driving circuit (fourth VCO driving circuit) according to a fourth embodiment of the invention will be described with reference to FIG. FIG. 10 is a configuration diagram of a VCO drive circuit according to the fourth embodiment of the present invention.
As shown in FIG. 10, the fourth VCO driving circuit includes a switch 13 that connects a point between the resistor R5 and the LPF5 and a point between the LPF5 and the VCO9 with respect to the second VCO driving circuit. The switch 13 is opened and closed under the control of the control circuit 3.
The operation of the switch 13 is the same as that described in the third VCO drive circuit.

[Fifth VCO drive circuit: FIG. 11]
Next, a VCO drive circuit (fifth VCO drive circuit) according to a fifth embodiment of the invention will be described with reference to FIG. FIG. 11 is a configuration diagram of a VCO driving circuit according to the fifth embodiment of the present invention.
In the fifth VCO drive circuit, as shown in FIG. 11, a coarse adjustment DAC 4, an operational amplifier 11, resistors R 1, LPF 5, and LPF 15 are connected in series to a coarse adjustment line output from the control circuit 3. Is input to the control terminal.

One end of a capacitor C3 is connected between LPF5 and LPF15, and the other end is grounded via a variable resistor R4.
The LPF may be an RC filter that is a combination of a resistor R and a capacitor C, an LC filter that is a combination of a coil L and a capacitor C, and a filter that is a combination of a resistor R, a coil L, and a capacitor C. .

A PWM 12, a fine tuning DAC 6, a resistor R5, and a variable resistor R4 are connected in series to the fine adjustment line output from the control circuit 3, and the end of the variable resistor R4 is grounded.
The point (3) between the resistor R1 and the LPF 5 of the coarse adjustment line and the point (1) between the fine adjustment DAC 6 and the resistor R5 of the fine adjustment line are connected via the resistor R6.
The point (4) between the LPF5 and LPF15 of the coarse adjustment line and the point (2) between the resistance R5 and the variable resistance R4 of the fine adjustment line are coupled via a capacitor C3.

  The fifth VCO drive circuit is configured when the output of the fine tuning DAC 6 is a voltage output type. That is, the coarse adjustment line is voltage driven, and the fine adjustment line is also operated by voltage drive. The basic operation principle is the same as that of the current output type in the first VCO driving circuit.

In the fifth VCO drive circuit, the output of the coarse adjustment DAC 4 determines a rough VCO output frequency, and the PWM signal of the output of the fine adjustment DAC 6 controls the PLL.
The PWM signal output from the fine adjustment DAC 6 is added to the output of the coarse adjustment DAC 4 by the capacitor C3.
The resistor R6 is connected so that the DC component (1) of the fine adjustment DAC 6 in the fine adjustment line does not affect the coarse adjustment line (4). In particular, the influence is reduced by sufficiently increasing the value of the resistor R6 as compared with the value of the resistor R5 + variable resistor R4.
The LPF 15 is an LPF (third LPF) for smoothing the PWM signal.
The resistors R1 and LPF5 are LPFs having a large time constant for removing noise from the output of the coarse adjustment DAC 4.

[Sixth VCO drive circuit: FIG. 12]
Next, a VCO driving circuit (sixth VCO driving circuit) according to a sixth embodiment of the invention will be described with reference to FIG. FIG. 12 is a configuration diagram of a VCO drive circuit according to the sixth embodiment of the present invention.
As shown in FIG. 12, the sixth VCO driving circuit has a point (3) between the resistors R1 and LPF5 and a point (4) between the LPF5 and LPF15 with respect to the fifth VCO driving circuit. Is connected to the switch 13, and the switch 13 is opened and closed under the control of the control circuit 3.
The operation of the switch 13 is the same as that described in the third VCO drive circuit.

[Seventh VCO drive circuit: FIG. 13]
Next, a VCO driving circuit (seventh VCO driving circuit) according to a seventh embodiment of the present invention will be described with reference to FIG. FIG. 13 is a configuration diagram of a VCO driving circuit according to the seventh embodiment of the present invention.
As shown in FIG. 13, the seventh VCO drive circuit is similar to the second VCO drive circuit in that the temperature sensor 14 is connected to the control circuit 3 to the fifth VCO drive circuit. A memory for storing the relationship between the VF sensitivity with respect to the temperature and the appropriate R4 resistance value as data is provided so that the VF sensitivity viewed from the fine adjustment DAC 6 becomes the target VF sensitivity from the temperature detected by the temperature sensor 14. Further, the control circuit 3 searches the memory, reads the appropriate resistance value, and sets the resistance value (control value) of the variable resistor R4.

[Eighth VCO drive circuit: FIG. 14]
Next, a VCO drive circuit (eighth VCO drive circuit) according to an eighth embodiment of the invention will be described with reference to FIG. FIG. 14 is a configuration diagram of a VCO drive circuit according to the eighth embodiment of the present invention.
As shown in FIG. 14, the eighth VCO drive circuit connects the temperature sensor 14 to the control circuit 3 and controls the sixth VCO drive circuit in the same manner as the second and seventh VCO drive circuits. The circuit 3 is provided with a memory for storing the relationship between the VF sensitivity with respect to the temperature and an appropriate R4 resistance value as data, and the VF sensitivity viewed from the fine adjustment DAC 6 from the temperature detected by the temperature sensor 14 is the target VF sensitivity. Thus, the control circuit 3 searches the memory, reads the corresponding appropriate resistance value, and sets the resistance value (control value) of the variable resistor R4.

  The present invention lowers the impedance viewed from the control terminal of the VCO to prevent the deterioration of the phase noise characteristics of the VCO, and can maintain the natural frequency at a constant value with respect to the solid variation of the VCO and the temperature change. Suitable for circuits and frequency synthesizers.

1 is a schematic configuration diagram of a frequency synthesizer according to an embodiment of the present invention. 1 is a configuration diagram of a VCO drive circuit according to a first embodiment of the present invention. FIG. It is a block diagram of the VCO drive circuit based on the 2nd Embodiment of this invention. It is a figure which shows the relationship between variable resistance R4 and VF sensitivity. It is a figure which shows the relationship of VF sensitivity with respect to temperature, and R4 resistance value. It is a figure which shows the phase noise characteristic of VCO. It is a figure which shows the phase noise characteristic of VCO when temperature is low. It is a figure which shows the phase noise characteristic of VCO in case temperature is high. It is a block diagram of the VCO drive circuit based on the 3rd Embodiment of this invention. It is a block diagram of the VCO drive circuit based on the 4th Embodiment of this invention. It is a block diagram of the VCO drive circuit based on the 5th Embodiment of this invention. It is a block diagram of the VCO drive circuit based on the 6th Embodiment of this invention. It is a block diagram of the VCO drive circuit based on the 7th Embodiment of this invention. It is a block diagram of the VCO drive circuit based on the 8th Embodiment of this invention. It is a schematic block diagram of the conventional frequency synthesizer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Oscillation circuit, 2 ... Frequency divider, 3 ... Control circuit, 4 ... Coarse adjustment DAC, 5 ... LPF, 6 ... Fine adjustment DAC, 7 ... LPF, 8 ... Synthesizer, 9 ... Voltage controlled oscillator (VCO), DESCRIPTION OF SYMBOLS 10 ... Frequency divider, 11 ... Operational amplifier, 12 ... Pulse width modulation circuit (PWM), 13 ... Switch, 14 ... Temperature sensor, 15 ... LPF, 21 ... Oscillator, 22 ... Frequency divider, 23 ... Phase comparator (PLL) IC), 24 ... charge pump, 25 ... LPF, 26 ... VCO, 27 ... frequency divider,

Claims (10)

A VCO driving circuit for inputting a control signal to a control terminal of a voltage controlled oscillator,
A control circuit that outputs digital data for coarse tuning frequency and fine tuning frequency;
Coarse adjustment DAC that inputs digital data of coarse adjustment frequency and outputs analog signal;
A fine-tuning DAC that inputs digital data of a fine-tuning frequency and outputs an analog signal;
A first LPF shall be the input of removing the noise of the output from the DAC for the coarse adjustment to the control terminal of the voltage controlled oscillator,
Converts the output from the fine adjustment DAC to a voltage, a second LPF intends line smoothing signal,
A resistor connecting the input stage of the first LPF and the input stage of the second LPF;
A capacitor capacitively coupled so that the output of the second LPF is added to the output of the first LPF;
Provided on the output side of the second LPF, it has a voltage control means for the voltage variable,
The first LPF has a frequency pass characteristic that allows only a low frequency to pass through the frequency pass characteristic of the second LPF,
The second LPF is, VCO driving circuit according to claim Rukoto that having a frequency pass characteristic of passing up to a frequency higher than the frequency pass characteristic of the first LPF. The first LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, a coil and a capacitor,
The second LPF includes a resistor and a capacitor, a coil and a capacitor or a resistor, a coil and a capacitor,
The resistance value connecting the input stage of the first LPF and the input stage of the second LPF is made larger than the sum of the resistance values constituting the second LPF,
2. The VCO drive circuit according to claim 1, wherein the voltage control means is composed of a variable resistor. A VCO driving circuit for inputting a control signal to a control terminal of a voltage controlled oscillator,
A control circuit that outputs digital data for coarse tuning frequency and fine tuning frequency;
Coarse adjustment DAC that inputs digital data of coarse adjustment frequency and outputs analog signal;
A fine-tuning DAC that inputs digital data of a fine-tuning frequency and outputs an analog signal;
A first LPF to eliminate noise output from the coarse tuning DAC,
Voltage dividing means for dividing the voltage of the output from the fine adjustment DAC;
A resistor connecting the input stage of the first LPF and the input stage of the voltage dividing means;
A third LPF that smoothes the output signal from the first LPF and inputs it to the control terminal of the voltage controlled oscillator;
A capacitor that is capacitively coupled so that the voltage divided by the voltage dividing means is applied to the output of the first LPF;
Provided in the voltage divider, to have a voltage control means for the voltage variable,
The first LPF is, VCO driving circuit according to claim Rukoto that having a third frequency pass characteristics not lower frequencies only passed against frequency pass characteristics of the LPF. The first LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, a coil and a capacitor,
The third LPF is composed of a resistor and a capacitor, a coil and a capacitor or a resistor, a coil and a capacitor,
The voltage dividing means is composed of a resistor and a variable resistor,
4. The resistance value connecting the input stage of the first LPF and the input stage of the voltage dividing means is larger than the sum of the resistance values constituting the voltage dividing means. VCO drive circuit.   The control circuit stores the control value of the voltage control means in the VCO driving circuit for keeping the natural frequency constant corresponding to the solid variation of the voltage controlled oscillator, and supplies the control value to the voltage control means The VCO driving circuit according to claim 1, wherein: Provided in the vicinity of the voltage-controlled oscillator , provided with a temperature measuring means for measuring the temperature,
The control circuit stores the control value of the voltage control means in the VCO driving circuit for keeping the natural frequency constant corresponding to the temperature change of the voltage controlled oscillator, and the temperature value input from the temperature measuring means 5. The VCO drive circuit according to claim 1, wherein the control value is supplied to the voltage control means.   7. The VCO drive circuit according to claim 6, wherein the control circuit has a memory for storing a control value for keeping the natural frequency constant with respect to the fluctuating temperature value as a table. A switch for connecting or disconnecting the input stage and the output stage of the first LPF;
8. The VCO drive circuit according to claim 1, wherein when the power is turned on or when the frequency is changed, the switch temporarily turns on and charges and discharges a capacitor that is capacitively coupled as a connected state. 9.   9. The VCO driving circuit according to claim 8, wherein the switch is turned off after a specified time to be disconnected to discharge the charged capacitor. A voltage controlled oscillator that oscillates at a desired frequency;
A reference frequency oscillation circuit for oscillating a reference frequency;
A first divider for dividing the oscillated reference frequency by 1 / M;
A second frequency divider that feeds back the output of the voltage controlled oscillator and divides the frequency by 1 / N;
A VCO driving circuit according to any one of claims 1 to 9,
The control circuit in the VCO drive circuit inputs and compares the signal from the first frequency divider and the signal from the second frequency divider, and compares the digital data of the coarse adjustment frequency based on the difference between the two signals. And a frequency synthesizer that outputs digital data of a fine tuning frequency.

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