CN117691993A - Frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and adjusting method - Google Patents

Frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and adjusting method Download PDF

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Publication number
CN117691993A
CN117691993A CN202311776358.9A CN202311776358A CN117691993A CN 117691993 A CN117691993 A CN 117691993A CN 202311776358 A CN202311776358 A CN 202311776358A CN 117691993 A CN117691993 A CN 117691993A
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China
Prior art keywords
frequency
voltage
controlled oscillator
output
input end
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CN202311776358.9A
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Chinese (zh)
Inventor
王玺
张航
张红升
徐璐
刘程卓
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Chongqing University of Post and Telecommunications
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Chongqing University of Post and Telecommunications
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Priority to CN202311776358.9A priority Critical patent/CN117691993A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention relates to a frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and an adjusting method, and belongs to the field of radio frequency integrated circuit design. The circuit comprises a phase frequency detector, a charge pump, a voltage controlled oscillator, a loop filter, a frequency divider, a counting unit, a comparing unit and a digital state machine. The phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the frequency divider are sequentially connected, the output end of the frequency divider is connected with the input end of the phase frequency detector, and a switch T2 is arranged between the output end of the loop filter and the input end of the voltage-controlled oscillator; the input end of the comparison unit is connected with the output end of the loop filter through a switch T1, and the output end of the comparison unit is connected with the input end of the digital state machine; the input end of the counting unit is respectively connected with the reference frequency and the feedback frequency output by the frequency divider, and the output end of the counting unit is connected with the input end of the digital state machine through a switch T3; the output end of the digital state machine is connected with the input end of the voltage-controlled oscillator, and simultaneously controls the capacitor array and the current array of the voltage-controlled oscillator.

Description

Frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and adjusting method
Technical Field
The invention belongs to the field of radio frequency integrated circuit design, and relates to a frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and an adjusting method.
Background
A Phase-Locked Loop (PLL) is a frequency synthesizer, which is mainly a negative feedback control system that can generate a target frequency. The phase-locked loop has a plurality of functions and can be mainly applied to frequency synthesis and exchange of frequency multiplication and frequency division; some high frequency output signals may be generated as a frequency synthesizer. In recent years, it has been widely used even in biophysics, hydrodynamics, meteorology, atomic physics, oceanography, and the like. Phase locked loops are also being developed towards higher accuracy and performance as a very important module inside the present Soc chip.
With the development of integrated circuits and the demand of higher precision and higher performance of clock frequency in chips, the application of phase-locked loops is increasing, and phase-locked loops have high-frequency phase-locked synthesis and good noise characteristics, so that the phase-locked loops become a mainstream technical means of high-frequency synthesis in the market. A Voltage Controlled Oscillator (VCO) is a core device of a phase locked loop, which determines the output frequency range of the phase locked loop, adjusts the output frequency of the phase locked loop by changing the VCO's own parameters, and in the case of different sub-bands, the amplitude changes with frequency due to the change of its own coefficients. Second, the VCO output may change somewhat during operation with changing conditions, such as temperature changes, device aging, and a number of non-ideal factors. When the variation is small, the phase-locked loop can still work in the current sub-band, but in the case of large environmental variation, the phase-locked loop may need to replace the sub-band, especially in the case of low phase noise required nowadays, as the value of Kvco is lower and lower, the number of sub-bands is higher and higher, and in the case of external environmental variation, the frequency jump is easier to be caused, so how to reasonably adjust the output frequency of the voltage-controlled oscillator is also a problem.
Disclosure of Invention
In view of the above, the present invention aims to provide a voltage-controlled oscillator circuit and an adjusting method for synchronous and adaptive frequency and amplitude, wherein the amplitude can be adaptively changed along with the frequency, so as to realize synchronous and adaptive change of the frequency and the amplitude; and the circuit reasonably adjusts the output frequency of the voltage-controlled oscillator by adopting the same group of digital state machines in an open-loop rough adjustment state and a closed-loop fine adjustment state.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the first scheme is a frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit, which comprises a phase frequency detector, a charge pump, a voltage-controlled oscillator, a loop filter, a frequency divider, a counting unit, a comparing unit and a digital state machine. The output end of the frequency divider is also connected with the input end of the phase frequency detector, and a switch T2 is arranged between the output end of the loop filter and the input end of the voltage-controlled oscillator; the input end of the comparison unit is connected with the output end of the loop filter through a single-pole double-throw switch T1, and the output end of the comparison unit is connected with the input end of the digital state machine; the input end of the counting unit is respectively connected with the reference frequency and the feedback frequency output by the frequency divider, and the output end of the counting unit is connected with the input end of the digital state machine through a switch T3; the output end of the digital state machine is connected with the input end of the voltage-controlled oscillator.
The voltage-controlled oscillator comprises a VCO core circuit, a capacitor array unit and a current array unit. The output end of the digital state machine is respectively connected with the capacitor array unit and the current array unit, and the capacitor array unit and the current array unit are respectively connected with the VCO core circuit.
The output amplitude of the voltage-controlled oscillator is changed by selecting a sub-band of the voltage-controlled oscillator controlled by the capacitor array unit and controlling the tail current of the voltage-controlled oscillator by the current array unit, and the capacitor array unit and the current array unit are simultaneously controlled by adopting control signals output by the same group of digital state machines, so that synchronous self-adaption of frequency and amplitude is realized.
Optionally, the comparing unit includes adjustable resistors R1 and R2, a resistor R3, and comparators COMP1 and COMP2; wherein the adjustable resistor R1, the resistor R3 and the adjustable resistor R2 are connected in sequence, and the adjustable resistor R1 is connected with a power supply V DD The adjustable resistor R2 is grounded; the non-inverting input end of the comparator COMP1 is connected between the adjustable resistor R2 and the resistor R3; the inverting input end of the comparator COMP2 is connected between the adjustable resistor R1 and the resistor R3; both the inverting input terminal of COMP1 and the non-inverting input terminal of COMP2 are connected to the voltage signal Vctrl output by the loop filter. The reference voltage values of the two comparators can be changed by adjusting the resistance values of the adjustable resistors R1 and R2, specifically, R1 can change the voltage value VH of the inverting input terminal of the comparator COMP2, and R2 can change the voltage value VL of the non-inverting input terminal of the comparator COMP 1.
Optionally, the counting unit includes two counters, a first counter input end of the two counters is connected to a reference frequency Fref, a second counter input end of the two counters is connected to a feedback frequency Ffb of the frequency divider, and output ends of the first counter and the second counter are connected to the digital state machine through a switch T3. Both counters have CRL zero clearing position, when one counter is full, the counter automatically returns to the initial counting value, and a signal is output to enable the other counter to be cleared back to the initial counting value.
Optionally, a fixed end of the single-pole double-throw switch T1 is connected to an input end of the voltage-controlled oscillator, and a movable end of the single-pole double-throw switch T1 is connected to the power supply VDD and an input end of the comparing unit, respectively.
According to the scheme II, the frequency output by a VCO core circuit in a voltage-controlled oscillator enters a target frequency sub-band range through open-loop coarse adjustment, and then the most suitable sub-band in the target frequency sub-band range is selected through closed-loop fine adjustment; the same digital state machine is used for both the open-loop coarse tuning and the closed-loop fine tuning stages, and the state change of the digital state machine can be applied to both tuning stages.
In the open-loop rough adjustment stage, comparing the feedback frequency Ffb of the frequency divider with the reference frequency Fref through the counting unit, and outputting a signal to enable the digital state machine to be in a state of-1 if Fref > Ffb, so that the capacitance array unit and the current array unit in the voltage-controlled oscillator reduce the capacitance and the current source connected into the VCO core circuit; if Fref < Ffb, entering a closed loop fine tuning stage;
in the closed loop fine tuning stage, comparing the magnitude of a voltage signal Vctrl output by a loop filter with preset voltage values VH and VL by a comparison unit, and outputting a signal to enable a digital state machine to be in a state-1 if Vctrl is more than VH so as to increase Ffb; if Vctrl < VL, then the output signal causes the digital state machine state +1, thereby causing Ffb to decrease; if VL < Vctrl < VH, the adjustment process ends.
When the open-loop rough adjustment stage starts, the single-pole double-throw switch T1 is connected to the power supply VDD, the switch T2 is opened, the switch T3 is closed, and the initial digits of the digital state machine are all 1; when the closed loop fine tuning stage is entered, the loop filter outputs a voltage signal Vctrl to the comparing unit through the single pole double throw switch T1, the switch T2 is closed, and the switch T3 is opened.
The initial digits of the digital state machine are all 1, which can be expressed as 11 … 11, +1 and-1 are carried out according to the input, and when the input signal-1 is detected, the input signal-1 is changed from 11 … to 11 … 10; when the input signal +1 is detected, it is changed from 11 … 11 to 00 … 00, and so on. The capacitor array and the current array are controlled by the same group of control signals K < N:0> from the digital state machine, the switches of the capacitor array and the current array correspond to the signals of the digital state machine, and the corresponding switches are simultaneously opened and closed. For example, the switch of the 11 … digital state machine corresponding to the capacitor array and the current array is all closed, and all the capacitors and current sources in the capacitor array and the current array are connected into the VCO core circuit; the 00 … of the digital state machine corresponds to all the switches of the capacitor array and the current array being open; 10 … of the digital state machine is closed for K1 and Kn of the capacitor array and the current array, and the others are all open.
The invention has the beneficial effects that: the frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit provided by the invention performs proper sub-band coarse selection through an open-loop coarse tuning stage; the closed loop fine tuning stage makes finer adjustments and always detects whether the output frequency is in the appropriate sub-band and the two states share a digital state machine. Closed loop fine tuning can automatically adjust the sub-band according to the variation of non-ideal factors, namely has frequency self-adaptability; meanwhile, the output amplitude is changed along with the change of the sub-frequency band in a synchronous and self-adaptive mode, and therefore the power consumption of the voltage-controlled oscillator can be reduced under the condition that the proper output amplitude is ensured.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the specification.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
fig. 1 shows a voltage-controlled oscillator circuit with synchronous adaptive frequency and amplitude according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of sub-bands;
FIG. 3 is a digital state machine flow diagram;
fig. 4 is a diagram of the VCO core circuit configuration;
FIG. 5 is a simplified diagram of a capacitor array structure;
FIG. 6 is a schematic diagram of a capacitor array structure;
FIG. 7 is a schematic diagram of a current array structure;
FIG. 8 is a schematic diagram of a counting unit;
FIG. 9 is a schematic diagram of a comparison unit;
fig. 10 is a schematic diagram of a circuit operation flow.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to limit the invention; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc., that indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or suggesting that the referred device or element must have a specific azimuth, be constructed and operated in a specific azimuth, so that the terms describing the positional relationship in the drawings are merely for exemplary illustration and should not be construed as limiting the present invention, and that the specific meaning of the above terms may be understood by those of ordinary skill in the art according to the specific circumstances.
As shown in fig. 1, an embodiment of the present invention provides a frequency and amplitude synchronous adaptive voltage controlled oscillator circuit, which includes a Phase Frequency Detector (PFD), a Charge Pump (CP), a Voltage Controlled Oscillator (VCO), a loop filter (LPF), a frequency divider, a counting unit, a comparing unit, and a digital state machine. The voltage-controlled oscillator is composed of a capacitor array unit, a current array unit and a VCO core circuit, the sub-band of the voltage-controlled oscillator is controlled by selecting the capacitor array unit, and the tail current of the voltage-controlled oscillator is controlled by selecting the current array unit. The whole circuit works in two stages of open-loop coarse adjustment and closed-loop fine adjustment, and in the open-loop stage, a voltage-controlled oscillator, a frequency divider, a counting unit and a digital state machine are taken as main circuits, so that target frequency enters a sub-band range; in the closed loop phase, the phase frequency discriminator, the charge pump, the voltage controlled oscillator, the loop filter, the frequency divider, the comparing unit and the digital state machine are used as main circuits, and the phase-locked loop enters the working phase to be finely adjusted.
The comparison unit is shown in fig. 9, and comprises adjustable resistors R1 and R2, a resistor R3, a comparator 1 and a comparator 2; wherein the adjustable resistor R1, the resistor R3 and the adjustable resistor R2 are connected in sequence, and the adjustable resistor R1 is connected with a power supply V DD The adjustable resistor R2 is grounded; the non-inverting input end of the comparator 1 is connected between the adjustable resistor R2 and the resistor R3; the inverting input end of the comparator 2 is connected between the adjustable resistor R1 and the resistor R3; the inverting input of the comparator 1 and the non-inverting input of the comparator 2 are both connected to the voltage signal Vctrl output by the loop filter. The reference voltage values of the two comparators can be changed by adjusting the resistance values of the adjustable resistors R1 and R2, specifically, R1 can change the voltage value VH of the inverting input terminal of the comparator 2, and R2 can change the voltage value VL of the non-inverting input terminal of the comparator 1.
The counting unit is shown in fig. 8, and comprises two counters, wherein the input end of the counter 1 is connected with the reference frequency Fref, the input end of the counter 2 is connected with the feedback frequency Ffb of the frequency divider, and the output ends of the counter 1 and the counter 2 are connected with the digital state machine through a switch T3. Both counters have CRL zero clearing position, when one counter is full, the counter automatically returns to the initial counting value, and a signal is output to enable the other counter to be cleared back to the initial counting value.
The voltage controlled oscillator includes a VCO core circuit (shown in fig. 4), a capacitor array unit (shown in fig. 5 and 6), and a current array unit (shown in fig. 7). The capacitor array unit and the current array unit are respectively connected with the VCO core circuit, the sub-band of the voltage-controlled oscillator is controlled by selecting the capacitor array unit, and the tail current of the voltage-controlled oscillator is controlled by selecting the current array unit.
Closed loop fine tuning requires the phase locked loop to be changed after each settling, which takes much time and frequency control time. T (T) afc For adaptive frequency control time, T lock For PLL loop after each adjustment of sub-bandN is the number of subband adjustments. The sub-band is changed every time a new output is generated by the digital state machine, the PLL undergoes a lock process, and the total time spent is:
T afc ＝T lock ·N
the digital state machine is not only used in the open-loop coarse tuning stage, but also used in the closed-loop fine tuning stage, but the digital state machine of the dichotomy cannot directly jump to adjacent sub-bands at some positions and does not accord with the running change of a closed-loop fine tuning circuit, so the invention does not adopt the dichotomy to accelerate the open-loop coarse tuning stage.
The output amplitude of the voltage controlled oscillator, which is proportional to the bias tail current and the equivalent parallel resistance, can be expressed as:
V OUT ＝I SS ·R P
wherein I is SS The tail current of the voltage-controlled oscillator is represented, and the value of the tail current is mirrored by the current array. R is R P The parallel resistance is equivalent to VCO, and R P And QwL, wherein Q is the quality factor of the resonant circuit, w is the output angular frequency, and L is the magnitude of the inductance. The inductance L generally cannot be changed after the circuit is manufactured, w is the corresponding output angular vibration frequency, Q is determined by the inductance and the capacitance together and increases with the increase of w, so R P As the oscillation frequency increases, the amplitude of the output increases continuously during the increase of the VCO output frequency, resulting in a fixed I SS At the output voltage V OUT Continuously reducing or even causing the circuit to fail to start vibrating. But the tail current may be selectively adjusted to compensate for the magnitude of the output amplitude with the output frequency decreasing.
The voltage-controlled oscillator circuit proposed in this embodiment has two operating states, an open-loop coarse tuning stage and a closed-loop fine tuning stage.
The open loop coarse tuning is to make the frequency output by the VCO enter the target frequency sub-band range to make a pad for the fine tuning later, and save the fine tuning time. Adjusting the output frequency of the voltage-controlled oscillator can be achieved by changing the size of the inductor, the size of the capacitor or the number of connected capacitor arrays, but the inductor cannot be changed after being manufactured in the manufacturing process, so that coarse adjustment can be achieved only by changing the connection amount of the capacitor arrays. When the feedback frequency is larger than the reference frequency, the rough adjustment is completed, and the counter 2 counts before the counter 1. In order to ensure that the target frequency is counted in the corresponding sub-bands at the same time, the counter 2 and the counter 1 reflect the magnitude of the feedback frequency, the counter 1 reflects the magnitude of the reference frequency, and when the feedback frequency is larger than the reference frequency, the target frequency can be considered to be located in the sub-band where the reference frequency is located, and generally, the target frequency has corresponding points in a plurality of sub-bands, so that the optimal sub-band is selected in a fine adjustment stage. After a proper sub-band is selected, the Q value of the whole voltage-controlled oscillator is changed due to the addition of the capacitor array, the more the capacitor array is opened, the more the Q value is severely reduced, the voltage-controlled oscillator cannot vibrate or the amplitude is too small, and the gm value of the cross coupling tube can be increased by changing the Q value of the inductor, so that the tail current is increased. However, the cross-coupled tube and inductance are generally fixed and cannot be changed during the manufacturing process, and only the magnitude of the tail current can be adjusted to change the amplitude of the VCO output.
After the coarse tuning is finished, the fine tuning stage is started, one most suitable frequency band is selected from a series of frequency sub-bands comprising target frequencies, whether the selected frequency sub-band is the most suitable frequency sub-band can be judged through the Vctrl, and in the most suitable frequency sub-band, vctrl is arranged in the middle part of the frequency sub-band, and even if the frequency is changed in the middle, the Vctrl cannot jump to the upper frequency band and the lower frequency band to cause larger change of output. If Vctrl is at a boundary position, it may cause the phase locked loop to fluctuate under some non-ideal factors, resulting in the selected frequency band no longer including the target frequency, and thus resulting in loss of lock.
The specific adjustment process is shown in fig. 10, and includes:
first a certain point is ensured where the target frequency is between the maximum and minimum output frequencies of the designed VCO.
An open-loop rough adjustment stage:
first, the T1 switch in FIG. 1 is turned on to the 0 terminal to connect VDD, T3 is in the closed state, T2In the open state. The digital state machine is in a state of 11 … 11, the digital state machine 11 … controls the capacitor array to be all connected with the VCO circuit, the current array is all opened, the circuit Q is the minimum, the VCO tail current is in the maximum state, the output frequency of the VCO is in the maximum value corresponding to the sub-band 11 … 11, and the output amplitude V is obtained OUT ＝I SS ·R P ，I SS At maximum, R P At a minimum, the output amplitude tends to be constant.
If Fref > Ffb in the counting unit, it is stated that the output frequency of the voltage controlled oscillator is smaller than the target frequency, which is not within this sub-band, fref represents the reference frequency and Ffb represents the feedback frequency from the frequency divider. In the same time, the counter 1 is fully charged before the counter 2, a potential signal is output to reset the counter 2 to the initial state, meanwhile, the potential signal is input to the digital state machine-1 end, the digital state machine is changed from 11 … to 11 …, the lowest bit of the output control capacitor array is not connected to the voltage-controlled oscillator, one branch with the smallest current array is controlled to be disconnected, and the counter 1 automatically returns to the initial state after being fully charged. Wherein the digital state machine digital change is shown in figure 3.
If Fref < Ffb in the counting unit, it indicates that the output frequency of the voltage controlled oscillator is greater than the target frequency, the target frequency is within this sub-band. In the same time, the counter 2 is fully charged before the counter 1, a potential signal is output to reset the counter 1 to the initial state, the counter 2 automatically returns to the initial state after being fully charged, at the moment, the T1 switch is turned to the 1 end to enable the comparison unit to collect the loop filter, the T2 is closed, the T3 is opened, and at the moment, the phase-locked loop enters a closed loop fine adjustment stage.
If fref=ffb, this indicates that the output frequency at this time is equal to the target frequency, which is at the edge of this sub-band. In the same time, the counter 2 and the counter 1 should be fully charged together theoretically, but due to the phase difference problem, there is still a problem of being fully charged in sequence, and the circuit returns to the two cases, so that no influence is caused. At this time, vctrl has a corresponding position at the edge of this subband, and in the case of Fref > Ffb, it is shifted to the next subband; in the case of Fref < Ffb, the phase locked loop enters a closed loop fine tuning phase where there is also a change in adjacent sub-bands.
Closed loop fine tuning stage:
the T1 switch is switched to the 1 end, the loop filter is collected through the comparison unit, the T2 is closed, the T3 is opened, and the sub-band is temporarily fixed in a certain frequency band. The phase-locked loop works in a closed loop, the phase frequency detector controls the charge pump switch under the influence of the reference frequency and the target frequency, the current output by the charge pump passes through the loop filter to generate Vctrl, the Vctrl is compared with VH and VL of the comparison unit, the VH and VL can be adjusted through an adjustable voltage reference, and the VH is kept to be more than VL.
If Vctrl > VH, this indicates that Vctrl is now relatively close to the upper edge portion of this sub-band. As indicated by point a in fig. 2. At this time, the output of the comparator 1 is low level, the output of the comparator 2 is high level, the output level of the comparator 2 controls the digital state machine-1, the sub-band is changed by changing the access condition of the capacitor array, and meanwhile, the magnitude of the current array is changed to keep the output amplitude unchanged, at this time, the Vctrl is at the point A2, the VCO output frequency is greater than the target frequency, and the charge pump starts to discharge until the Vctrl reaches the A3 locking state.
If Vctrl < VL, this indicates that Vctrl is now relatively close to the lower edge portion of this sub-band. As shown at point B in fig. 2. At this time, the output of the comparator 1 is high level, the output of the comparator 2 is low level, the output level of the comparator 1 controls the digital state machine +1, the sub-band is changed by changing the connection condition of the capacitor array, and meanwhile, the magnitude of the current array is changed to keep the output amplitude unchanged, at this time, the Vctrl is at the point B2, the VCO output frequency is smaller than the target frequency, and the charge pump starts to charge until the Vctrl reaches the B2 locking state.
If VL < Vctrl < VH, it is stated that Vctrl is now in the middle part of this subband, as indicated by point C in fig. 2. At this time, the output of the comparator 1 is low, the output of the comparator 2 is low, the digital state machine is kept unchanged, the Vctrl is in a proper state, which indicates that the sub-band is the most proper sub-band, the sub-band does not need to be changed, the capacitor array and the current array are kept unchanged, and the phase-locked loop is locked.
During the locking operation, even if severe variations in non-ideal factors are encountered, resulting in no corresponding output frequency on the current sub-band, the circuit will re-lock to the target frequency position and maintain stable output amplitude after a period of self-adjustment due to the self-adaptation of the circuit.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.

Claims (6)

1. A frequency and amplitude synchronous adaptive voltage controlled oscillator circuit characterized by: the circuit comprises a phase frequency detector, a charge pump, a voltage controlled oscillator, a loop filter, a frequency divider, a counting unit, a comparing unit and a digital state machine; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the frequency divider are sequentially connected, wherein the output end of the frequency divider is also connected with the input end of the phase frequency detector, and a switch T2 is arranged between the output end of the loop filter and the input end of the voltage-controlled oscillator; the input end of the comparison unit is connected with the output end of the loop filter through a single-pole double-throw switch T1, and the output end of the comparison unit is connected with the input end of the digital state machine; the input end of the counting unit is respectively connected with the reference frequency and the feedback frequency output by the frequency divider, and the output end of the counting unit is connected with the input end of the digital state machine through a switch T3;
the voltage-controlled oscillator comprises a VCO core circuit, a capacitor array unit and a current array unit; the output end of the digital state machine is respectively connected with the capacitor array unit and the current array unit, and the capacitor array unit and the current array unit are respectively connected with the VCO core circuit; the sub-band of the voltage-controlled oscillator is controlled by selecting the capacitor array unit, and the output amplitude of the voltage-controlled oscillator is changed by selecting the tail current of the voltage-controlled oscillator controlled by the current array unit; the capacitor array unit and the current array unit are controlled simultaneously by adopting control signals output by the same group of digital state machines, so that synchronous self-adaption of frequency and amplitude is realized.
2. The voltage controlled oscillator circuit of claim 1, wherein: the comparison unit comprises adjustable resistors R1 and R2, a resistor R3 and comparators COMP1 and COMP2; wherein the adjustable resistor R1, the resistor R3 and the adjustable resistor R2 are connected in sequence, and the adjustable resistor R1 is connected with a power supply V DD The adjustable resistor R2 is grounded; the non-inverting input end of the comparator COMP1 is connected between the adjustable resistor R2 and the resistor R3; the inverting input end of the comparator COMP2 is connected between the adjustable resistor R1 and the resistor R3; both the inverting input terminal of COMP1 and the non-inverting input terminal of COMP2 are connected to the voltage signal Vctrl output by the loop filter.
3. The voltage controlled oscillator circuit of claim 1, wherein: the counting unit comprises two counters, wherein the input end of a first counter is connected with reference frequency Fref, the input end of a second counter is connected with feedback frequency Ffb of the frequency divider, and the output ends of the first counter and the second counter are connected with the digital state machine through a switch T3.
4. The voltage controlled oscillator circuit of claim 1, wherein: the fixed end of the single-pole double-throw switch T1 is connected with the input end of the voltage-controlled oscillator, and the movable end of the single-pole double-throw switch T1 is respectively connected with the power supply VDD and the input end of the comparison unit.
5. The frequency and amplitude synchronous self-adaptive adjustment method based on the voltage-controlled oscillator circuit as claimed in any one of claims 1 to 4, characterized in that: the method comprises the steps of enabling the frequency output by a VCO core circuit in a voltage-controlled oscillator to enter a target frequency sub-band range through open-loop coarse adjustment, and selecting the most suitable sub-band in the target frequency sub-band range through closed-loop fine adjustment; the same digital state machine is used in both the open-loop coarse adjustment phase and the closed-loop fine adjustment phase, and the state change of the digital state machine can be applied to the two adjustment phases;
in the open-loop rough adjustment stage, comparing the feedback frequency Ffb of the frequency divider with the reference frequency Fref through the counting unit, and outputting a signal to enable the digital state machine to be in a state of-1 if Fref > Ffb, so that the capacitance array unit and the current array unit in the voltage-controlled oscillator reduce the capacitance and the current source connected into the VCO core circuit; if Fref < Ffb, entering a closed loop fine tuning stage;
in the closed loop fine tuning stage, comparing the magnitude of the voltage signal Vctrl output by the loop filter with the magnitude of the reference voltages VH and VL by a comparison unit, and outputting a signal to enable a digital state machine to be in a state of-1 if Vctrl > VH so as to increase Ffb; if Vctrl < VL, then the output signal causes the digital state machine state +1, thereby causing Ffb to decrease; if VL < Vctrl < VH, the adjustment process ends.
6. The adjustment method according to claim 5, characterized in that: when the open-loop rough adjustment stage starts, a single-pole double-throw switch T1 is connected to a power supply VDD, a switch T2 is opened, a switch T3 is closed, the initial digits of a digital state machine are all 1, and a capacitor array unit and a current array unit in a voltage-controlled oscillator are connected to a VCO circuit; when the closed loop fine tuning stage is entered, the loop filter outputs a voltage signal Vctrl to the comparing unit through a single pole double throw switch T1, the switch T2 is closed, and the switch T3 is opened.
CN202311776358.9A 2023-12-21 2023-12-21 Frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and adjusting method Pending CN117691993A (en)

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CN202311776358.9A CN117691993A (en) 2023-12-21 2023-12-21 Frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and adjusting method

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CN202311776358.9A CN117691993A (en) 2023-12-21 2023-12-21 Frequency and amplitude synchronous self-adaptive voltage-controlled oscillator circuit and adjusting method

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