JP4248658B2 - Fuse trimming circuit - Google Patents

Fuse trimming circuit Download PDF

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Publication number
JP4248658B2
JP4248658B2 JP03482599A JP3482599A JP4248658B2 JP 4248658 B2 JP4248658 B2 JP 4248658B2 JP 03482599 A JP03482599 A JP 03482599A JP 3482599 A JP3482599 A JP 3482599A JP 4248658 B2 JP4248658 B2 JP 4248658B2
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Prior art keywords
resistor
fuse
nmos transistor
voltage
protective
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JP03482599A
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JP2000236022A (en
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成人 井上
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Seiko Instruments Inc
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Seiko Instruments Inc
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Description

【0001】
【発明の属する技術分野】
本発明は、LCDコントローラICのように、発振回路等の合わせ込みを必要とするICのフューズトリミング回路に関するものである。
【0002】
【従来の技術】
第2図に従来技術のフューズトリミング回路を示す。入力回路7のゲート電極のレベルを決めるために、フューズ抵抗2とプルアップトランジスタ8を基本的な構成要素として、静電破壊からインバータを守るための保護抵抗3と保護用NMOSトランジスタから構成されていた。この時に保護用NMOSトランジスタ4のゲート電極は接地線5に繋がれていた。
【0003】
フューズトリミング回路に於いては、トリミングしたいパッド端子に電圧を印加することにより多結晶シリコンなどからなるフューズ抵抗に電流が流れ
抵抗*電流*電流
で表されるパワーに比例して発生する熱によりフューズ抵抗を溶断しトリミングしていた。
【0004】
【発明が解決しようとする問題点】
ICの微細化が進むにつれてゲート酸化膜が薄くなり、ゲート酸化膜の耐圧は下がって来ている。例えば100オングストロームの酸化膜の場合には10Vで10MV/cmもの電界が掛かっている。熱酸化膜の真性破壊電界は約11MV/cmくらいであるので、11Vもかかると素子の破壊をきたす。また真性破壊電界まで達しなくても高い電界がかかる程トンネル電流が流れる為にゲート酸化膜へのダメージが増し信頼性上問題であった。また静電気が印加された時に電流を流すための保護素子であるNMOSトランジスタ4のドレイン耐圧はゲート酸化膜の薄膜化につれて下がるが、その下がり方は緩やかであるので、NMOSトランジスタ4が静電気を逃がす前にインバータ7のゲート酸化膜に高い電界がかかり破壊してしまっていた。
【0005】
保護素子であるNMOSトランジスタが電流を流す過程には、ドレインのアバランシェ降伏とソース、基板、ドレイン間のバイポーラ動作がある。NMOSトランジスタのゲート電極を接地した場合には、初めにドレインのアバランシェ降伏、次にアバランシェ降伏にて発生する基板電流をトリガーにしてソース、基板、ドレイン間のバイポーラ動作が起こり大電流を流す。バイポーラ動作時にはNMOSトランジスタのドレインには低い電圧しかかからないが、バイポーラ動作に入る前のドレインのアバランシェ降伏は通常12―17Vである為、その電圧が入力回路のゲート酸化膜にかかってしまっていた。
【0006】
【課題を解決するための手段】
本発明においてもパワーに比例して発生する熱によりフューズ抵抗を溶断するが、保護素子であるNMOSトランジスタのゲート電極の電位を接地するのではなく、フューズ抵抗と電圧分割するための抵抗を直列に配置し、NMOSトランジスタのゲート電極の電位がドレインと接地線の中間電位となるようにした。
【0007】
そこで、パッド端子にかかる電圧を電圧分割したものがNMOSトランジスタのゲート電圧として供給されるために、チャネルホットキャリアにより基板電流が増えアバランシェ降伏に入らなくてもソース、基板、ドレイン間のバイポーラ動作に入り大電流が流れるようにした。これによりドレインに高い電圧がかからなくなり、しいては入力回路7のゲート酸化膜にも高い電界がかからない。またフューズ抵抗の溶断後にはNMOSトランジスタのゲート電圧は接地線に固定されるので、このNMOSトランジスタはノーマリオフの状態になる。
【0008】
【発明の実施の形態】
(実施例1)
第1図に本発明の実施例を示す。実施例ではP型基板上に設けられたフューズトリミング回路を示している。トリミング用のパッド端子1と多結晶シリコンからなるフューズ抵抗2と保護抵抗3と電流を流すための保護素子として働くNMOSトランジスタ4とNMOSトランジスタのゲート電極にパッド端子1の電位と接地線5の中間電位がかかるようにする分割抵抗6と入力回路7のレベルを決めるためのプルアップトランジスタ8からなる。以下に各要素について述べる。
【0009】
ここでは入力回路7がインバータである場合について述べる。
多結晶シリコンからなるフューズ抵抗2のトータルの抵抗値は100Ωくらいであるが、第4図(a)のように電流が集中し発熱しやすいようにくびれた形状が好ましい。
NMOSトランジスタをバイポーラ動作に入れるためのトリガーになる基板電流はドレイン構造によっても異なるが、ゲート電圧がドレイン電圧の1/2〜1/4くらいの時に最も大きくなるので、多結晶シリコンからなる分割抵抗6は100Ω以下良い。この時分割抵抗6は第4図(b)のように電流が集中するような形状は避ける。ここでは分割抵抗6よりもフューズ抵抗2の方が電流集中し易く、溶断し易くなっていれば良い。
【0010】
本実施例では分割抵抗6、フューズ抵抗2の材質は多結晶シリコンについて説明したが、WSi等のシリサイド膜と多結晶シリコン膜の積層膜でも良いし、金属膜でも構わない。
護抵抗3は1kΩ程度で良い。保護素子として働くNMOSトランジスタ4はトランジスタの幅が400um程度、チャネル長は1.0umくらいが目安となるが、これらのサイズはトランジスタがバイポーラ動作した状態で200mAくらいの電流を駆動できる能力があり、破壊に至らなければ良い。
【0011】
次にトリミング(フューズ抵抗を切断)するときの動作について説明する。
パッド端子1に電圧を印加するとフューズ抵抗2と分割抵抗6を介して接地線に電流が流れる。通常は50〜100msecの電圧パルスが印加される。NMOSトランジスタ4はゲート電極の電位がパッド端子の電圧と接地線5の電圧の抵抗分割比で決まる中間電位になり、チャネルホットキャリアによる基板電流を発生しバイポーラ動作に入る。このバイポーラ動作への入る過程を第3図に示す。第3図中のA点がスナップバック電圧に入る電圧、B点がバイポーラ動作に入った後の電圧を示している。第3図のカーブ▲1▼、▲2▼、▲3▼はフューズ抵抗2と分割抵抗6の抵抗比を変えた場合 を表している。▲1▼は分割抵抗6が無い場合でNMOSトランジスタでは14―17Vとなる。分割抵抗6の値を大きくすると▲2▼から▲3▼の方向へカーブが移動し、A点のスナップバック電圧が小さくなる。この時B点の電圧は殆ど変わらない。
【0012】
フューズ抵抗2の切断後にはNMOSトランジスタのゲート電極は接地線に固定されるが、NMOSトランジスタは既にバイポーラ動作に入っているのでバイポーラ動作はパッド端子7に印加されるパルスが終わるまで続く。入力回路7のゲート酸化膜には保護用NMOSトランジスタがバイポーラ動作に入る前に、最も高い電圧がかかるが、A点のスナップバック電圧以下であり、バイポーラ動作に入っているときにはほぼB点の電圧に固定される。このA点のスナップバック電圧はフューズ抵抗2と分割抵抗6の抵抗比によって制御できるので、入力回路7のゲート酸化膜の厚みに応じてゲート酸化膜に影響を与えないような電圧となるようにA点を選べばよい。フューズ抵抗2が切断された後はプルアップトランジスタ8によって入力回路7のゲートのレベルが決まり、電源線9の電位、つまりHighに固定される。
【0013】
次にフューズ抵抗2を切断しない場合について述べる。保護抵抗3とフューズ抵抗2と分割抵抗6の和とプルアップトランジスタ8の駆動能力の引っ張り合いにより入力回路7のゲートのレベルが決まるが、入力回路7のゲートのレベルはLowに固定されるようにプルアップトランジスタ8のサイズ、及び保護抵抗3とフューズ抵抗2と分割抵抗6の和が決められなければならない。またフューズ抵抗2を切断しない場合には保護用NMOSトランジスタ4のゲート電極には電源線9の電圧をプルアップトランジスタ8のオン抵抗、保護抵抗3、フューズ抵抗2、分割抵抗6の比で分割して電圧がかかるが、分割抵抗6は小さいので保護用NMOSトランジスタ4のリーク電流非常に小さい。イオン注入により保護用NMOSトランジスタ4のしきい値が上がるようにすれば、よりリーク電流を小さくできる。
(実施例2)
第5図に本発明の別の実施例を示す。実施例1に対して、プルアップトランジスタ8の代わりに入力回路の出力を固定するためのトランジスタ12と入力回路の出力の初期値を決めるためのトランジスタ13が付加された構成となっている。
【0014】
実施例1ではフューズ2を切断しない場合にはプルアップトランジスタ8はノーマリオンになっているために、フューズ抵抗2、分割抵抗6を介して電源線9と接地線5の間に電流が流れるが、本実施例ではフューズ2を切断しない場合に入力回路7であるインバータの入力がLowに固定される為に入力回路の出力を固定するためのトランジスタ13はオフとなり電源線9と接地線5の間に電流が流れず消費電流を増加させずに済む。またこの時保護用NMOSトランジスタ4のゲートも接地線と同電位となるために、保護用NMOSトランジスタ4のリーク電流の心配も無い。
【0015】
【発明の効果】
本発明によれば、ICの微細化によりゲート酸化膜が薄くなっても、ゲート酸化膜に高い電界がかからないフューズトリミング回路を構成できる。本発明ではP型半導体基板上のフューズトリミング回路について述べたが、無論N型基板であっても構わない。
【図面の簡単な説明】
【図1】本発明の実施例を示した回路図である。
【図2】従来技術の回路図。
【図3】フューズトリミング時にNMOSトランジスタに流れる電流−電圧のフューズ抵抗と分割抵抗の抵抗比依存を示すための図である。
【図4】フューズ抵抗と分割抵抗の平面図を示している。
【図5】本発明の別の実施例を示した回路図である。
【符号の説明】
1 パッド端子
2 フューズ抵抗
3 保護抵抗
4 保護用NMOSトランジスタ
5 接地線
6 分割抵抗
7 入力回路
8 プルアップトランジスタ
9 電源線
10 多結晶シリコン
11 コンタクト
12 入力回路の出力を固定するためのトランジスタ
13 入力回路の出力の初期値を決めるトランジスタ
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fuse trimming circuit of an IC that requires adjustment of an oscillation circuit or the like, such as an LCD controller IC.
[0002]
[Prior art]
FIG. 2 shows a conventional fuse trimming circuit. In order to determine the level of the gate electrode of the input circuit 7, the fuse resistor 2 and the pull-up transistor 8 are used as basic components, and the protection resistor 3 and the protection NMOS transistor are provided to protect the inverter from electrostatic breakdown. It was. At this time, the gate electrode of the protective NMOS transistor 4 was connected to the ground line 5.
[0003]
In a fuse trimming circuit, a current flows through a fuse resistor made of polycrystalline silicon or the like by applying a voltage to a pad terminal to be trimmed, and the fuse is generated by heat generated in proportion to the power represented by resistance * current * current. The resistor was melted and trimmed.
[0004]
[Problems to be solved by the invention]
As IC miniaturization progresses, the gate oxide film becomes thinner and the breakdown voltage of the gate oxide film is decreasing. For example, in the case of a 100 Å oxide film, an electric field of 10 MV / cm is applied at 10V. Since the intrinsic breakdown electric field of the thermal oxide film is about 11 MV / cm, if 11 V is applied, the element is destroyed. Even if the electric field does not reach the intrinsic breakdown electric field, the tunnel current flows as a high electric field is applied, which increases the damage to the gate oxide film, which is a problem in reliability. Further, the drain breakdown voltage of the NMOS transistor 4 which is a protection element for allowing a current to flow when static electricity is applied decreases as the gate oxide film becomes thinner. However, since the decrease is gentle, before the NMOS transistor 4 releases static electricity. In addition, a high electric field is applied to the gate oxide film of the inverter 7 to destroy it.
[0005]
In the process in which the NMOS transistor as the protective element passes a current, there are avalanche breakdown of the drain and a bipolar operation between the source, the substrate, and the drain. When the gate electrode of the NMOS transistor is grounded, a bipolar operation occurs between the source, the substrate, and the drain by using the substrate current generated by the avalanche breakdown of the drain first and then the avalanche breakdown as a trigger, and a large current flows. During the bipolar operation, only a low voltage is applied to the drain of the NMOS transistor, but since the avalanche breakdown of the drain before the bipolar operation is normally 12-17 V, the voltage is applied to the gate oxide film of the input circuit.
[0006]
[Means for Solving the Problems]
In the present invention, the fuse resistor is blown by heat generated in proportion to the power, but the potential of the gate electrode of the NMOS transistor as the protective element is not grounded, but the fuse resistor and the resistor for voltage division are connected in series. The gate electrode potential of the NMOS transistor is set to an intermediate potential between the drain and the ground line.
[0007]
Therefore, since the voltage applied to the pad terminal is divided and supplied as the gate voltage of the NMOS transistor, the substrate current increases due to channel hot carriers, and the bipolar operation between the source, the substrate, and the drain can be performed without causing an avalanche breakdown. A large current was made to flow. As a result, no high voltage is applied to the drain, and no high electric field is applied to the gate oxide film of the input circuit 7. Further, after the fuse resistor is blown, the gate voltage of the NMOS transistor is fixed to the ground line, so that the NMOS transistor is normally off.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
FIG. 1 shows an embodiment of the present invention. In the embodiment, a fuse trimming circuit provided on a P-type substrate is shown. Fuse resistor 2 and the coercive Mamoru抵 anti 3 and NMOS transistor 4 and the ground line 5 and the potential of the pad terminal 1 to the gate electrode of the NMOS transistor acting current as a protective element for the flow of the pad terminal 1 for trimming of polycrystalline silicon And a pull-up transistor 8 for determining the level of the input circuit 7. Each element is described below.
[0009]
Here, a case where the input circuit 7 is an inverter will be described.
The total resistance value of the fuse resistor 2 made of polycrystalline silicon is about 100Ω. However, as shown in FIG. 4A, a constricted shape is preferred so that current is concentrated and heat is easily generated.
The substrate current that triggers the NMOS transistor to enter the bipolar operation differs depending on the drain structure, but it is the highest when the gate voltage is about 1/2 to 1/4 of the drain voltage. 6 the following is a good 100Ω. The time-sharing resistor 6 avoids a shape in which current concentrates as shown in FIG. 4 (b). Here, it is sufficient that the fuse resistor 2 is more likely to concentrate the current and more easily melt than the divided resistor 6.
[0010]
In this embodiment, the material of the dividing resistor 6 and the fuse resistor 2 has been described with respect to polycrystalline silicon. However, a laminated film of a silicide film such as WSi and a polycrystalline silicon film or a metal film may be used.
Coercive Mamoru抵 anti-3 may be about 1kΩ. The NMOS transistor 4 that acts as a protection element has a width of about 400 um and a channel length of about 1.0 um, but these sizes are capable of driving a current of about 200 mA in a state where the transistor is in a bipolar operation, and is destroyed. It is good if it does not reach.
[0011]
Next, the operation when trimming (cutting the fuse resistor) will be described.
When a voltage is applied to the pad terminal 1, a current flows through the ground line via the fuse resistor 2 and the dividing resistor 6. Usually, a voltage pulse of 50 to 100 msec is applied. In the NMOS transistor 4, the potential of the gate electrode becomes an intermediate potential determined by the resistance division ratio of the voltage of the pad terminal and the voltage of the ground line 5, generates a substrate current due to channel hot carriers, and enters a bipolar operation. The process of entering the bipolar operation is shown in FIG. The point A in FIG. 3 shows the voltage that enters the snapback voltage, and the point B shows the voltage after entering the bipolar operation. Curves (1), (2), and (3) in FIG. 3 represent cases where the resistance ratio of the fuse resistor 2 and the dividing resistor 6 is changed. (1) is 14-17 V in the case of the NMOS transistor when there is no dividing resistor 6. When the value of the dividing resistor 6 is increased, the curve moves from (2) to (3), and the snapback voltage at the point A is decreased. At this time, the voltage at point B hardly changes.
[0012]
After the fuse resistor 2 is disconnected, the gate electrode of the NMOS transistor is fixed to the ground line. However, since the NMOS transistor has already entered the bipolar operation, the bipolar operation continues until the pulse applied to the pad terminal 7 ends. The highest voltage is applied to the gate oxide film of the input circuit 7 before the protective NMOS transistor enters the bipolar operation. However, the voltage is lower than the snapback voltage at the point A and is almost the voltage at the point B when the bipolar operation is started. Fixed to. Since the snapback voltage at point A can be controlled by the resistance ratio of the fuse resistor 2 and the dividing resistor 6, the voltage does not affect the gate oxide film according to the thickness of the gate oxide film of the input circuit 7. Select A point. After the fuse resistor 2 is cut, the level of the gate of the input circuit 7 is determined by the pull-up transistor 8 and is fixed to the potential of the power supply line 9, that is, High.
[0013]
Next, the case where the fuse resistor 2 is not cut will be described. The gate level of the input circuit 7 is determined by the sum of the protective resistor 3, the fuse resistor 2 and the dividing resistor 6 and the pulling of the drive capability of the pull-up transistor 8, but the gate level of the input circuit 7 is fixed to Low. In addition, the size of the pull-up transistor 8 and the sum of the protective resistor 3, the fuse resistor 2, and the dividing resistor 6 must be determined. When the fuse resistor 2 is not cut, the voltage of the power supply line 9 is divided by the ratio of the on-resistance of the pull-up transistor 8, the protective resistor 3, the fuse resistor 2, and the dividing resistor 6 to the gate electrode of the protective NMOS transistor 4. However, since the dividing resistor 6 is small, the leakage current of the protective NMOS transistor 4 is very small. If the threshold value of the protective NMOS transistor 4 is increased by ion implantation, the leakage current can be further reduced.
(Example 2)
FIG. 5 shows another embodiment of the present invention. In contrast to the first embodiment, a transistor 12 for fixing the output of the input circuit and a transistor 13 for determining the initial value of the output of the input circuit are added instead of the pull-up transistor 8.
[0014]
In the first embodiment, when the fuse 2 is not cut, the pull-up transistor 8 is normally on, so that a current flows between the power supply line 9 and the ground line 5 via the fuse resistor 2 and the divided resistor 6. In this embodiment, when the fuse 2 is not cut, the input of the inverter which is the input circuit 7 is fixed to Low, so that the transistor 13 for fixing the output of the input circuit is turned off and the power supply line 9 and the ground line 5 are connected. Current does not flow between them, and current consumption does not increase. At this time, since the gate of the protective NMOS transistor 4 is also at the same potential as the ground line, there is no concern about the leakage current of the protective NMOS transistor 4.
[0015]
【The invention's effect】
According to the present invention, a fuse trimming circuit in which a high electric field is not applied to a gate oxide film even when the gate oxide film is thinned by IC miniaturization can be configured. In the present invention, the fuse trimming circuit on the P-type semiconductor substrate has been described. Of course, an N-type substrate may be used.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram of the prior art.
FIG. 3 is a diagram illustrating a resistance ratio dependence of a current-voltage current flowing through an NMOS transistor during fuse trimming and a divided resistor.
FIG. 4 is a plan view of a fuse resistor and a split resistor.
FIG. 5 is a circuit diagram showing another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Pad terminal 2 Fuse resistance 3 Protection resistance 4 Protection NMOS transistor 5 Ground line 6 Dividing resistor 7 Input circuit 8 Pull-up transistor 9 Power supply line 10 Polycrystalline silicon 11 Contact 12 Transistor 13 for fixing the output of the input circuit 13 Input circuit Transistor that determines the initial value of the output

Claims (1)

導体基板上に設けられたトリミングを行なうパッド端子と、
該パッド端子に一方の端を結合する切断可能なフューズ抵抗と、
該フューズ抵抗の他方の端と接地線を結合する分割抵抗と、
該パット端子に一方の端を結合する保護抵抗と、
該保護抵抗の他方の端にドレインが結合し、ソースは接地され、かつ、ゲート電極該フューズ抵抗と該分割抵抗の結合部に結合している保護用NMOSトランジスタと、
該保護抵抗の該他方の端にゲート電極が結合した入力回路と、
該保護抵抗の該他方の端に結合して該入力回路のレベルを決めるための電源線に吊られたプルアップトランジスタと、
からなることを特徴としたフューズトリミング回路。
A pad terminal trimming provided on a semi-conductor substrate,
A severable fuse resistor coupling one end to the pad terminal;
A split resistor that couples the other end of the fuse resistor to the ground wire;
A protective resistor for coupling one end to the pad terminal;
Drain is coupled to the other end of the protective resistance, the source is grounded, and the gate electrode and the protective NMOS transistor coupled junction of the fuse resistor and the divided resistor,
An input circuit having a gate electrode coupled to the other end of the protective resistor ;
A pull-up transistor suspended on a power line for coupling to the other end of the protective resistor to determine the level of the input circuit;
A fuse trimming circuit comprising:
JP03482599A 1999-02-12 1999-02-12 Fuse trimming circuit Expired - Fee Related JP4248658B2 (en)

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Publication number Priority date Publication date Assignee Title
JP2006294903A (en) 2005-04-12 2006-10-26 Nec Electronics Corp Fuse trimming circuit
JP2009506577A (en) * 2005-08-31 2009-02-12 インターナショナル・ビジネス・マシーンズ・コーポレーション Random access electrically programmable E-fuse ROM
JP4851357B2 (en) * 2007-02-09 2012-01-11 ルネサスエレクトロニクス株式会社 Semiconductor device and test method thereof
JP5629075B2 (en) * 2009-09-16 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. Semiconductor device
TWI484313B (en) * 2013-08-05 2015-05-11 Nuvoton Technology Corp Reference voltage generating circuit and voltage adjusting device having negative charge protection mechanism of the same
CN113189477B (en) * 2020-09-03 2022-10-28 深圳利普芯微电子有限公司 Chip trimming circuit and trimming method

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