JP4248658B2 - Fuse trimming circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fuse trimming circuit of an IC that requires adjustment of an oscillation circuit or the like, such as an LCD controller IC.
[0002]
[Prior art]
FIG. 2 shows a conventional fuse trimming circuit. In order to determine the level of the gate electrode of the input circuit 7, the fuse resistor 2 and the pull-up transistor 8 are used as basic components, and the protection resistor 3 and the protection NMOS transistor are provided to protect the inverter from electrostatic breakdown. It was. At this time, the gate electrode of the protective NMOS transistor 4 was connected to the ground line 5.
[0003]
In a fuse trimming circuit, a current flows through a fuse resistor made of polycrystalline silicon or the like by applying a voltage to a pad terminal to be trimmed, and the fuse is generated by heat generated in proportion to the power represented by resistance * current * current. The resistor was melted and trimmed.
[0004]
[Problems to be solved by the invention]
As IC miniaturization progresses, the gate oxide film becomes thinner and the breakdown voltage of the gate oxide film is decreasing. For example, in the case of a 100 Å oxide film, an electric field of 10 MV / cm is applied at 10V. Since the intrinsic breakdown electric field of the thermal oxide film is about 11 MV / cm, if 11 V is applied, the element is destroyed. Even if the electric field does not reach the intrinsic breakdown electric field, the tunnel current flows as a high electric field is applied, which increases the damage to the gate oxide film, which is a problem in reliability. Further, the drain breakdown voltage of the NMOS transistor 4 which is a protection element for allowing a current to flow when static electricity is applied decreases as the gate oxide film becomes thinner. However, since the decrease is gentle, before the NMOS transistor 4 releases static electricity. In addition, a high electric field is applied to the gate oxide film of the inverter 7 to destroy it.
[0005]
In the process in which the NMOS transistor as the protective element passes a current, there are avalanche breakdown of the drain and a bipolar operation between the source, the substrate, and the drain. When the gate electrode of the NMOS transistor is grounded, a bipolar operation occurs between the source, the substrate, and the drain by using the substrate current generated by the avalanche breakdown of the drain first and then the avalanche breakdown as a trigger, and a large current flows. During the bipolar operation, only a low voltage is applied to the drain of the NMOS transistor, but since the avalanche breakdown of the drain before the bipolar operation is normally 12-17 V, the voltage is applied to the gate oxide film of the input circuit.
[0006]
[Means for Solving the Problems]
In the present invention, the fuse resistor is blown by heat generated in proportion to the power, but the potential of the gate electrode of the NMOS transistor as the protective element is not grounded, but the fuse resistor and the resistor for voltage division are connected in series. The gate electrode potential of the NMOS transistor is set to an intermediate potential between the drain and the ground line.
[0007]
Therefore, since the voltage applied to the pad terminal is divided and supplied as the gate voltage of the NMOS transistor, the substrate current increases due to channel hot carriers, and the bipolar operation between the source, the substrate, and the drain can be performed without causing an avalanche breakdown. A large current was made to flow. As a result, no high voltage is applied to the drain, and no high electric field is applied to the gate oxide film of the input circuit 7. Further, after the fuse resistor is blown, the gate voltage of the NMOS transistor is fixed to the ground line, so that the NMOS transistor is normally off.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
FIG. 1 shows an embodiment of the present invention. In the embodiment, a fuse trimming circuit provided on a P-type substrate is shown. Fuse resistor 2 and the coercive Mamoru抵 anti 3 and NMOS transistor 4 and the ground line 5 and the potential of the pad terminal 1 to the gate electrode of the NMOS transistor acting current as a protective element for the flow of the pad terminal 1 for trimming of polycrystalline silicon And a pull-up transistor 8 for determining the level of the input circuit 7. Each element is described below.
[0009]
Here, a case where the input circuit 7 is an inverter will be described.
The total resistance value of the fuse resistor 2 made of polycrystalline silicon is about 100Ω. However, as shown in FIG. 4A, a constricted shape is preferred so that current is concentrated and heat is easily generated.
The substrate current that triggers the NMOS transistor to enter the bipolar operation differs depending on the drain structure, but it is the highest when the gate voltage is about 1/2 to 1/4 of the drain voltage. 6 the following is a good 100Ω. The time-sharing resistor 6 avoids a shape in which current concentrates as shown in FIG. 4 (b). Here, it is sufficient that the fuse resistor 2 is more likely to concentrate the current and more easily melt than the divided resistor 6.
[0010]
In this embodiment, the material of the dividing resistor 6 and the fuse resistor 2 has been described with respect to polycrystalline silicon. However, a laminated film of a silicide film such as WSi and a polycrystalline silicon film or a metal film may be used.
Coercive Mamoru抵 anti-3 may be about 1kΩ. The NMOS transistor 4 that acts as a protection element has a width of about 400 um and a channel length of about 1.0 um, but these sizes are capable of driving a current of about 200 mA in a state where the transistor is in a bipolar operation, and is destroyed. It is good if it does not reach.
[0011]
Next, the operation when trimming (cutting the fuse resistor) will be described.
When a voltage is applied to the pad terminal 1, a current flows through the ground line via the fuse resistor 2 and the dividing resistor 6. Usually, a voltage pulse of 50 to 100 msec is applied. In the NMOS transistor 4, the potential of the gate electrode becomes an intermediate potential determined by the resistance division ratio of the voltage of the pad terminal and the voltage of the ground line 5, generates a substrate current due to channel hot carriers, and enters a bipolar operation. The process of entering the bipolar operation is shown in FIG. The point A in FIG. 3 shows the voltage that enters the snapback voltage, and the point B shows the voltage after entering the bipolar operation. Curves (1), (2), and (3) in FIG. 3 represent cases where the resistance ratio of the fuse resistor 2 and the dividing resistor 6 is changed. (1) is 14-17 V in the case of the NMOS transistor when there is no dividing resistor 6. When the value of the dividing resistor 6 is increased, the curve moves from (2) to (3), and the snapback voltage at the point A is decreased. At this time, the voltage at point B hardly changes.
[0012]
After the fuse resistor 2 is disconnected, the gate electrode of the NMOS transistor is fixed to the ground line. However, since the NMOS transistor has already entered the bipolar operation, the bipolar operation continues until the pulse applied to the pad terminal 7 ends. The highest voltage is applied to the gate oxide film of the input circuit 7 before the protective NMOS transistor enters the bipolar operation. However, the voltage is lower than the snapback voltage at the point A and is almost the voltage at the point B when the bipolar operation is started. Fixed to. Since the snapback voltage at point A can be controlled by the resistance ratio of the fuse resistor 2 and the dividing resistor 6, the voltage does not affect the gate oxide film according to the thickness of the gate oxide film of the input circuit 7. Select A point. After the fuse resistor 2 is cut, the level of the gate of the input circuit 7 is determined by the pull-up transistor 8 and is fixed to the potential of the power supply line 9, that is, High.
[0013]
Next, the case where the fuse resistor 2 is not cut will be described. The gate level of the input circuit 7 is determined by the sum of the protective resistor 3, the fuse resistor 2 and the dividing resistor 6 and the pulling of the drive capability of the pull-up transistor 8, but the gate level of the input circuit 7 is fixed to Low. In addition, the size of the pull-up transistor 8 and the sum of the protective resistor 3, the fuse resistor 2, and the dividing resistor 6 must be determined. When the fuse resistor 2 is not cut, the voltage of the power supply line 9 is divided by the ratio of the on-resistance of the pull-up transistor 8, the protective resistor 3, the fuse resistor 2, and the dividing resistor 6 to the gate electrode of the protective NMOS transistor 4. However, since the dividing resistor 6 is small, the leakage current of the protective NMOS transistor 4 is very small. If the threshold value of the protective NMOS transistor 4 is increased by ion implantation, the leakage current can be further reduced.
(Example 2)
FIG. 5 shows another embodiment of the present invention. In contrast to the first embodiment, a transistor 12 for fixing the output of the input circuit and a transistor 13 for determining the initial value of the output of the input circuit are added instead of the pull-up transistor 8.
[0014]
In the first embodiment, when the fuse 2 is not cut, the pull-up transistor 8 is normally on, so that a current flows between the power supply line 9 and the ground line 5 via the fuse resistor 2 and the divided resistor 6. In this embodiment, when the fuse 2 is not cut, the input of the inverter which is the input circuit 7 is fixed to Low, so that the transistor 13 for fixing the output of the input circuit is turned off and the power supply line 9 and the ground line 5 are connected. Current does not flow between them, and current consumption does not increase. At this time, since the gate of the protective NMOS transistor 4 is also at the same potential as the ground line, there is no concern about the leakage current of the protective NMOS transistor 4.
[0015]
【The invention's effect】
According to the present invention, a fuse trimming circuit in which a high electric field is not applied to a gate oxide film even when the gate oxide film is thinned by IC miniaturization can be configured. In the present invention, the fuse trimming circuit on the P-type semiconductor substrate has been described. Of course, an N-type substrate may be used.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram of the prior art.
FIG. 3 is a diagram illustrating a resistance ratio dependence of a current-voltage current flowing through an NMOS transistor during fuse trimming and a divided resistor.
FIG. 4 is a plan view of a fuse resistor and a split resistor.
FIG. 5 is a circuit diagram showing another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Pad terminal 2 Fuse resistance 3 Protection resistance 4 Protection NMOS transistor 5 Ground line 6 Dividing resistor 7 Input circuit 8 Pull-up transistor 9 Power supply line 10 Polycrystalline silicon 11 Contact 12 Transistor 13 for fixing the output of the input circuit 13 Input circuit Transistor that determines the initial value of the output

Claims (1)

A pad terminal trimming provided on a semi-conductor substrate,
A severable fuse resistor coupling one end to the pad terminal;
A split resistor that couples the other end of the fuse resistor to the ground wire;
A protective resistor for coupling one end to the pad terminal;
Drain is coupled to the other end of the protective resistance, the source is grounded, and the gate electrode and the protective NMOS transistor coupled junction of the fuse resistor and the divided resistor,
An input circuit having a gate electrode coupled to the other end of the protective resistor ;
A pull-up transistor suspended on a power line for coupling to the other end of the protective resistor to determine the level of the input circuit;
A fuse trimming circuit comprising:

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