JP4244396B2 - Capacitance of semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacity of a semiconductor integrated circuit and a manufacturing method thereof, and more particularly to a capacity of a MOS structure and a manufacturing method thereof.
[0002]
[Prior art]
In a semiconductor integrated circuit, a capacitor is used in many cases. For example, in a D-RAM, capacitors are arranged in a matrix and are used for storing digital signals. Further, in a solid-state imaging device or the like, a capacitor is used to temporarily accumulate signal charges.
[0003]
Several structures of capacitors arranged in such semiconductor integrated circuits have been proposed. For example, the metal used for wiring etc. is arrange | positioned in two layers, this is made into an electrode, and the thing mutually insulated with the insulating film between them is mentioned. A so-called MOS structure having a silicon substrate as a first electrode and a metal or polysilicon used for wiring as a second electrode and insulated by an oxide film therebetween has also been proposed. The former requires a multilayer metal process, while the latter can also be formed by a single-layer metal process.
[0004]
Incidentally, in recent years, semiconductor integrated circuits have been miniaturized. Miniaturization is also demanded in the capacitance, and the oxide film thickness is reduced in order to reduce the area of the capacitance of the MOS structure while maintaining the capacitance value.
Further, in order to charge and discharge the capacitor at a high speed, the impurity concentration of the semiconductor under the oxide film is increased and the resistance is lowered.
[0005]
However, if the oxide film thickness is reduced, the dielectric breakdown voltage is reduced. Therefore, the oxide film is thickened at a portion where a relatively high breakdown voltage is required such as the gate or under the wiring of the MOS transistor, and the oxide film is thinned at the MOS capacitor portion. By doing so, the MOS capacitance is miniaturized without adversely affecting the MOS transistor or the like.
7 is a capacitance plan view of a conventional semiconductor integrated circuit, and FIG. 8 is a partial cross-sectional view taken along the line BB ′ of FIG. An N-type diffusion layer 202 is formed on the surface of the P-type Si substrate 201, and an N + -type diffusion layer 203 for making ohmic contact with the metal wiring is formed in the N-type diffusion layer 202. A thick oxide film 204 and a thin oxide film 205 are formed on the Si substrate surface. A thin oxide film 205 is provided on a part of the N-type diffusion layer 202 and is covered with an N + type polysilicon 206. An aluminum wiring 207 is connected to the N + type diffusion layer 203.
[0006]
The N type diffusion layer 202 is one electrode of the capacitor, and the N + type polysilicon 206 is the other electrode of the capacitor. The charge is accumulated on these electrodes arranged on both sides of the thin oxide film 205. Charges stored in the N-type diffusion layer 202 are input / output via the aluminum wiring 207 and the N + -type diffusion layer 203. If only the function as an electrode is required, the N-type diffusion layer 202 is unnecessary, and a silicon substrate may be used instead. However, in order to charge and discharge the capacitor at high speed, it is preferable to lower the resistance of this portion. Further, when the impurity concentration of the silicon substrate is low, the surface of the silicon substrate is depleted depending on the bias condition, and the capacitance value changes. Also from this point, it is preferable to provide the high concentration N-type diffusion layer 202.
[0007]
In the N-type diffusion layer 202, there are secondary defects 208 generated by ion implantation described later.
9 to 12 are capacitance cross-sectional views in respective steps of a conventional method of manufacturing a capacity of a semiconductor integrated circuit. The manufacturing method will be described with reference to these drawings.
First, the P-type silicon substrate 201 is thermally oxidized to form a thick oxide film 204, and then a photoresist 209 is provided so as to open a region for forming the N-type diffusion layer 202 by photolithography. Then, ³¹ P ⁺ is implanted into the opening according to the ion implantation method under the conditions of an acceleration energy of 100 KeV and a dose of 5 × 10 ¹⁴ cm ⁻² (FIG. 9).
[0008]
After removing the photoresist 209, annealing is performed at 900 ° C. for 30 minutes to activate the ion species ³¹ P ⁺ and form the diffusion layer 202. Next, a photoresist 210 is provided by a photolithography technique so that a portion where the thin oxide film 205 is formed is opened. Next, the thick oxide film 204 is removed by etching using this as a mask. FIG. 10 shows this state.
[0009]
After removing the photoresist 210, a thin oxide film 205 is formed by thermal oxidation in the region where the thick oxide film 204 has been removed in the above process. Next, N + type polysilicon 206 is deposited by low pressure CVD, and a photoresist 211 is formed on a portion covering the thin oxide film 205 by photolithography (FIG. 11).
The N + type polysilicon 206 is etched using the photoresist 211 as a mask. The remaining N + type polysilicon 206 becomes one of the two electrodes of the capacitive element. After removing the photoresist 211, ³¹ P ⁺ is implanted into the N-type diffusion layer 202 in accordance with a photolithography technique and an ion implantation method. Next, ionic species ³¹ P ⁺ is activated by annealing at 950 ° C. for 30 minutes, and an N + -type diffusion layer 203 is provided.
[0010]
Next, the aluminum electrode 207 is connected to the N + type diffusion 203 by a well-known wiring formation technique, and the capacitance shown in FIGS. 7 and 8 is completed.
[0011]
[Problems to be solved by the invention]
As for the capacity of a conventional semiconductor integrated circuit, in order to make the N-type diffusion layer 202 have a low impedance as described above and to prevent depletion of the diffusion layer, ion implantation of 1 × 10 ¹⁴ cm ⁻² or more is generally performed. . By the way, when ion implantation is performed, crystal defects (secondary defects) are generated in the semiconductor substrate. It is known that this crystal defect disappears by recrystallization by annealing treatment. However, when the implantation amount is as high as 1 × 10 ¹⁴ cm ⁻² , even if annealing is performed, recrystallization does not occur completely, and crystal defects remain. If a thin oxide film is formed on the crystal defect with the crystal defects remaining, there is a problem in that fine irregularities are formed in the oxide film, resulting in poor film quality and a breakdown voltage failure.
[0012]
The present invention has been made in view of this point, and an object of the present invention is to prevent an insulation failure of a capacitive element using an oxide film formed on a substrate ion-implanted at a high concentration as a dielectric.
[0013]
[Means for Solving the Problems]
Capacity of the semiconductor integrated circuit according to claim 1 is arranged a first oxide film thickness in the first region of the "P-type silicon substrate is 60nm or less, the first oxidation definitive in the first region is arranged impurity diffusion region by ion implantation of ³¹ P ⁺ in the above acceleration energy 150KeV through the film, the second oxide film thickness in the second region in the first region is 30nm or less arranged And an electrode is disposed so as to cover at least the second oxide film in the second region ”.
[0014]
The present inventor has found that when a semiconductor covered with an oxide film having a film thickness of 60 nm or less with an acceleration energy of 150 KeV or more is ion-implanted and annealed, the diffusion region is less likely to cause residual defects. It was. The reason is not clear. However, there is a theory that the mechanism in which secondary defects remain varies depending on the amount of oxygen atoms repelled from the oxide film into the substrate and the amount of impurities implanted (dose amount) (Japan Journal of Applied Physics vol. 27, No. 12, December, 1998, pp 2209-2217).
[0015]
According to this theory, since the oxide film thickness and acceleration energy are optimized in the present invention, it is estimated that crystal defects caused by ion implantation are almost completely eliminated. Since the remaining crystal defects are reduced, a high breakdown voltage can be maintained even if a capacitor is created by making the above oxide film thickness thinner than before. Further, the density of remaining crystal defects varies depending on the ion species. If the ionic species is ³¹ P ^+, it is almost completely recrystallized.
The capacitance of the semiconductor integrated circuit according to claim 2 is the capacitance according to claim 1, wherein the second region is provided in a part of the first region, the electrode is polysilicon, and the impurity diffusion region Is one electrode of the capacitor, and the polysilicon is the other electrode of the capacitor, and the charge accumulated in the capacitor is accumulated on both sides of the second oxide film .
[0016]
The capacitor of the semiconductor integrated circuit according to claim 3 is characterized in that in the capacitor according to claim 1, "the first oxide film and the second oxide film are each 5 nm or more in thickness". Originally, this oxide film is called a protective oxide film, and serves to prevent damage to the silicon crystal due to various processes and to prevent loss of impurities doped into silicon during annealing. However, as a result of earnest research, it has been found that if the thickness is 5 nm or more, the object can be sufficiently achieved, and the present invention has been achieved.
[0017]
According to a fourth aspect of the present invention, there is provided a capacitor manufacturing method comprising: a step of thermally oxidizing a surface of a P-type silicon substrate to form a first oxide film having a thickness of 60 nm or less in at least a first region; a step of the ³¹ P ⁺ ion implantation acceleration energy as more 150KeV through the first oxide film definitive in the region, and annealing the semiconductor substrate, the first of said first region by photolithography Removing one oxide film by etching to form a second region in the first region, and thermally oxidizing the P-type silicon substrate to form a second region of 30 nm or less in the second region. forming an oxide film, and a step of forming the second electrode over the oxide film in at least the second region by photolithography "that And butterflies.
[0018]
The capacitance manufacturing method according to claim 5 is the capacitance manufacturing method according to claim 4 , wherein in the step of forming the second region, a part of the first oxide film in the first region is etched, and the electrode In the step of forming the electrode, polysilicon is used to form the impurity diffusion region as one electrode of the capacitor and the polysilicon as the other electrode of the capacitor, so that the accumulated charges are It is formed so as to be accumulated on both sides of the film ”.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a capacitance plan view of a semiconductor circuit according to an embodiment of the present invention, and FIG. 2 is a partial cross-sectional view taken along line AA ′ of FIG. An N type diffusion layer 102 (first region) is formed on the surface of the P type Si substrate 101, and an N + type diffusion layer 103 for making ohmic contact with the metal wiring is disposed in the N type diffusion layer 102. . A first oxide film 104 having a thickness of 50 nm and a second oxide film 105 having a thickness of 15 nm are disposed on the surface of the Si substrate. The second oxide film 105 is disposed in a part (second region) on the N-type diffusion layer 102, and is covered with N + -type polysilicon 106. An aluminum wiring 107 is connected to the N + type diffusion layer 103.
[0020]
The N type diffusion layer 102 is one electrode of the capacitor, and the N + type polysilicon 106 is the other electrode of the capacitor. The charge is accumulated on both sides of the thin oxide film 105. Charges accumulated in the N-type diffusion layer 102 are input / output through the aluminum wiring 107 and the N + -type diffusion layer 103. The N-type diffusion layer 102 is provided so that the first region has a low resistance so that the capacitance is suitable for high-speed reading, and the silicon surface is depleted to prevent the capacitance value from changing. Reference numeral 108 denotes a region where crystal defects are recrystallized.
[0021]
3 to 6 are capacitance sectional views in respective steps of the semiconductor integrated circuit capacitance manufacturing method according to the present invention. The manufacturing method will be described with reference to these drawings.
First, a P-type substrate 101 is thermally oxidized to form a first oxide film 104 having a thickness of 50 nm, and then a photoresist 109 is formed so as to open a region for forming the N-type diffusion layer 102 by photolithography. Provide. Then, ³¹ P ⁺ is implanted into the opening according to the ion implantation method under the condition of an acceleration energy of 170 KeV and a dose of 5 × 10 ¹⁴ cm ⁻² (FIG. 3).
[0022]
After the photoresist 109 is peeled off, annealing is performed at 900 ° C. for 30 minutes to activate the ion species ³¹ P ⁺ to form the N-type diffusion layer 102. Next, a photoresist 110 is provided by a photolithography technique so that a portion for forming a second oxide film 105 described later is opened. Next, using this as a mask, the portion of the first oxide film 104 is removed by etching. FIG. 4 shows this state.
[0023]
After the photoresist 110 is peeled off, a second oxide film 105 having a thickness of 15 nm is formed by thermal oxidation in the region (second region) from which the first oxide film 104 has been removed in the above process. Next, N + type polysilicon 106 is deposited by low pressure CVD, and a photoresist 111 is formed on the portion covering the second oxide film 105 by photolithography (FIG. 5).
[0024]
The N + type polysilicon 106 is etched using the photoresist 111 as a mask. The remaining N + type polysilicon 106 becomes one of the two electrodes of the capacitive element. After stripping the photoresist 111, ³¹ P ⁺ is implanted into the N-type diffusion layer 102 by photolithography and ion implantation. Next, ionic species ³¹ P ⁺ is activated by annealing at 950 ° C. for 30 minutes, and an N + type diffusion layer 103 is provided.
[0025]
Next, the aluminum electrode 107 is connected to the N + type diffusion 103 by a well-known wiring formation technique, and the capacitance of the semiconductor integrated circuit according to the present invention shown in FIGS. 1 and 2 is completed.
In the present invention, by examining the relationship between the ion implantation conditions and the occurrence of an oxide film breakdown voltage failure, the inventors have found a condition where no breakdown voltage failure occurs. In the present invention, it is presumed that the secondary defect 108 of the ion implantation does not exist or exists only at an extremely low density.
[0026]
When a capacitive element was prepared according to the present invention and the oxide film breakdown voltage was measured, the defect occurrence rate was 7% in the past, but it was improved to 0%.
[0027]
【The invention's effect】
As described in detail above, according to the present invention, even if high-concentration ion implantation is performed, crystal defects are reliably recrystallized by subsequent annealing, and residual defects can be reduced. Therefore, an oxide film having a good film quality can be formed on the diffusion portion subjected to high-concentration ion implantation. For this reason, even if the oxide film is made thinner, a capacitor element having a good breakdown voltage can be obtained. .
[Brief description of the drawings]
FIG. 1 is a capacitance plan view of a semiconductor circuit according to an embodiment of the present invention.
FIG. 2 is a partial cross-sectional view taken along the line AA ′ of FIG.
FIG. 3 is a cross-sectional view of a capacitor in each step of a method for manufacturing a capacitor of a semiconductor integrated circuit according to the present invention.
FIG. 4 is a cross-sectional view of a capacitor in each step of a method of manufacturing a capacitor of a semiconductor integrated circuit according to the present invention.
FIG. 5 is a cross-sectional view of a capacitor in each step of the semiconductor integrated circuit capacitor manufacturing method according to the present invention;
FIG. 6 is a cross-sectional view of a capacitor in each step of the method for manufacturing a capacitor of a semiconductor integrated circuit according to the present invention.
FIG. 7 is a capacitance plan view of a conventional semiconductor integrated circuit.
FIG. 8 is a cross-sectional view taken along the line BB ′ of FIG.
FIG. 9 is a cross-sectional view of a capacitor in each step of a conventional method for manufacturing a capacitor of a semiconductor integrated circuit.
FIG. 10 is a cross-sectional view of a capacitor in each step of a conventional method for manufacturing a capacitor of a semiconductor integrated circuit.
FIG. 11 is a cross-sectional view of a capacitor in each step of a conventional method for manufacturing a capacitor of a semiconductor integrated circuit.
FIG. 12 is a cross-sectional view of a capacitor in each step of a conventional method for manufacturing a capacity of a semiconductor integrated circuit.
[Explanation of symbols]
101, 201... P type semiconductor substrate 102, 202... N type diffusion layer 103, 203... N + type diffusion layer 104, 105. Silicon 107, 207 ... Al wiring 108 ... Crystal defect disappearance portion 109, 110, 111 ... Photoresist 204 ... Thick oxide film 205 ... Thin oxide film 208 ... Crystal defects caused by ion implantation 209, 210, 211 ... Photoresist

Claims (5)

A first oxide film having a thickness of 60 nm or less is disposed in a first region on a P-type silicon substrate;
The first definitive in the area the first impurity diffusion region of ³¹ P ⁺ ions are implanted at 150KeV more acceleration energy through the oxide film is disposed,
A second oxide film having a thickness of 30 nm or less is disposed in the second region in the first region;
A capacitance of a semiconductor integrated circuit, wherein an electrode is disposed to cover at least the second oxide film in the second region. The second region is provided in a part of the first region, and the electrode is polysilicon;
  The impurity diffusion region is one electrode of a capacitor, and the polysilicon is the other electrode of the capacitor;
  2. The capacitor of the semiconductor integrated circuit according to claim 1, wherein the electric charge accumulated in the capacitor is accumulated on both sides of the second oxide film.   2. The capacitance of a semiconductor integrated circuit according to claim 1, wherein both the first oxide film and the second oxide film have a thickness of 5 nm or more. Thermally oxidizing the surface of the P-type silicon substrate to form a first oxide film of 60 nm or less in at least the first region;
A step of ion-implantation ³¹ of P ⁺ as above 150KeV acceleration energy via the first oxide film definitive in the first region using a photolithography technique,
Annealing the semiconductor substrate;
Removing the first oxide film in the first region by etching using a photolithography technique to form a second region in the first region;
Thermally oxidizing the P-type silicon substrate to form a second oxide film of 30 nm or less in the second region;
And a step of forming an electrode so as to cover at least the second oxide film in the second region by a photolithography technique. In the step of forming the second region, a part of the first oxide film in the first region is etched,
In the step of forming the electrode, by forming the electrode from polysilicon, the impurity diffusion region is used as one electrode of the capacitor, and the polysilicon is used as the other electrode of the capacitor, so that the accumulated charge is the second electrode. 5. The method of manufacturing a capacitor of a semiconductor integrated circuit according to claim 4, wherein the capacitor is formed so as to be accumulated on both sides of the oxide film.

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