JP4236895B2 - Driving method of active display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit formed on an insulating surface. The present invention also relates to a display device including the semiconductor integrated circuit as a drive circuit and a light emitting element provided on an insulating surface. In particular, the present invention relates to an active matrix display device including the driving circuit, in which a plurality of pixels are arranged in a matrix, and a switching element and a light emitting element are arranged for each pixel.
[0002]
[Prior art]
An active matrix display device having a plurality of pixels, in which switching elements and light emitting elements are arranged for each of the plurality of pixels, has advantages such as excellent response, operation at a low voltage, and a wide viewing angle. It is attracting attention as a next-generation flat panel display.
[0003]
The light-emitting element is an element that emits light with a luminance corresponding to a flowing current, such as an OLED (Organic Light Emitting Diode) element, a field emission (FE) element, and a MIM (Metal-Insulator-Metal). ) And the like using electron source elements represented by type elements.
[0004]
The structure of the light-emitting element includes an anode, a cathode, and a layer containing an organic compound sandwiched between the anode and the cathode (hereinafter simply referred to as an organic compound layer). The light emitting element emits light by applying a voltage between the anode and the cathode. Note that causing the light emitting element to emit light is also referred to as driving the light emitting element.
[0005]
This organic compound layer usually has a laminated structure, and a typical example is a laminated structure of “hole transport layer / light emitting layer / electron transport layer” proposed by Tang et al. Of Kodak Eastman Company. In addition, the hole injection layer / hole transport layer / light emitting layer / electron transport layer, or hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer are laminated in this order on the anode. It may be a structure. You may dope a fluorescent pigment | dye etc. with respect to a light emitting layer. When a predetermined voltage is applied to the organic compound layer from a pair of electrodes (anode and cathode), recombination of carriers occurs in the light emitting layer to emit light.
[0006]
The light emission luminance of the light emitting element at this time is proportional to the current flowing between the electrodes of the light emitting element (between the anode and the cathode). For this reason, there has been proposed a pixel configuration in which a current flowing through a light emitting element of each pixel is controlled by a current input to the pixel portion (hereinafter referred to as a control current). This pixel configuration is referred to as a current control type pixel.
[0007]
The current control type pixel circuit as described above is described in Patent Document 1, for example.
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-147659
[0009]
FIG. 7 illustrates an example of a structure of a current control pixel which is an active matrix display device.
[0010]
As shown in FIG. 7, the pixel structure includes a signal line 701, a scanning line 702, a power supply line 703, a wiring 710, a light emitting element 709, a switching transistor (switching transistor) 704, and a current holding transistor ( A current holding transistor) 705, a transistor (current transistor) 706 constituting a current mirror circuit, a current mirror circuit, a transistor for driving a light emitting element (driving transistor) 707, and a holding capacitor 708;
[0011]
One of the source electrode and the drain electrode of the switching transistor 704 is connected to the signal line 701, and the other is connected to the drain electrode of the current transistor 706 and one of the source electrode or the drain electrode of the current holding transistor 705, and the switching transistor 704 The gate electrode is connected to the scanning line 702.
[0012]
The source electrode of the current transistor 706 is connected to the power supply line 703. The side of the source electrode or drain electrode of the current holding transistor 705 that is not connected to the switching transistor 704 is connected to one electrode of the holding capacitor 708, the gate electrode of the current transistor 706, and the gate electrode of the driving transistor 707. ing.
[0013]
The side of the storage capacitor 708 that is not connected to the current holding transistor 705 is connected to the power supply line 703. A source electrode of the driving transistor 707 is connected to the power supply line 703, and a drain electrode is connected to one electrode of the light emitting element 709.
[0014]
Next, a driving method (operation method) in which a video signal is input to the pixel having the configuration illustrated in FIG. 7 and the light emitting element emits light will be described. Note that a current (signal current) having a current value corresponding to the luminance expressed by the pixel is input as the video signal input to the pixel. In the pixel configured as shown in FIG. 7, a current (control current) for controlling a current flowing through the light emitting element of each pixel corresponds to a video signal (signal current).
[0015]
When a signal is input to the scan line 702 and the switching transistor 704 is turned on, a signal current input from the signal line 702 is input to the pixel. At this time, the current holding transistor 705 is turned on by a signal input to the wiring 710.
[0016]
When a sufficient time elapses after the signal current is input to the pixel, the signal current flows between the source and drain of the current transistor 706. At this time, the storage capacitor 708 holds a gate voltage (gate-source voltage) for allowing the current transistor 706 to flow a signal current as a drain current. After that, the signal of the wiring 710 changes, and the current holding transistor 705 is turned off.
[0017]
When the characteristics of the current transistor 706 and the driving transistor 707 are equal, the drain current of the current transistor 706 and the drain current of the driving transistor 707 are equal. At this time, a current equal to the input signal current is input to the light emitting element 709 from the power supply line 703 through the driving transistor 707. Thus, the light emitting element 709 emits light with luminance corresponding to the signal current.
[0018]
Even after the signal current is not input to the pixel, the driving transistor 707 continues to pass a current equal to the signal current due to the voltage held in the storage capacitor 708.
[0019]
FIG. 8 is a block diagram illustrating a configuration of an active matrix display device including the current control type pixel as illustrated in FIG.
[0020]
In FIG. 8, a pixel portion 804 provided over a substrate having an insulating surface (hereinafter referred to as a pixel substrate) 801, and scan line driver circuits 803a and 803b for inputting signals to the scan lines of the pixels of the pixel portion 804. And a signal line driver circuit 802 that inputs a signal to a signal line of each pixel of the pixel portion 804. The signal line driver circuit 802 is formed of an LSI chip 806 or the like, and the LSI chip 806 is attached to the pixel substrate 801 with a TAB 805.
[0021]
Note that in a current control type pixel as shown in FIG. 7, a drive circuit for inputting a control current is referred to as a control current output circuit. In the display device having the configuration shown in FIG. 8, the control current output circuit corresponds to a signal line driver circuit.
[0022]
In addition, a wiring to which a control current output from the control current output circuit is supplied to the pixel portion is referred to as a control current line. In the pixel portion illustrated in FIG. 7, the control current line corresponds to the signal line 701.
[0023]
[Problems to be solved by the invention]
As shown in FIG. 8, a drive circuit (control current output circuit) for inputting a control current to a current control type pixel is formed from an LSI chip on a single crystal substrate. The single crystal substrate on which the control current output circuit is formed is attached using a pixel substrate and TAB or the like. Thus, the electrical connection between the pixel portion and the control current output circuit is established.
[0024]
For this reason, a margin area is required for attaching the control current output circuit, and it has become difficult to reduce the size of the display device. In addition, since the wiring resistance and wiring capacitance between the control current output circuit to which the electrical connection is established and the pixel portion are increased, it is difficult to reduce the power consumption of the display device.
[0025]
Therefore, it is desired that the control current output circuit is integrally formed on the pixel substrate using a polysilicon transistor (polycrystalline silicon transistor). Furthermore, the drive frequency can be set high by forming the control current output circuit with a polysilicon transistor.
[0026]
However, a control current output circuit manufactured using a polysilicon transistor has a problem that output current variation is large due to the influence of crystallinity variation in a channel formation region. Here, as described above, the light emitting element emits light with a luminance proportional to the flowing current. For this reason, if the control current varies between pixels, it becomes a variation in luminance of the light emitting elements of the pixels (hereinafter also referred to as display unevenness), which causes a problem.
[0027]
Therefore, an object of the present invention is to provide a control current output circuit manufactured using a polysilicon transistor in which variation in output current is suppressed.
[0028]
It is another object of the present invention to provide a display device that can be reduced in size and power consumption by using the control current output circuit of the present invention, and an electronic device using the display device.
[0029]
[Means for Solving the Problems]
The configuration of the drive circuit (control current output circuit) of the present invention will be described below.
[0030]
The control current output circuit corresponds to the reference current input to the control current output circuit, and m (m is a natural number) current output circuits (m is a natural number) that outputs currents having substantially the same current value. (Referred to as a semi-control current output circuit). Each of these m quasi-control current output circuits has a polysilicon transistor (specifically, a TFT having a polycrystalline semiconductor film: a polycrystalline TFT).
[0031]
The present invention averages output currents output from m quasi-control current output circuits to n (n is a natural number of m or less) output wirings (hereinafter referred to as output terminals) of control current output times. To be output.
[0032]
For example, output currents output from these m pieces of quasi-control current output circuits to n output terminals are sequentially switched and output.
[0033]
In other words, the combination of the connection between the output terminals connected to the m quasi-control current output circuits and the n output terminals is switched at regular intervals.
[0034]
In other words, the n output terminals may be connected to one different output terminal among the output terminals of the m quasi-control current output circuits in a certain period.
[0035]
Specifically, among the n output terminals, a control current output having a first output terminal, a second output terminal, a first quasi-control current output circuit, and a second quasi-control current output circuit. In the circuit, the first output terminal is connected to the output terminal of the first quasi-control current output circuit, and the second output terminal is connected to the output terminal of the second quasi-control current output circuit; The state in which the first output terminal and the output terminal of the second quasi-control current output circuit are connected and the second output terminal and the output terminal of the first quasi-control current output circuit are connected is selected. Means to do.
[0036]
With the above configuration, the output currents of the two quasi-control current output circuits are output from the first output terminal and the second output terminal in a state where they are temporally averaged.
[0037]
In this way, the output current (control current) output from the control current output circuit to the n control current lines is averaged over time.
[0038]
Accordingly, it is possible to provide a drive circuit (control current output circuit) in which variations in output current are suppressed. In the display device using the drive circuit (control current output circuit) of the present invention, the display unevenness of the pixels due to the control current variation can be visually reduced.
[0039]
Furthermore, according to the present invention, a control current output circuit manufactured on a substrate having an insulating surface using a polycrystalline TFT can be integrally formed on the substrate on which the pixel portion is formed. Therefore, a display device that can be reduced in size and reduced in power consumption can be provided.
[0040]
Note that the display device of the present invention may include a plurality of control current output circuits to form a signal line driver circuit, and the current values of the control currents output from the plurality of control current output circuits may be different. Further, the reference currents input to the plurality of control current output circuits may be equal.
[0041]
Note that each of the plurality of pixels included in the display device of the present invention includes a light emitting element, but the light emitting element may be an OLED element or an element using an electron source element.
[0042]
Note that in the present invention, the light-emitting element may use light emitted from singlet excitons (fluorescence) or may use light emitted from triplet excitons (phosphorescence).
[0043]
In addition, the organic compound layer of the light-emitting element may be any material of a low molecular material, a high molecular material, and a medium molecular material. The medium molecular material is a material having no sublimation property and a chain molecule length of 10 μm or less. The organic compound layer may be a stacked body of a layer containing an inorganic material and a layer containing an organic material. Specifically, an inorganic material such as silicon carbide may be used for the charge transport layer or the charge injection layer.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
A control current output circuit and a display device using the same according to the present invention will be described below.
[0045]
FIG. 1 is a diagram showing a configuration example of a control current output circuit of the present invention. In this embodiment, a control current output circuit configured to sequentially switch and output the output currents of the four quasi-control current output circuits 1102_1 to 1102_4 from the four output terminals (output terminal portions) of the control current output circuit. 1100 is shown as an example.
[0046]
In FIG. 1, the control current output circuit 1100 includes a switching circuit 1101 and semi-control current output circuits 1102 (1102_1 to 1102_4).
[0047]
The quasi-current output circuits 1102_1 to 1102_4 include transistors 1112_1 to 1112_4, and the output terminals (first terminals) C1 to C4 of the quasi-control current output circuits 1102_1 to 1102_4 are connected to the drain terminals of the transistors 1112_1 to 1112_4, respectively. Equivalent to. Gate electrodes of the transistors 1112_1 to 1112_4 are connected to a gate electrode of the reference transistor 1110. The gate electrode and the drain terminal (electrode) of the reference transistor 1110 are connected, and the reference current I0 input from the reference current source circuit 1111 flows between the source and the drain.
[0048]
Note that the potential of the source terminal (electrode) of the reference transistor 1110 and the potential of the source terminals of the transistors 1112_1 to 1112_4 are kept equal. In the configuration illustrated in FIG. 1, the source terminal of the reference transistor 1110 and the source terminals of the transistors 1112_1 to 1112_4 are connected to the power supply line 1120 and are given the same potential.
[0049]
Thus, the gate voltage of the reference transistor 1110 and the gate voltages of the transistors 1112_1 to 1112_4 are kept equal, and the transistors 1112_1 to 1112_4 pass currents I1 to I4 as drain currents, respectively. At this time, if the current characteristics of the transistors 1112_1 to 1112_4 are uniform, the current values of the currents I1 to I4 are equal. However, since the transistors 1112_1 to 1112_4 are polycrystalline TFTs, the currents I1 to I4 actually vary. Therefore, the switching circuit 1101 switches and outputs the currents I1 to I4.
[0050]
Note that the current characteristics of the reference transistor 1110 and the current characteristics of the transistors 1112_1 to 1112_4 are not necessarily the same. That is, when the same gate voltage is applied to the reference transistor 1110 and the transistor 1112 (indicating any one of the transistors 1112_1 to 1112_4), the designer sets the drain current to flow to a predetermined current ratio. Is possible. However, it is desirable that characteristics such as mobility and threshold voltage are uniform.
[0051]
For example, the gate length of the reference transistor 1110 is set to L ₀ , Gate width W ₀ And The gate length of the transistor 1112_1 is L ₁ , Gate width W ₁ And L ₀ / W ₀ : L ₁ / W ₁ By setting the ratio to 1: 2, the current I1 can be reduced to about ½ of the reference current I0.
[0052]
The reference transistor 1110 and the transistors 1102_1 to 1102_4 may be either n-channel TFTs or p-channel TFTs, but the polarities of the reference transistor 1110 and the transistors 1102_1 to 1102_4 must be the same.
[0053]
The control current output circuit of the present invention is not limited to this. m (m is a natural number) quasi-current output circuits and n (n is a natural number of m or less) switching means for selecting one from the m quasi-current output circuits, and the n switching Each of the means may have a function of changing the selection destination of the m quasi-current output circuits every predetermined period.
[0054]
Next, the configuration of the switching circuit 1101 will be described. The switching circuit 1101 includes switches SW1 to SW4 serving as switching means and a plurality of terminal groups each including terminals (second terminals) 1 to 4 as one group.
[0055]
The switches SW1 to SW4 respectively select the terminals 1 to 4 of each terminal group in order (however, in actuality, not the terminals but the wirings connected to the switches are selected). Here, in a certain switch SWp (p is a natural number of 1 to 4), when a terminal q (q is a natural number of 1 to 4) is selected from the terminal group, other switches other than SWp are also other types. Terminal q of the terminal group is selected.
[0056]
Here, the terminals 1 to 4 are connected to the output terminals C1 to C4 of the different quasi-control current output circuits 1102_1 to 1102_4, respectively. In the four sets of terminals 1 to 4 corresponding to the four control current lines CS1 to CS4, the terminals indicated by the same numbers are connected to the output terminals C1 to C4 of the different quasi-control current output circuits 1102_1 to 1102_4, respectively. Yes.
[0057]
Next, FIG. 2 shows an example of a specific circuit configuration of the switches SW1 to SW4 as switching means. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.
[0058]
In FIG. 2, each of the switches SW1 to SW4 is composed of four switches. The four switches sequentially select the terminals 1 to 4 according to signals input to the wirings A1 to A4 and the wirings A1b to A4b, and are connected to the control current lines CS1 to CS4.
[0059]
Note that a signal obtained by inverting the polarity of a signal input to the wiring Aq (q is a natural number of 1 to 4) is input to the wiring Aqb.
[0060]
Next, a method for driving the control current output circuit configured as shown in FIGS. 1 and 2 will be described. FIG. 3 is a timing chart showing a method for driving the control current output circuit.
[0061]
A1 to A4 and A1b to A4b illustrated in FIG. 3 indicate potentials of signals input to the wirings A1 to A4 and the wirings A1b to A4b. The frame periods F1 to F4 indicate one frame period in order. Note that one frame period is a period during which the display device displays one image. One frame period is normally set to about 1/60 seconds so that human eyes do not feel flicker.
[0062]
In the first frame period F1, signals are input to the wiring A1 and the wiring A1b, and the terminal 1 is selected in each of SW1 to SW4.
[0063]
In the second frame period F2, signals are input to the wiring A2 and the wiring A2b, and the terminal 2 is selected in each of SW1 to SW4.
[0064]
Similar operations are repeated, and the frame periods F1 to F4 are completed. Thus, SW1 to SW4 select terminal 1 to terminal 4, respectively, in order.
[0065]
Thus, by operating the switching circuit 1101 as described above, the temporal average values of the output currents of the control current lines CS1 to CS4 are the same.
[0066]
In this way, the currents output to the control current lines CS1 to CS4 are averaged and output over time. Therefore, by using the control current output circuit 1100 having the above structure in a display device, display unevenness of pixels due to variations in control current can be visually reduced.
[0067]
In the timing chart shown in FIG. 3, the switches SW1 to SW4 are sequentially switched for each frame period, and the terminals 1 to 4 are sequentially selected. In the above driving method, in a certain switch SWq (q is a natural number of 1 to 4), the period in which the terminal 1 is selected, the period in which the terminal 2 is selected, the period in which the terminal 3 is selected, and the terminal 4 The selected period is set to the same length.
[0068]
However, the present invention is not limited to this. The switches SW1 to SW4 can be switched every period of an arbitrary length. For example, the switches SW1 to SW4 may be switched every two frame periods, and the terminals 1 to 4 may be sequentially selected.
[0069]
When one frame is divided into a plurality of subframes and gradation display is performed, the switches SW1 to SW4 may be switched for each subframe. However, at this time, it is necessary to switch the switch outside the period in which a signal is written to the pixel. That is, one frame has sub-frame periods SF1, SF2,..., SFm, and the m sub-frame periods SF1, SF2,... SFm are written periods Ta1, Ta2,. ,..., Tsm, and the switch may be switched in any of the display periods Ts1, Ts2,.
[0070]
In FIGS. 1 and 2, only the control current output circuits corresponding to the four control current lines are shown as representatives. However, in an actual display device, all control current lines for inputting a control current to each pixel are divided into a plurality of sets, and in each set, a control current is output from a control current output circuit having the same configuration as in FIG. The configuration may be made.
[0071]
In FIG. 15A, all control current lines CS1 to CSx for inputting a control current to each pixel of the display device are divided into a plurality of groups (first group to rth (r is a natural number) group), respectively. In this group, control current output circuits 1100_B1 to 1100_Br having the same structure as the control current output circuit 1100 shown in FIG.
[0072]
Note that the configuration and driving method of each of the control current output circuits 1100_B1 to 1100_Br are the same as the configuration shown in FIGS. 1 and 2 and the driving method shown in FIG.
[0073]
In the configuration of FIG. 15A, the reference current I0 may be input from a common reference current source circuit in the control current output circuits 1100_B1 to 1100_Br corresponding to the plurality of sets of control current lines. Further, the control current output circuits 1100_B1 to 1100_Br may share the reference transistor.
[0074]
FIG. 15B illustrates a structure in which the control current output circuits 1100_B1 to 1100_Br include the common reference current source circuit 1111 and the reference transistor 1110 in the structure illustrated in FIG. 15A.
[0075]
Note that in the control current output circuits 1100_B1 to 1100_Br, the same portions as those in FIG. 1 are denoted by the same reference numerals.
[0076]
In FIG. 15B, the transistors 1112_1 to 1112_4 of the quasi-control current output circuits 1102_1 to 1102_4 constituting the control current output circuit 1100_B1, and the transistors of the quasi-control current output circuits 1102_1 to 1102_4 constituting the control current output circuit 1100_B2 1112_1 to 1112_4 have their source terminals connected to the power supply line 1120 and their gate electrodes connected to the gate electrode of the reference transistor 1110.
[0077]
In FIG. 15B, the control current output circuit 1100_B1 corresponding to the first set of control current lines CS1 to CS4 and the control current output circuit 1100_B2 corresponding to the second set of control current lines CS5 to CS8 are representative. The transistors 1112_1 to 1112_4 constituting the quasi-control current output circuits 1102_1 to 1102_4 of all the control current output circuits 1100_B1 to 1100_Br are connected to the power supply line 1120 and their gate electrodes are reference transistors. 1110 is connected to a gate electrode.
[0078]
In this way, a voltage equal to the gate voltage of the shared reference transistor 1110 is applied as the gate voltage of the transistors 1112_1 to 1112_4 constituting the semi-control current output circuits 1102_1 to 1102_4 of all the control current output circuits 1100_B1 to 1100_Br.
[0079]
Note that in the control current output circuits 1100_B1 to 1100_Br, the drive timing of the switching circuit 1101 can be the same. That is, the switches SW1 to SW4 constituting the switching circuit 1101 shown in FIG. 1 can select the same timing for selecting the terminals 1 to 4 in the switching circuits 1101 of all the control current output circuits 1100_B1 to 1100_Br.
[0080]
For example, a case where the same configuration as that in FIG. 2 is used as the configuration of the switching circuit 1101 is taken as an example. At this time, the wirings A1 to A4 and the wirings A1b to A4b of the switching circuit 1101 are shared by all the switching circuits 1101 of the control current output circuits 1100_B1 to 1100_Br.
[0081]
In this way, as shown in FIG. 3, signals are input to the wirings A1 to A4 and the wirings A1b to A4b, and the timing at which the switches SW1 to SW4 constituting the switching circuit 1101 select the terminals 1 to 4 is controlled by the control current. The same can be applied to all the switching circuits 1101 of the output circuits 1100_B1 to 1100_Br.
[0082]
With the configuration described above, it is possible to output temporally averaged control currents to all the control current lines CS1 to CSx formed in the pixel portion (region where a plurality of pixels are provided) of the display device. In this manner, it is possible to reduce the visual variation in the luminance of the light emitting element of each pixel included in the display device.
[0083]
(Embodiment 2)
In this embodiment, a structure of a control current output circuit which is different from the structure shown in Embodiment 1 is described with reference to FIG.
[0084]
In FIG. 14, the control current output circuit 1440 of this embodiment has a control current output circuit 1100, and the output currents output from the output terminals Q1 to Q4 of the control current output circuit 1100 are four control current output circuits. A reference current is input to 1400_1 to 1400_4. Then, the control current is output to the control current lines CS1 to CS16 from the control current output circuits 1400_1 to 1400_4.
[0085]
As described above, by switching the reference current and supplying it to the control current output circuits 1400_1 to 1400_4, variation in output current can be further reduced.
[0086]
Note that the configurations and driving methods of the control current output circuit 1100 and the control current output circuits 1400_1 to 1400_4 are the same as those in the configuration shown in FIGS. 1 and 2 and the driving method shown in FIG. Can do.
[0087]
In FIG. 14, the control current output circuit 1100 is configured such that the output currents of the four quasi-control current output circuits 1102_1 to 1102_4 are sequentially switched by the switching circuit 1101 every predetermined period and output from the four output terminals Q1 to Q4. However, the present invention is not limited to this.
[0088]
The control current output circuit 1100 in FIG. 14 includes m (m is a natural number) quasi-current output circuits and n (n is a natural number of m or less) switching for selecting one of the m quasi-current output circuits. Each of the n switching means may have a function of changing the selection destination of the m quasi-current output circuits every predetermined period.
[0089]
In FIG. 14, each of the control current output circuits 1400_1 to 1400_4 replaces the output currents of the four quasi-control current output circuits in order for each predetermined period by the switching circuit 1401, and four control terminals are controlled from the four output terminals. Although it is configured to output to the current line, the present invention is not limited to this.
[0090]
Each of the control current output circuits 1400_1 to 1400_4 in FIG. 14 selects f (f is a natural number) quasi-current output circuits and one of the f quasi-current output circuits (e is a natural number less than or equal to f). Each of the e switching means may have a function of changing the selection destination of the f quasi-current output circuits every predetermined period.
[0091]
In FIG. 14, only the control current output circuit 1440 corresponding to the 16 control current lines CS1 to CS16 has been described. However, in an actual display device, all control current lines for inputting a control current to each pixel are divided into a plurality of groups, and for each group, a control current output circuit 1440 having the same configuration as in FIG. The control current may be output.
[0092]
In FIG. 16A, all control current lines CS1 to CSx for inputting a control current to each pixel of the display device are divided into a plurality of groups (first group to rth (r is a natural number) group). 16 shows a configuration in which control current output circuits 1440_1 to 1440_r / 4 having the same configuration as the control current output circuit 1440 shown in FIG.
[0093]
The configurations of the control current output circuits 1440_1 to 1440_r / 4 are the same as the configuration of the control current output circuit 1440 shown in FIG. For example, in FIG. 16A, the control current output circuits 1400_B1 to 1400_B4 of each control current output circuit 1440_1 correspond to the control current output circuits 1400_1 to 1400_4 in FIG. 14, and the control current output circuit 1100_1 is the control current output in FIG. This corresponds to the current output circuit 1100.
[0094]
In the configuration of FIG. 16A, in the control current output circuits 1440_1 to 1440_r / 4 corresponding to the plurality of sets of control current lines, the reference current I0 may be input from a common reference current source circuit. .
[0095]
Further, the control current output circuits 1440_1 to 1440_r / 4 may share the reference transistor.
[0096]
FIG. 16B illustrates a structure in which the reference current source circuit 1111 and the reference transistor 1110 are shared in the control current output circuits 1440_1 to 1440_r / 4 in the structure illustrated in FIG. Note that, in the control current output circuits 1100_1 to 1100_2 in the control current output circuits 1440_1 to 1440_r / 4, the same portions as those in FIG. 14 are denoted by the same reference numerals.
[0097]
In FIG. 16B, transistors 1112_1 to 1112_4 of quasi-control current output circuits 1102_1 to 1102_4 constituting the control current output circuit 1100_1 and transistors of quasi-control current output circuits 1102_1 to 1102_4 constituting the control current output circuit 1100_2. 1112_1 to 1112_4 have their source terminals connected to the power supply line 1120 and their gate electrodes connected to the gate electrode of the reference transistor 1110.
[0098]
In FIG. 16B, the control current output circuit 1440_1 corresponding to the first to fourth sets of control current lines CS1 to CS16 and the fifth to eighth set of control current lines CS17 to CS32 are supported. The control current output circuit 1440_2 is shown as a representative. However, the transistors 1112_1 to 1112_4 constituting the quasi-control current output circuits 1102_1 to 1102_4 of the control current output circuits 1100_1 to 1100_r / 4 of all the control current output circuits 1440_1 to 1440_r / 4 have their source terminals connected to the power supply line 1120. The gate electrode is connected to the gate electrode of the reference transistor 1110.
[0099]
Thus, a transistor whose voltage equal to the gate voltage of the common reference transistor 1110 constitutes the quasi-control current output circuits 1102_1 to 1102_4 of the control current output circuits 1100_1 to 1100_r / 4 of all the control current output circuits 1440_1 to 1440_r / 4. It is applied as a gate voltage of 1112_1 to 1112_4.
[0100]
Note that in the control current output circuits 1100_1 to 1100_r / 4, the drive timing of the switching circuit 1101 can be made the same. That is, the switches SW1 to SW4 constituting the switching circuit 1101 shown in FIG. 1 may select the same timing for selecting the terminals 1 to 4 in the switching circuits 1101 of all the control current output circuits 1100_1 to 1100_r / 4. it can.
[0101]
For example, a case where the same configuration as that in FIG. 2 is used as the configuration of the switching circuit 1101 is taken as an example. At this time, the wirings A1 to A4 and the wirings A1b to A4b of the switching circuit 1101 are shared by all the switching circuits 1101 of the control current output circuits 1100_1 to 1100_r / 4.
[0102]
In this way, as shown in FIG. 3, signals are input to the wirings A1 to A4 and the wirings A1b to A4b, and the timing at which the switches SW1 to SW4 constituting the switching circuit 1101 select the terminals 1 to 4 is controlled by the control current. The output circuits 1100_1 to 1100_r / 4 can be the same in all the switching circuits 1101.
[0103]
Note that the driving timing of the switching circuit 1101 of the control current output circuits 1100_1 to 1100_r / 4 and the driving timing of the switching circuit 1401 of the control current output circuits 1400_B1 to 1400_Br can be implemented at different timings.
[0104]
With the above configuration, it is possible to output the control current averaged over time to all the control current lines CS1 to CSx formed in the pixel portion of the display device. In this manner, it is possible to reduce the visual variation in the luminance of the light emitting element of each pixel included in the display device.
[0105]
Here, in the configuration shown in FIG. 15B in the first embodiment, variations in output current between control current output circuits corresponding to different sets of control current lines are not a problem.
[0106]
On the other hand, in the present embodiment, as shown in FIG. 14, the output current from one output terminal of the control current output circuit 1100 that outputs a current that is temporally averaged with little variation is used as the control current output circuit. 1400_1 to 1400_4 or the like is used to output to a plurality of control current lines. At this time, each of the control current output circuits 1400_1 to 1400_4 also outputs a current averaged in terms of time with little variation as a control current.
[0107]
Therefore, by using the configuration of the second embodiment, variation in output current to different sets of control current lines corresponding to the control current output circuits 1440_1 to 1440_r / 4 illustrated in FIG. Can do.
[0108]
In the present embodiment, as shown in FIG. 14, by combining a plurality of control current output circuits of the present invention, a control current output circuit in which variation in output current is further reduced can be obtained.
[0109]
【Example】
Example 1
In the present embodiment, an example of a display device that includes a plurality of control current output circuits and in which the values of the control currents output from the respective control current output circuits are set to be different will be described.
[0110]
In this embodiment, a display device that inputs a digital video signal, inputs an analog current corresponding to the input digital video signal to a pixel as a control current, and performs image display will be described as an example.
[0111]
Here, the control currents output from each of the plurality of control current output circuits correspond to the gradation reference current. The gradation reference current is a current having a weighted current value corresponding to each bit from the upper bit to the lower bit of the digital video signal.
[0112]
The corresponding gradation reference current is selected according to the digital video signal. Thus, the digital video signal is converted into a corresponding analog current. An analog current is output to the control current line.
[0113]
That is, the plurality of control current output circuits shown in this embodiment function as part of a signal line driver circuit that inputs a signal current to a pixel, and the control current line corresponds to a signal line.
[0114]
FIG. 4 is a schematic diagram illustrating a configuration of the signal line driver circuit 220 included in the display device of this embodiment.
[0115]
FIG. 4 shows an example in which a 3-bit digital video signal is input and a corresponding analog current is output as a control current.
[0116]
The signal line driver circuit 220 includes a first control current output circuit 200A, a second control current output circuit 200B, a third control current output circuit 200C, a D / A conversion unit 203, a shift register 211, A first latch circuit 212 and a second latch circuit 213 are included.
[0117]
The first control current output circuit 200A includes a first quasi-control current output circuit 202A configured by four quasi-control current output circuits, and a first switching circuit 201A.
[0118]
The second control current output circuit 200B includes a second quasi-control current output circuit 202B configured by four quasi-control current output circuits, and a second switching circuit 201B.
[0119]
The third control current output circuit 200C includes a third quasi-control current output circuit 202C configured by four quasi-control current output circuits, and a third switching circuit 201C.
[0120]
In FIG. 4, the configuration of each control current output circuit (first control current output circuit 200A, second control current output circuit 200B, and third control current output circuit 200C) is almost the same as the configuration shown in the embodiment. It is the same.
[0121]
However, the current value of the current (hereinafter referred to as the first gradation reference current) output from the first control current output circuit 200A corresponds to the first bit of the digital video signal input to the display device. The weighted current value is set. The current value of the current output from the second control current output circuit 200B (hereinafter referred to as the second gradation reference current) corresponds to the second most significant bit of the digital video signal input to the display device. The weighted current value is set. The current value of the current output from the third control current output circuit 200C (hereinafter referred to as the third gradation reference current) is weighted corresponding to the third bit of the digital video signal input to the display device. Current value is set.
[0122]
In this embodiment, in each of the first control current output circuit 200A to the third control current output circuit 200C, the four output currents of the quasi-control current output circuit are supplied to the four output terminals of the control current output circuit. A configuration in which the output is switched and output is taken as an example.
[0123]
The control current output circuit of the present invention is not limited to this. m (m is a natural number) quasi-current output circuits and n (n is a natural number of m or less) switching means for selecting one from the m quasi-current output circuits, and the n switching Each of the means may have a function of changing the selection destination of the m quasi-current output circuits every predetermined period.
[0124]
In the present embodiment, the output currents of the first control current output circuit 200 </ b> A to the third control current output circuit 200 </ b> C are input to the D / A conversion unit 203.
[0125]
In addition, a 3-bit digital video signal is input to the signal line driver circuit 220 from the wirings VD1 to VD3. Here, it is assumed that a signal of the first (most significant) bit of the digital video signal is input to VD1. Assume that VD2 is input with a second bit signal of a digital video signal. Assume that VD3 is input with a signal of the third (least significant) bit of the digital video signal.
[0126]
The operation of sampling the 3-bit digital video signal input to the signal line driver circuit 220 will be described in detail below.
[0127]
In this embodiment, the display device has x (x is a natural number) columns of pixels.
[0128]
FIG. 6 illustrates a configuration example of the shift register 211, the first latch circuit 212, and the second latch circuit 213 in FIG.
[0129]
The shift register 211 receives a clock pulse S_CLK, an inverted clock pulse S_CLKB in which the polarity of the clock pulse is inverted, a start pulse S_SP, and a scanning direction switching signal L / R. Thus, the shift register outputs sequentially shifted pulses (sampling pulses) to the terminals 211_1 to 211_x.
[0130]
In FIG. 6, only a part 212_1 of the first latch circuit and a part 213_1 of the second latch circuit corresponding to a part outputting a signal to the first pixel column are shown as representatives.
[0131]
Digital video signals input to the wirings VD1 to VD3 are simultaneously held in the respective blocks 212a_1 to 212a_3 of the first latch circuit 212_1 by the sampling pulse output to the 211_1 from the shift register 211. When the first latch circuit finishes holding the 3-bit digital video signal for one pixel row, the held signal is latched by the second latch pulse LP and the inverted latch pulse LPB in which the polarity of the latch pulse is inverted. The data is transferred all at once to the blocks 213a_1 to 213a_3 of the circuit 213_1. Signals held in the respective blocks 213a_1 to 213a_3 of the second latch circuit 213_1 are output to the wiring S1d_1 to the wiring S1d_3.
[0132]
In this way, the second latch circuit 213 outputs a 3-bit digital video signal corresponding to each pixel of one pixel row all at once.
[0133]
The output of the second latch circuit 213 is input to the D / A conversion unit 203.
[0134]
Refer to FIG. 4 again.
[0135]
In the D / A conversion unit 203, the first gray scale reference current to the third gray scale reference current are selected by the digital video signal input from the second latch circuit 213. In this way, the D / A conversion unit 203 outputs an analog current (signal current) corresponding to the digital video signal to the control current lines CS1 to CS4.
[0136]
Note that as a structure of the shift register 211, the first latch circuit 212, and the second latch circuit 213 which form the signal line driver circuit, a circuit having a known structure can be freely used.
[0137]
Further, a decoder or the like can be used instead of the shift register 211.
[0138]
Specifically, the configuration of the first control current output circuit 200A, the second control current output circuit 200B, the third control current output circuit 200C, and the D / A converter 203 of the signal line driving circuit 220 having the configuration shown in FIG. A schematic circuit diagram is shown in FIG.
[0139]
The structure and operation of the signal line driver circuit 220 will be described with reference to FIG.
[0140]
The first quasi-control current output circuit 202A includes four quasi-control current output circuits 111_1 to 114_1. The second quasi-control current output circuit 202B includes four quasi-control current output circuits 111_2 to 114_2. The third quasi-control current output circuit 202C includes four quasi-control current output circuits 111_3 to 114_3.
[0141]
Since the gate electrode and the drain terminal of the reference transistor 100 are connected, the reference transistor 100 operates in a saturation region when a drain current flows. Here, the constant current I 0 input from the reference current source circuit 1111 is input between the source and drain terminals of the reference transistor 100. Thus, the reference transistor 100 allows the constant current I0 to flow as the drain current.
[0142]
In FIG. 5, the reference transistor 100, the transistors 101_1 to 104_1 included in the four quasi-control current output circuits 111_1 to 114_1 constituting the first quasi-control current output circuit 202A, and the second quasi-control current output circuit 202B are configured. The transistors 101_2 to 104_2 included in the four quasi-control current output circuits 111_2 to 114_2 and the transistors 101_3 to 104_3 included in the four quasi-control current output circuits 111_3 to 114_3 included in the third quasi-control current output circuit 202C are: The source terminal is connected to a power supply line, and the gate electrode is electrically connected.
[0143]
Thus, the gate voltage of the reference transistor 100 and the gate voltages of the transistors 101_1 to 104_1, 101_2 to 104_2, and 101_3 to 104_3 are kept equal.
[0144]
The drain terminals of the transistors 101_1 to 104_1 correspond to the output terminals of the first quasi-control current output circuit, the drain terminals of the transistors 101_2 to 104_2 correspond to the output terminals of the second quasi-control current output circuit, and the transistor 101_3 The drain terminal of ˜104_3 corresponds to the output terminal of the third quasi-control current output circuit.
[0145]
However, the gate width W1 and the gate length L1 of the transistors 101_1 to 104_1 included in the first quasi-control current output circuits 111_1 to 114_1 are all set equal. Further, the gate width W2 and the gate length L2 of the transistors 101_2 to 104_2 constituting the second quasi-control current output circuits 111_2 to 114_2 are all set equal. The gate width W3 and the gate length L3 of the transistors 101_3 to 104_3 constituting the third quasi-control current output circuits 111_3 to 114_3 are all set equal. Here, the ratio W1 / L1 of the gate width W1 and the gate length L1, the ratio W2 / L2 of the gate width W2 and the gate length L2, and the ratio W3 / L3 of the gate width W3 and the gate length L3 are set to different values. Has been.
[0146]
For example, W1 / L1: W2 / L2: W3 / L3 is set to 4 to 2 to 1. In this case, the average value I_1 of the current values I_1_1 to I4_1 output from the first quasi-control current output circuits 111_1 to 114_1 and the currents I1_2 to I4_2 output from the second quasi-control current output circuits 111_2 to 114_2. The ratio of the average value I_2 of the values and the average value I_3 of the current values of the currents I1_3 to I4_3 output from the third quasi-control current output circuits 111_3 to 114_3 can be set to 4: 1 to 1: 1.
[0147]
Here, the reference transistor 100 and the transistors 101_1 to 104_1, 101_2 to 104_2, and 101_3 to 104_3 may be either n-channel TFTs or p-channel TFTs. However, the reference transistor 100 and the transistors 101_1 to 104_1 and 101_2 may be used. The polarities of ˜104_2 and 101_3 to 104_3 must be the same.
[0148]
If the current characteristics of the transistors 101_1 to 104_1 are uniform, the current values of the currents I1_1 to I4_1 are equal. If the current characteristics of the transistors 101_2 to 104_2 are uniform, the current values of the currents I1_2 to I4_2 are equal. If the current characteristics of the transistors 101_3 to 104_3 are uniform, the current values of the currents I1_3 to I4_3 are equal. However, since the transistors 101_1 to 104_1, 101_2 to 104_2, and 101_3 to 104_3 are polycrystalline TFTs, the variations of the currents I1_1 to I4_1, the variations of the currents I1_2 to I4_2, and the variations of the currents I1_3 to I4_3 are large.
[0149]
Next, the configuration of the switches SW1_1 to SW1_3, SW2_1 to SW2_3, SW3_1 to SW3_3, and SW4_1 to SW4_3 will be described.
[0150]
With the switches SW1_1, SW2_1, SW3_1, and SW4_1, the output currents I1_1 to I4_1 of the first quasi-control current output circuits 111_1 to 114_1 are replaced with PCS1_1, PCS2_1, PCS3_1, and PCS4_1 at regular intervals, for example, every frame period. Is output.
[0151]
With the switches SW1_2, SW2_2, SW3_2, and SW4_2, the output currents I1_2 to I4_2 of the second quasi-control current output circuits 111_2 to 114_2 are replaced with PCS1_2, PCS2_2, PCS3_2, and PCS4_2 at regular intervals, for example, every frame period. Is output.
[0152]
With the switches SW1_3, SW2_3, SW3_3, and SW4_3, the output currents I1_3 to I4_3 of the third quasi-control current output circuits 111_3 to 114_3 are replaced with PCS1_3, PCS2_3, PCS3_3, and PCS4_3 at regular intervals, for example, every frame period. Is output.
[0153]
The configuration of the switches (SW1_p to SW4_p) corresponding to each of the quasi-control current output circuits (111_1 to 114_1, 111_2 to 114_2 and 111_3 to 114_3) and the driving method thereof are shown in FIG. Since it can be the same as the configuration shown by a certain SW1 to SW4 and the timing chart of FIG. 3, detailed description is omitted here.
[0154]
With the above configuration, the currents output from PCS1_1, PCS2_1, PCS3_1, and PCS4_1 corresponding to the first gradation reference current are temporally averaged. Currents output from PCS1_2, PCS2_2, PCS3_2, and PCS4_2 corresponding to the second gradation reference current are averaged over time. Currents output from PCS1_3, PCS2_3, PCS3_3, and PCS4_3 corresponding to the third gradation reference current are averaged in terms of time.
[0155]
Next, the D / A conversion unit 203 will be described.
[0156]
A portion that outputs a signal current to the control current line CS1 is configured by transistors 401_1 to 401_3.
[0157]
A digital video signal of the first bit is input to the gate electrode of the transistor 401_1 from the second latch circuit 213 through the wiring S1d_1. One of a source terminal and a drain terminal of the transistor 401_1 is connected to the PCS1_1, and the other is connected to the control current line CS1.
[0158]
The second-order bit digital video signal is input to the gate electrode of the transistor 401_2 from the second latch circuit 213 through the wiring S1d_2. One of a source terminal and a drain terminal of the transistor 401_2 is connected to the PCS1_2, and the other is connected to the control current line CS1.
[0159]
A third-bit digital video signal is input to the gate electrode of the transistor 401_3 from the second latch circuit 213 through the wiring S1d_3. One of a source terminal and a drain terminal of the transistor 401_3 is connected to the PCS1_3, and the other is connected to the control current line CS1.
[0160]
The part corresponding to the control current lines CS2 to CS4 is the same as the part corresponding to the control current line CS1.
[0161]
In part of the D / A converter 203 that outputs a signal current to the control current line CS1, among the transistors 401_1 to 401_3, a digital video signal input from the second latch circuit 213 via the wirings S1d_1 to S1d_3 is used. The first gray scale reference current to the third gray scale reference current selectively flow through the transistor which is turned on. Thus, an analog signal current corresponding to the digital video signal is output to the control current line CS1.
[0162]
Similarly, analog signal currents corresponding to digital video signals are output from the control current lines CS2 to CS4.
[0163]
In this way, in a pixel to which an analog signal current output to each of the control current lines CS1 to CS4 is input, variation in luminance of the light emitting element can be visually reduced.
[0164]
In this embodiment, only the control current output circuits corresponding to the four control current lines are shown as representatives. In general, all control current lines for inputting a control current to each pixel of the display device are divided into a plurality of groups, and in each group, a control current is output from a control current output circuit having the same configuration as in FIGS. Is output.
[0165]
In this manner, it is possible to reduce the visual variation in the luminance of the light emitting element of each pixel included in the display device.
[0166]
Note that as a pixel configuration of the display device in this embodiment, a pixel of a type that displays an analog signal current as a control current for controlling light emission luminance of a light emitting element of each pixel and can perform display can be freely used. . For example, in the conventional example, a pixel having a configuration as shown in FIG. 7 can be used.
[0167]
In the present embodiment, a signal control circuit having a configuration in which one reference current source circuit is shared by a plurality of control current output circuits and a plurality of gradation reference currents is generated is shown as an example. It is not limited to. The present invention can be easily applied to a signal line driving circuit having a configuration in which a reference current source circuit that outputs currents having different current values is provided for each of a plurality of control current output circuits.
[0168]
(Example 2)
In this embodiment, a method for manufacturing a pixel portion and a driver circuit portion of a display device of the present invention over a substrate having an insulating surface using a TFT will be described.
[0169]
In this embodiment, for simplicity, a switching transistor that selects input of a signal current to the pixel, a driving transistor that supplies current to the light emitting element, and a light emitting element are representatively shown as elements constituting the pixel. In addition, a CMOS circuit including an n-channel transistor and a p-channel transistor is typically shown as an element constituting the driver circuit portion.
[0170]
First, as shown in FIG. 9A, a silicon oxide film is formed on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass, A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 5002a made of O is formed to 10 to 200 [nm] (preferably 50 to 100 [nm]), and similarly SiH _Four , N ₂ A silicon oxynitride silicon film 5002b formed from O is stacked to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.
[0171]
Next, a semiconductor film having an amorphous structure is formed and patterned as island-shaped semiconductor layers 5003 to 5006. Then, a semiconductor film having an amorphous structure is crystallized by using a laser crystallization method or a known thermal crystallization method to form a crystalline semiconductor film. The island-like semiconductor layers 5003 to 5006 are formed with a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.
[0172]
In order to fabricate a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four Use a laser. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz] and the laser energy density is 100 to 400 [mJ / cm. ² ] (Typically 200-300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is set to 1 to 10 [kHz], and the laser energy density is set to 300 to 600 [mJ / cm. ² ] (Typically 350-500 [mJ / cm ² ]) Then, a laser beam focused in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the overlay rate of the linear laser beam at this time is 50. Perform as ~ 98 [%].
[0173]
Next, a gate insulating film 5007 is formed to cover the island-shaped semiconductor layers 5003 to 5006. The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ And a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], a high frequency (13.56 [MHz]), and a power density of 0.5 to 0.8 [W / cm]. ² ] Can be formed by discharging. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].
[0174]
Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed with Ta to a thickness of 50 to 100 [nm], and the second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].
[0175]
The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.
[0176]
When forming a W film, it is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 [μΩcm] or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. From this, in the case of the sputtering method, by using a W target having a purity of 99.9999 [%] and further forming a W film with sufficient consideration so that impurities are not mixed in from the gas phase during film formation, A resistivity of 9 to 20 [μΩcm] can be realized.
[0177]
Note that in this embodiment, the first conductive film 5008 is Ta and the second conductive film 5009 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a desirable example of a combination other than this embodiment, a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN), the second conductive film 5009 is W, and the first conductive film 5008 is nitrided. A combination of tantalum (TaN) and the second conductive film 5009 made of Al, a combination of the first conductive film 5008 made of tantalum nitride (TaN) and the second conductive film 5009 made of Cu can be given. .
[0178]
Next, a mask 5010 is formed using a resist, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF is used as an etching gas. _Four And Cl ₂ Then, 500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1 [Pa] to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ When W is mixed, the W film and the Ta film are etched to the same extent.
[0179]
Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the overetching process. become. Thus, the first shape conductive layers 5011 to 5016 (the first conductive layers 5011a to 5016a and the second conductive layers 5011b to 5016b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched and thinned by about 20 to 50 [nm]. (Fig. 9 (B))
[0180]
Then, a first doping process is performed, and an impurity element imparting n-type conductivity is added. As a doping method, an ion doping method or an ion implantation method may be used. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁴ [atoms / cm ² The acceleration voltage is set to 60 to 100 [keV]. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 5011 to 5015 serve as a mask for the impurity element imparting n-type, and the first impurity regions 5017 to 5025 are formed in a self-aligning manner. The first impurity regions 5017 to 5025 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} [atoms / cm ^Three An impurity element imparting n-type is added in a concentration range of (Fig. 9 (B))
[0181]
Next, as shown in FIG. 9C, a second etching process is performed without removing the resist mask. CF as etching gas _Four And Cl ₂ And O ₂ Then, the W film is selectively etched. At this time, second shape conductive layers 5026 to 5031 (first conductive layers 5026a to 5031a and second conductive layers 5026b to 5031b) are formed by the second etching process. At this time, in the gate insulating film 5007, a region that is not covered with the second shape conductive layers 5026 to 5031 is further etched and thinned by about 20 to 50 [nm].
[0182]
CF of W film and Ta film _Four And Cl ₂ The etching reaction by the mixed gas can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressure of fluoride and chloride of W and Ta, WF, which is fluoride of W ₆ Is extremely high, other WCl _Five , TaF _Five , TaCl _Five Are comparable. Therefore, CF _Four And Cl ₂ With this mixed gas, both the W film and the Ta film are etched. However, an appropriate amount of O is added to this mixed gas. ₂ When CF is added _Four And O ₂ Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, O ₂ When Ta is added, the surface of Ta is oxidized. Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.
[0183]
Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 [keV] and 1 × 10 ¹³ [atoms / cm ² A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 9B. Doping is performed using the second shape conductive layers 5026 to 5030 as masks against the impurity elements so that the impurity elements are also added to the lower regions of the first conductive layers 5026a to 5030a. Thus, third impurity regions 5032 to 5036 are formed. The concentration of phosphorus (P) added to the third impurity regions 5032 to 5036 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 5026a to 5030a. Note that, in the semiconductor layer overlapping the tapered portions of the first conductive layers 5026a to 5030a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 5026a to 5030a, The concentration is similar.
[0184]
A third etching process is performed as shown in FIG. CHF as etching gas _Three And using a reactive ion etching method (RIE method). By the third etching treatment, the tapered portions of the first conductive layers 5026a to 5031a are partially etched, and a region where the first conductive layer overlaps with the semiconductor layer is reduced. Through the third etching treatment, third-shaped conductive layers 5037 to 5042 (first conductive layers 5037a to 5042a and second conductive layers 5037b to 5042b) are formed. At this time, in the gate insulating film 5007, regions that are not covered with the third shape conductive layers 5037 to 5042 are further etched by about 20 to 50 [nm] to form thin regions.
[0185]
In the third impurity regions 5032 to 5036 before the third etching by the third etching treatment, the third impurity regions 5032a to 5036a overlapping with the first conductive layers 5037a to 5041a, and the first impurity regions Second impurity regions 5032b to 5036b between the third impurity regions are formed.
[0186]
Then, as shown in FIG. 10C, fourth impurity regions 5043 to 5054 having a conductivity type opposite to the first conductivity type are formed in the island-like semiconductor layers 5004 and 5006 forming the p-channel TFT. . Using the third shape conductive layers 5038b and 5041b as masks against the impurity element, impurity regions are formed in a self-aligning manner. At this time, the island-shaped semiconductor layers 5003 and 5005 and the wiring portion 5042 forming the n-channel TFT are covered with the resist mask 5200 in advance. The impurity regions 5043 to 5054 have already been doped with phosphorus at different concentrations, but diborane (B ₂ H ₆ ) And the impurity concentration is 2 × 10 5 in any region by ion doping. ²⁰ ~ 2x10 ^{twenty one} [atoms / cm ^Three ] To form.
[0187]
Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 5037 to 5041 overlapping with the island-shaped semiconductor layers function as gate electrodes. Reference numeral 5042 functions as an island-shaped signal line.
[0188]
After removing the resist mask 5200, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.], In this embodiment, heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for the third shape conductive layers 5037 to 5042 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done.
[0189]
Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100 [%] hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0190]
Next, as shown in FIG. 11A, a first interlayer insulating film 5055 is formed from a silicon oxynitride film to a thickness of 100 to 200 [nm]. A second interlayer insulating film 5056 made of an organic insulating material is formed thereon, and then contact holes are formed in the first interlayer insulating film 5055, the second interlayer insulating film 5056, and the gate insulating film 5007. After each wiring (including connection wiring and signal lines) 5057 to 5062 and 5064 is formed by patterning, a pixel electrode 5063 in contact with the connection wiring 5062 is formed by patterning.
[0191]
As the second interlayer insulating film 5056, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5056 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably it may be 1-5 [μm] (more preferably 2-4 [μm]).
[0192]
The contact holes are formed by dry etching or wet etching. The contact holes reach the n-type impurity regions 5017, 5018, 5021, and 5023 and the p-type impurity regions 5043 to 5054, contact holes that reach the wiring 5042, and power supply lines. A contact hole (not shown) reaching the gate electrode and a contact hole (not shown) reaching the gate electrode are formed.
[0193]
Further, as wirings (connection wirings) 5057 to 5062 and 5064, a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering. A film obtained by patterning a laminated film into a desired shape is used. Of course, other conductive films may be used.
[0194]
In this embodiment, an ITO film having a thickness of 110 [nm] is formed as the pixel electrode 5063 and patterned. A contact is made by arranging the pixel electrode 5063 so as to be in contact with and overlapping with the connection wiring 5062. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 5063 becomes the anode of the light emitting element. (Fig. 11 (A))
[0195]
Next, as shown in FIG. 11B, an insulating film containing silicon (silicon oxide film in this embodiment) is formed to a thickness of 500 nm, and an opening is formed at a position corresponding to the pixel electrode 5063. Then, a third interlayer insulating film 5065 functioning as a bank is formed. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. Care must be taken because the deterioration of the organic compound layer due to the step becomes a significant problem unless the side wall of the opening is sufficiently gentle.
[0196]
Next, the organic compound layer 5066 and the cathode (MgAg electrode) 5067 are continuously formed by using a vacuum evaporation method without being released to the atmosphere. The thickness of the organic compound layer 5066 is 80 to 200 [nm] (typically 100 to 120 [nm]), and the thickness of the cathode 5067 is 180 to 300 [nm] (typically 200 to 250 [nm]. nm]).
[0197]
In this step, an organic compound layer and a cathode are sequentially formed for the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the organic compound layer has poor resistance to the solution, it must be formed for each color individually without using the photolithography technique. Therefore, it is preferable to use a metal mask to hide other than the desired pixels and to selectively form the organic compound layer and the cathode only at necessary portions.
[0198]
That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic compound layer that emits red light is selectively formed using the mask. Next, a mask that hides all pixels other than those corresponding to green is set, and an organic compound layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light-emitting organic compound layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used.
[0199]
Here, a method of forming three types of light emitting elements corresponding to RGB is used, but a method of combining a white light emitting element and a color filter, a blue or blue green light emitting element and a phosphor (fluorescent color conversion). Layer: CCM), a method of using a transparent electrode as a cathode (counter electrode), and a method of superimposing light emitting elements corresponding to RGB may be used.
[0200]
Note that a known material can be used for the organic compound layer 5066. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic compound layer.
[0201]
Next, a cathode 5067 is formed. In this embodiment, MgAg is used as the cathode 5067, but the present invention is not limited to this. Other known materials may be used for the cathode 5067.
[0202]
Finally, a passivation film 5068 made of a silicon nitride film is formed to a thickness of 300 [nm]. By forming the passivation film 5068, the organic compound layer 5066 can be protected from moisture and the like, and the reliability of the light-emitting element can be further improved.
[0203]
Thus, a display device having a structure as shown in FIG. 11B is completed. Note that in the manufacturing process of the display device in this embodiment, signal lines are formed of Ta and W, which are materials forming the gate electrode, and drain / source electrodes are formed because of the circuit configuration and process. Although the gate signal line is formed of Al which is the wiring material being used, a different material may be used.
[0204]
By the way, in the display device of this embodiment, the TFT having the optimum structure is arranged not only in the pixel portion but also in the drive circuit portion, so that it can show very high reliability and can improve the operation characteristics. In addition, it is possible to increase the crystallinity by adding a metal catalyst such as Ni in the crystallization step. Thereby, the driving frequency of the signal line driving circuit can be increased to 10 [MHz] or more.
[0205]
First, a TFT having a structure that reduces hot carrier injection so as not to reduce the operating speed as much as possible is used as an n-channel TFT of a CMOS circuit that forms a drive circuit portion.
[0206]
In this embodiment, the active layer of the n-channel TFT has an overlap LDD region (L that overlaps the gate electrode with the source region, drain region, and gate insulating film interposed therebetween. _OV Region), an offset LDD region (L _OFF Region) and a channel formation region.
[0207]
In addition, since the p-channel TFT of the CMOS circuit is hardly concerned with deterioration due to hot carrier injection, it is not particularly necessary to provide an LDD region. Needless to say, it is possible to provide an LDD region as in the case of the n-channel TFT and take measures against hot carriers.
[0208]
In addition, when the driving circuit uses a CMOS circuit in which a current flows bidirectionally in the channel formation region, that is, a CMOS circuit in which the roles of the source region and the drain region are switched, an n-channel TFT that forms the CMOS circuit In this case, it is preferable to form the LDD region in such a manner that the channel formation region is sandwiched between both sides of the channel formation region. In the case where a CMOS circuit that needs to keep off current as low as possible is used in the driver circuit, the n-channel TFT forming the CMOS circuit is L _OV It is preferable to have a region.
[0209]
Actually, when the state shown in FIG. 11B is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting material having high hermeticity and low degassing so as not to be exposed to the outside air. It is preferable to package (enclose) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the light emitting element is improved.
[0210]
In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal drawn from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product.
[0211]
Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a display device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0212]
This embodiment can be implemented by freely combining with the first embodiment.
[0213]
(Example 3)
In this embodiment, a method for sealing a display device will be described with reference to FIGS. Here, the pixel portion and the drive circuit portion provided in the periphery thereof are formed on the insulating substrate using TFTs.
[0214]
12A is a top view of the display device, FIG. 12B is a cross-sectional view taken along the line AA ′ in FIG. 12A, and FIG. 12C is a cross-sectional view taken along the line B- in FIG. It is sectional drawing in B '.
[0215]
A sealant is provided so as to surround the pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004 (the first scan line driver circuit 4004a and the second scan line driver circuit 4004b) provided over the substrate 4001. 4009 is provided. A sealing material 4008 is provided over the pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004 are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealing material 4008.
[0216]
The pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004a, and the second signal line driver circuit 4004b provided over the substrate 4001 include a plurality of TFTs. 12B, typically, driver circuit transistors included in the signal line driver circuit 4003 (note that n-channel TFTs and p-channel TFTs are illustrated here) 4201 formed over the base film 4010; A driving transistor 4202 included in the pixel portion 4002 is illustrated.
[0217]
In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driver circuit transistor 4201, and a p-channel TFT manufactured by a known method is used for the driving transistor 4202. . The pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving transistor 4202.
[0218]
An interlayer insulating film (planarization film) 4301 is formed over the driver circuit transistor 4201 and the driver transistor 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the driver transistor 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0219]
An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic compound layer 4204 is formed on the pixel electrode 4203. A known organic material or inorganic material can be used for the organic compound layer 4204. In addition, organic materials include low molecular (monomer) materials and high molecular (polymer) materials, either of which may be used.
[0220]
As a method for forming the organic compound layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic compound layer may be a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0221]
On the organic compound layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic compound layer 4204 as much as possible. Therefore, it is necessary to devise such that the organic compound layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0222]
As described above, a light-emitting element 4303 including the pixel electrode (anode) 4203, the organic compound layer 4204, and the cathode 4205 is formed. A protective film 4303 is formed over the insulating film 4302 so as to cover the light emitting element 4303. The protective film 4303 is effective in preventing oxygen, moisture, and the like from entering the light emitting element 4303.
[0223]
Reference numeral 4005 a denotes a lead wiring connected to the power supply line, which is electrically connected to the source region of the driving transistor 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.
[0224]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0225]
However, when the radiation direction of light from the light emitting element 4303 is directed to the cover material side, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.
[0226]
As the filler 4103, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0227]
Further, in order to expose the filler 4103 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is placed. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.
[0228]
As shown in FIG. 12C, the conductive film 4203a is formed to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0229]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0230]
This embodiment can be implemented by freely combining with Embodiments 1 and 2.
[0231]
(Example 4)
In this embodiment, a cross-sectional view of a pixel of a display device of the present invention is described with reference to FIG. Note that in this embodiment, only a light-emitting element and a transistor connected to a pixel electrode of the light-emitting element are shown as elements constituting the pixel of the display device.
[0232]
In FIG. 17A, a transistor (driving transistor) 1601 is formed over a pixel substrate 1600.
[0233]
The driving transistor 1601 includes a gate electrode 1603, an insulating film 1605, and a channel formation region 1604b. One of a source region and a drain region of the driving transistor 1601 is 1604a, and the other is 1604c. The channel formation region 1604b and 1604a and 1604c corresponding to the source region and the drain region, respectively, are formed of a thin film semiconductor layer. An interlayer film 1606 is formed over the driving transistor 1601.
[0234]
Note that the driving transistor 1601 is not limited to the structure illustrated in the drawing, and a TFT having a known structure can be used freely. For example, the driving transistor 1601 is a single-gate TFT, but may be a multi-gate TFT. Further, the driving transistor 1601 is a top gate type TFT, but may be a bottom gate type TFT. Furthermore, a dual gate TFT having two gate electrodes disposed above and below the channel region with a gate insulating film interposed therebetween may be used.
[0235]
Next, the pixel electrode 1608 is formed by patterning a reflective material into a desired shape. Here, the pixel electrode 1608 is an anode. Contact holes reaching the source and drain regions of the drive transistor, 1604a and 1604c are formed in the interlayer film 1606, and a laminated film made of Ti and Ti containing Ti and Ti is formed and patterned into a desired shape. A wiring 1607 and a wiring 1609 are formed. The wiring 1609 and the pixel electrode 1608 are brought into conduction by being in contact with each other.
[0236]
Subsequently, an insulating film made of an organic resin material such as photosensitive acrylic is formed, and an opening is formed at a position corresponding to the pixel electrode 1608 of the light-emitting element 1614, whereby the insulating film 1610 is formed.
[0237]
At this time, the lower end portion of the opening portion of the insulating film is in contact with the upper surface of the pixel electrode 1608, and the center of curvature above the tangent line between the pixel electrode and the lower end portion (O ₁ ) And the first radius of curvature (R ₁ ). The upper end of the opening of the insulating film has a center of curvature (O) below the tangent line between the upper end and the upper surface of the insulating film. ₂ ) And the second radius of curvature (R ₂ ). Note that the first radius of curvature (R) can be used as a curvature radius that can be controlled in an actual process, whether it is etching using an aqueous solution of acid, base or the like, or etching using a reactive gas. ₁ ) Is preferably 0.2 μm or more and 3.0 μm or less.
[0238]
Since the lower end of the opening of the insulating film has a gently curved shape that changes continuously, the coverage of the light emitting layer formed in the opening is improved, and disconnection of the light emitting layer at the lower end can be prevented. it can. Thereby, the short circuit between the pixel electrode and the cathode due to the disconnection of the light emitting layer is reduced. In addition, the light emitting layer can be prevented from being partially thinned, and local electric field concentration in the light emitting layer can be prevented.
[0239]
Next, after the organic compound layer 1611 is formed, the counter electrode (cathode) 1612 of the light-emitting element 1614 is formed using a cesium (Cs) film having a thickness of 2 [nm] or less and silver ( Ag) A film is formed by a laminated film formed in order. By making the thickness of the counter electrode 1612 of the light emitting element 1614 extremely small, light generated in the light emitting layer 1611 is transmitted through the counter electrode 1612 and is emitted in a direction opposite to that of the pixel substrate 1600. Next, a protective film 1613 is formed for the purpose of protecting the light emitting element 1614.
[0240]
As described above, in the case of a display device that emits light in a direction opposite to that of the pixel substrate 1600, elements such as the driving transistor 1601 formed on the pixel substrate 1600 side with respect to the light-emitting element 1614 can be used. Since it is not necessary to visually recognize the light emission of the light emitting element 1614, the aperture ratio can be increased.
[0241]
Note that TiN or the like is used as a material for the pixel electrode 1608, the pixel electrode is used as a cathode, and the counter electrode 1612 is formed using a transparent conductive film typified by ITO or the like as an anode. In this manner, the light emitted from the organic compound layer 1611 may be emitted from the anode side in the direction opposite to the pixel substrate 1600.
[0242]
FIG. 17B is a cross-sectional view illustrating the structure of a pixel including a light-emitting element having a structure different from that in FIG. 17B, the same portions as those in FIG. 17A are described using the same reference numerals, and the structure shown in FIG. 17A is used until the driver transistor 1601 is formed and the interlayer film 1606 is formed. It can be similarly produced.
[0243]
Next, contact holes reaching the source and drain regions 1604 a and 1604 c of the driving transistor 1601 are formed in the interlayer film 1606. After that, a laminated film made of Ti or Ti containing Ti and Ti is formed, and then a transparent conductive film typified by ITO or the like is formed. Ti or a laminated film composed of Ti containing Ti and Ti, and a transparent conductive film typified by ITO or the like are patterned into a desired shape, and a wiring 1621 composed of 1617 and 1618, a wiring 1619, A pixel electrode 1620 is formed. The pixel electrode 1620 corresponds to the anode of the light emitting element 1624.
[0244]
Subsequently, an insulating film made of an organic resin material such as photosensitive acrylic is formed, and an opening is formed at a position corresponding to the pixel electrode 1620 of the light emitting element 1624 to form an insulating film 1610. Here, in order to avoid problems such as deterioration of the organic compound layer and step breakage due to the step of the side wall of the opening, the opening has a sufficiently gentle tapered side wall as shown in FIG. Form to have.
[0245]
Next, after the organic compound layer 1611 is formed, the counter electrode (cathode) 1612 of the light-emitting element 1624 is formed using a cesium (Cs) film having a thickness of 2 [nm] or less and silver ( Ag) A film is formed by a laminated film formed in order. By making the thickness of the counter electrode 1612 of the light emitting element 1624 extremely small, light generated in the light emitting layer 1611 is transmitted through the counter electrode 1612 and emitted in a direction opposite to that of the pixel substrate 1600. Next, a protective film 1613 is formed for the purpose of protecting the light emitting element 1624.
[0246]
As described above, in the case of a display device that emits light in a direction opposite to that of the pixel substrate 1600, with respect to the light-emitting element 1624, elements such as the driving transistor 1601 formed on the pixel substrate 1600 side are used. Since it is not necessary to visually recognize the light emission of the light emitting element 1624, the aperture ratio can be increased.
[0247]
In the structure in FIG. 17B, the wiring 1619 connected to the source region or the drain region of the driver transistor and the pixel electrode 1620 are patterned using a common photomask as compared with the structure in FIG. Since it can be formed, a photomask required in the manufacturing process can be reduced and the process can be simplified.
[0248]
This embodiment can be implemented by freely combining with Embodiments 1 to 3.
[0249]
(Example 5)
In this embodiment, a cross-sectional view of a pixel of a display device of the present invention having a different structure from that shown in FIG. 17 is described with reference to FIG. In addition, the same part as FIG. 17 is shown using the same code | symbol.
[0250]
In this embodiment, only a light-emitting element and a transistor connected to a pixel electrode of the light-emitting element are shown as elements constituting the pixel of the display device.
[0251]
In FIG. 18, a transistor (driving transistor) 1601 is formed on a pixel substrate 1600. The driving transistor 1601 includes a gate electrode 1603, an insulating film 1605, and a channel formation region 1604b. One of a source region and a drain region of the driving transistor 1601 is 1604a, and the other is 1604c. The channel formation region 1604b and 1604a and 1604c corresponding to the source region and the drain region, respectively, are formed of a thin film semiconductor layer. A first interlayer film 1606 is formed over the driving transistor 1601.
[0252]
Note that the driving transistor 1601 is not limited to the structure illustrated in the drawing, and a TFT having a known structure can be used freely. For example, in FIG. 18, the driving transistor 1601 is a single gate type TFT, but may be a multi gate type TFT. In FIG. 18, the driving transistor 1601 is a top gate TFT, but may be a bottom gate TFT. Furthermore, a dual gate TFT having two gate electrodes disposed above and below the channel region with a gate insulating film interposed therebetween may be used.
[0253]
Contact holes reaching the source and drain regions 1604a and 1604c of the driving transistor 1601 are formed in the first interlayer film 1606, a wiring layer is formed, and patterned into a desired shape to form wirings 1667a and 1667b. . Then, a second interlayer film 1666 is formed over the wirings 1667a and 1667b.
[0254]
Next, the pixel electrode 1608 is formed by patterning a reflective material into a desired shape. Here, the pixel electrode 1608 is an anode. A contact hole reaching the wiring 1667b is formed in the second interlayer film 1666, a laminated film made of Ti and Ti containing Ti and Ti is formed, and patterned into a desired shape to form a wiring 1669. The wiring 1669 and the pixel electrode 1608 are brought into conduction by being in contact with each other.
[0255]
Subsequently, an insulating film made of an organic resin material such as photosensitive acrylic is formed, and an opening is formed at a position corresponding to the pixel electrode 1608 of the light-emitting element 1614, whereby the insulating film 1610 is formed. Here, in order to avoid problems such as degradation of the organic compound layer and step breakage due to the step of the side wall of the opening, the opening has a sufficiently gentle tapered side wall as shown in FIG. It forms so that it may have.
[0256]
Next, after the organic compound layer 1611 is formed, the counter electrode (cathode) 1612 of the light-emitting element 1614 is formed using a cesium (Cs) film having a thickness of 2 [nm] or less and silver ( Ag) A film is formed by a laminated film formed in order. By making the thickness of the counter electrode 1612 of the light emitting element 1614 extremely small, light generated in the light emitting layer 1611 is transmitted through the counter electrode 1612 and is emitted in a direction opposite to that of the pixel substrate 1600. Next, a protective film 1613 is formed for the purpose of protecting the light emitting element 1614.
[0257]
As described above, in the case of a display device that emits light in a direction opposite to that of the pixel substrate 1600, elements such as the driving transistor 1601 formed on the pixel substrate 1600 side with respect to the light-emitting element 1614 can be used. Since it is not necessary to visually recognize the light emission of the light emitting element 1614, the aperture ratio can be increased.
[0258]
Note that TiN or the like is used as a material for the pixel electrode 1608, the pixel electrode is used as a cathode, and the counter electrode 1612 is formed using a transparent conductive film typified by ITO or the like as an anode. In this manner, the light emitted from the light emitting layer 1611 may be emitted from the anode side in the direction opposite to the pixel substrate 1600.
[0259]
In the configuration shown in FIG. 18 in this embodiment, the wiring layer is increased and the wiring 1667a is formed as compared with the configuration shown in FIG. 17 in Embodiment 4. Therefore, as compared with the structure in FIG. 17, the pixel electrode can be formed above the wiring 1667a in the structure in FIG. Thus, the aperture ratio can be increased.
[0260]
This embodiment can be implemented by freely combining with Embodiments 1 to 3.
[0261]
(Example 6)
In this embodiment, an example of color display of the display device of the present invention will be described with reference to FIG. FIG. 19 is a cross-sectional view of a pixel of the display device.
[0262]
In this embodiment, only three pixels of the OLED display device are shown as representatives, and only the light-emitting elements and the transistors connected to the pixel electrodes of the light-emitting elements are shown as elements constituting each pixel.
[0263]
In FIG. 19, transistors (drive transistors) 1901_R, 1901_G, and 1901_B are formed over a pixel substrate 1900. A first interlayer film 1910 is formed over the driving transistors 1901_R, 1901_G, and 1901_B.
[0264]
Note that the driving transistors 1901_R, 1901_G, and 1901_B are not limited to the structures shown in the drawing, and TFTs having a known structure can be used freely. For example, although the drive transistors 1901_R, 1901_G, and 1901_B in FIG. 19 are single-gate TFTs, they may be multi-gate TFTs. In FIG. 19, the driving transistors 1901_R, 1901_G, and 1901_B are top-gate TFTs, but may be bottom-gate TFTs. Furthermore, a dual gate TFT having two gate electrodes disposed above and below the channel region with a gate insulating film interposed therebetween may be used.
[0265]
In the first interlayer film 1910, contact holes reaching the source region or the drain region of the driving transistors 1901_R, 1901_G, and 1901_B are formed, a wiring layer is formed, and patterned into a desired shape, and the wirings 1919_R, 1919_G, and 1919_B are formed. Form. Then, a second interlayer film 1911 is formed over the wirings 1919_R, 1919_G, and 1919_B.
[0266]
Next, contact holes reaching the wirings 1919_R, 1919_G, and 1919_B are formed in the second interlayer film 1911, and pixel electrodes 1912_R, 1912_G, and 1912_B are formed. Here, the pixel electrodes 1912_R, 1912_G, and 1912_B are anodes.
[0267]
Note that the second interlayer film 1911 may not be provided. That is, the pixel electrodes 1912_R, 1912_G, and 1912_B may be formed in the same layer as the wirings 1919_R, 1919_G, and 1919_B.
[0268]
Next, a red light-emitting organic compound layer 1914_R is formed. Next, a green light-emitting organic compound layer 1914_G is formed. Next, a blue light-emitting organic compound layer 1914_B is formed. After that, the counter electrode 1915 of the light emitting element 1614 is formed.
[0269]
Thus, a light-emitting element that emits red light, which includes the pixel electrode 1912_R, the red light-emitting organic compound layer 1914_R, and the counter electrode 1915, is formed. A light-emitting element that emits green light, which includes the pixel electrode 1912_G, the organic compound layer 1914_G that emits green light, and the counter electrode 1915, is formed. A light-emitting element that emits blue light, which includes the pixel electrode 1912_B, the blue-light-emitting organic compound layer 1914_B, and the counter electrode 1915, is formed.
[0270]
As in this embodiment, when the organic compound layers 1914_R, 1914_G, and 1914_B are formed (separated), the organic compound layers 1914_R, 1914_G, and 1914_B are overlapped at the boundary.
[0271]
With the above structure, it is possible to reduce the margin for separately coating the organic compound layer and increase the area of the light emitting region in the pixel.
[0272]
This embodiment can be implemented by freely combining with Embodiments 1 to 5.
[0273]
(Example 7)
In this embodiment, examples of electronic devices of the present invention will be described with reference to FIGS.
[0274]
Examples of the electronic device of the present invention include a portable information terminal, a personal computer, an image reproducing device, a television, a head mounted display, a video camera, and the like.
[0275]
FIG. 13A shows a schematic diagram of a portable information terminal of the present invention. The portable information terminal includes a main body 4601a, an operation switch 4601b, a power switch 4601c, an antenna 4601d, a display unit 4601e, and an external input port 4601f. The display device having the structure described in Embodiment Mode and Examples 1 to 6 is used for the display portion 4601e.
[0276]
FIG. 13B shows a schematic diagram of a personal computer of the present invention. The personal computer includes a main body 4602a, a housing 4602b, a display portion 4602c, operation switches 4602d, a power switch 4602e, and an external input port 4602f. The display device having the structure described in Embodiment Mode and Examples 1 to 6 is used for the display portion 4602c.
[0277]
FIG. 13C shows a schematic diagram of the image reproducing apparatus of the present invention. The image playback device includes a main body 4603a, a housing 4603b, a recording medium 4603c, a display unit 4603d, an audio output unit 4603e, and an operation switch 4603f. The display device having the structure described in Embodiment Mode and Examples 1 to 6 is used for the display portion 4603d.
[0278]
FIG. 13D is a schematic diagram of the television of the present invention. The television set includes a main body 4604a, a housing 4604b, a display portion 4604c, and operation switches 4604d. The display device having the structure described in Embodiment Mode and Examples 1 to 6 is used for the display portion 4604c.
[0279]
FIG. 13E shows a schematic diagram of the head mounted display of the present invention. The head mounted display includes a main body 4605a, a monitor unit 4605b, a head fixing band 4605c, a display unit 4605d, and an optical system 4605e. The display device having the structure described in Embodiment Mode and Examples 1 to 6 is used for the display portion 4605d.
[0280]
FIG. 13F shows a schematic diagram of a video camera of the present invention. The video camera includes a main body 4606a, a housing 4606b, a connection unit 4606c, an image receiving unit 4606d, an eyepiece unit 4606e, a battery 4606f, an audio input unit 4606g, and a display unit 4606h. The display device having the structure described in the embodiment mode and Examples 1 to 6 is used for the display portion 4606h.
[0281]
The present invention is not limited to the electronic devices described above, and various electronic devices using the display devices having the configurations shown in the embodiment modes and Examples 1 to 6 can be used.
[0282]
(Example 8)
In this example, an actual structure of the signal line driver circuit (control current output circuit) of the present invention shown in Embodiment Mode 1 is described with reference to FIG.
[0283]
FIG. 20 is a top view of a part of the signal line driver circuit, and includes a plurality of current sources (corresponding to the quasi-control current output circuit 1102 in FIG. 1) and a switching circuit (1101 in FIG. 1) connected to the current sources. Equivalent). In FIG. 1, four transistors constituting the current source (corresponding to 1112 in FIG. 1) form one set, but in FIG. 20, 12 transistors arranged for each RGB are used for full color display. One set is formed (however, only seven transistors are shown in FIG. 20 due to restrictions on the drawing).
[0284]
A plurality of analog switches as shown in FIG. 2 are connected to the switching circuit using wires. The electrical connection between the current source and the signal line (not shown in FIG. 20) is switched by the switching circuit, that is, the connection of the analog switch and the wiring.
[0285]
FIG. 21A illustrates an analog switch including an n-channel thin film transistor and a p-channel thin film transistor. Further, FIG. 21B shows an n-channel thin film transistor as a current source. Note that in order to reduce the variation of the thin film transistor of the current source, the channel length (L) and the channel width (W) of the channel formation region of the TFT are increased (particularly, the channel length is set to 100 μm).
[0286]
The p-channel thin film transistor and the n-channel thin film transistor as described above may be formed using the manufacturing method described in Embodiment 2.
[0287]
【The invention's effect】
The present invention can provide a control current output circuit that is manufactured using a polycrystalline TFT and suppresses variations in output control current with the above-described configuration.
[0288]
Further, in the display device using the control current output circuit, it is possible to visually reduce the variation in the light emission luminance of the light emitting element of the pixel. Thus, a display device that can be reduced in size and reduced in power consumption and an electronic device using the display device can be provided.
[0289]
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG. 2 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG. 3 is a timing chart showing a method for driving a control current output circuit of the present invention.
FIG. 4 is a schematic diagram showing a configuration of a control current output circuit of the present invention.
FIG. 5 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG. 6 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG. 7 illustrates a structure of a pixel of a display device.
FIG. 8 is a block diagram illustrating a configuration of a conventional display device.
FIGS. 9A to 9C are diagrams illustrating a manufacturing process of a display device of the present invention. FIGS.
10A and 10B illustrate a manufacturing process of a display device of the present invention.
11A to 11C illustrate a manufacturing process of a display device of the present invention.
12A and 12B are a top view and a cross-sectional view illustrating a structure of a display device of the invention.
FIG. 13 illustrates an electronic device of the present invention.
FIG. 14 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG. 15 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG. 16 is a diagram showing a configuration of a control current output circuit of the present invention.
FIG 17 is a cross-sectional view illustrating a structure of a display device of the invention.
FIG 18 is a cross-sectional view illustrating a structure of a display device of the invention.
FIG 19 is a cross-sectional view illustrating a structure of a display device of the invention.
FIG. 20 is a top view illustrating a structure of a display device of the present invention.
FIG. 21 is a top view illustrating a structure of a display device of the present invention.

Claims (4)

A plurality of current output circuits;
A signal line driving circuit having a plurality of switching means;
A driving method of an active display device, comprising: a pixel portion in which pixels output as video signals via signal lines from the plurality of current output circuits are arranged in a matrix;
Each of the plurality of switching means, at regular intervals, the plurality of current output circuits, switching the electrical connection between the signal line, and outputs the current output from the current output circuit to the signal line ,
The unit frame period corresponding to the synchronization timing of the video signal input to the signal line has m (m is a natural number of 2 or more) subframe periods SF1, SF2,..., SFm, and the m subframes. The periods SF1, SF2,... SFm each have a writing period Ta1, Ta2,... Tam and a display period Ts1, Ts2,..., Tsm, and the predetermined period is provided within the display period. For driving an active display device. A plurality of current output circuits;
A plurality of first terminals;
A plurality of terminal groups;
A signal line driving circuit having a plurality of switching means;
A driving method for an active display device, comprising: a pixel portion in which pixels output as video signals via signal lines from the plurality of current output circuits are arranged in a matrix;
Each of the plurality of terminal groups includes a plurality of second terminals;
Each of the plurality of current output circuits is electrically connected to any one of the plurality of first terminals via any one of the plurality of second terminals;
The signal line is electrically connected to the plurality of first terminals;
Each of the plurality of switching means switches the electrical connection between the plurality of current output circuits and the signal line at regular intervals, and outputs the current output from the current output circuit to the signal line. ,
The unit frame period corresponding to the synchronization timing of the video signal input to the signal line has m (m is a natural number of 2 or more) subframe periods SF1, SF2,..., SFm, and the m subframes. The periods SF1, SF2,... SFm each have a writing period Ta1, Ta2,... Tam and a display period Ts1, Ts2,..., Tsm, and the predetermined period is provided within the display period. For driving an active display device. A plurality of thin film transistors;
A signal line driving circuit having a plurality of switching means;
A driving method of an active display device having a pixel portion in which drain currents output from the plurality of thin film transistors are arranged in a matrix form pixels input as video signals via signal lines,
Each of the plurality of switching means switches the electrical connection between the plurality of thin film transistors and the signal line at regular intervals, and outputs a drain current output from the thin film transistor to the signal line,
The unit frame period corresponding to the synchronization timing of the video signal input to the signal line has m (m is a natural number of 2 or more) subframe periods SF1, SF2,..., SFm, and the m subframes. The periods SF1, SF2,... SFm each have a writing period Ta1, Ta2,... Tam and a display period Ts1, Ts2,..., Tsm, and the predetermined period is provided within the display period. For driving an active display device. A plurality of thin film transistors;
A plurality of first terminals;
A plurality of terminal groups;
A signal line driving circuit having a plurality of switching means;
A driving method of an active display device having a pixel portion in which drain currents output from the plurality of thin film transistors are arranged in a matrix form pixels input as video signals via signal lines,
Each of the plurality of terminal groups includes a plurality of second terminals;
Each of the plurality of thin film transistors is electrically connected to any one of the plurality of first terminals via any one of the plurality of second terminals;
The signal line is electrically connected to the plurality of first terminals;
Each of the plurality of switching means switches the electrical connection between the plurality of thin film transistors and the signal line at regular intervals, and outputs a drain current output from the thin film transistor to the signal line,
The unit frame period corresponding to the synchronization timing of the video signal input to the signal line has m (m is a natural number of 2 or more) subframe periods SF1, SF2,..., SFm, and the m subframes. The periods SF1, SF2,... SFm each have a writing period Ta1, Ta2,... Tam and a display period Ts1, Ts2,..., Tsm, and the predetermined period is provided within the display period. For driving an active display device.

Images