JP4236122B2 - Manufacturing method of semiconductor substrate - Google Patents
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Description
本発明は、半導体基板の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor substrate.
従来から、非特許文献１に示されるように、ＭＢＥ法により、金属源を用いてクロム層を作成し、そのクロム層をＮ２プラズマ源で窒化する技術がある。
非特許文献１の技術では、クロム層を室温付近で成膜し、そのクロム層を窒化することによりクロム窒化物膜を形成している。このとき、クロム窒化物膜の上にバッファ層及びＩＩＩ族窒化物半導体の結晶層を成長させた場合、ＩＩＩ族窒化物半導体の結晶層の結晶性が十分でないおそれがある。 In the technique of Non-Patent Document 1, a chromium nitride film is formed by forming a chromium layer near room temperature and nitriding the chromium layer. At this time, when the buffer layer and the group III nitride semiconductor crystal layer are grown on the chromium nitride film, the crystallinity of the group III nitride semiconductor crystal layer may not be sufficient.
本発明の目的は、ＩＩＩ族窒化物半導体の結晶層の結晶性を向上できる半導体基板の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a semiconductor substrate capable of improving the crystallinity of a crystal layer of a group III nitride semiconductor.
なお、ＩＩＩ族窒化物半導体としては、Ｇａ、Iｎ系のものが挙げられる。ＩＩＩ族窒化物半導体は、例えば、ＧａＮ系，ＡｌＧａＮ系，ＡｌＩｎＧａＮ系等であるが、これらに限らない。 In addition, as a group III nitride semiconductor, Ga and In type semiconductors can be cited. Group III nitride semiconductors are, for example, GaN-based, AlGaN-based, and AlInGaN-based, but are not limited thereto.
本発明の第１側面に係る半導体基板の製造方法は、下地基板の上にクロム層を５０℃以上の温度で成膜するクロム層成膜工程と、前記クロム層を窒化してクロム窒化物膜にする窒化工程とを備えたことを特徴とする。 The method for manufacturing a semiconductor substrate according to the first aspect of the present invention includes a chromium layer forming step of forming a chromium layer on a base substrate at a temperature of 50 ° C. or more, and a chromium nitride film formed by nitriding the chromium layer. And a nitriding step.
本発明の第２側面に係る半導体基板の製造方法は、下地基板の上にクロム層を５０℃以上の温度で成膜するクロム層成膜工程と、前記クロム層を窒化してクロム窒化物膜にする窒化工程と、前記クロム窒化物膜の上にＩＩＩ族窒化物半導体の結晶層を成長させる結晶層成長工程とを備えたことを特徴とする。 The method for manufacturing a semiconductor substrate according to the second aspect of the present invention includes a chromium layer forming step of forming a chromium layer on a base substrate at a temperature of 50 ° C. or more, and nitriding the chromium layer to form a chromium nitride film. And a crystal layer growth step for growing a group III nitride semiconductor crystal layer on the chromium nitride film.
本発明の第３側面に係る半導体基板の製造方法は、本発明の第１側面又は第２側面に係る半導体基板の製造方法の特徴に加えて、前記下地基板の上面は、六方晶系及び擬似六方晶系のいずれかの（０００１）面、又は立方晶系の（１１１）面であることを特徴とする。 The semiconductor substrate manufacturing method according to the third aspect of the present invention is characterized in that, in addition to the features of the semiconductor substrate manufacturing method according to the first or second aspect of the present invention, the upper surface of the base substrate has a hexagonal crystal structure and pseudo-structure. It is any hexagonal (0001) plane or cubic (111) plane.
本発明の第４側面に係る半導体基板の製造方法は、本発明の第１側面から第３側面のいずれかに係る半導体基板の製造方法の特徴に加えて、前記窒化工程では、前記クロム窒化物膜の表面に三角錐形状の複数の微結晶部を形成することを特徴とする。 The semiconductor substrate manufacturing method according to the fourth aspect of the present invention is characterized in that, in addition to the characteristics of the semiconductor substrate manufacturing method according to any one of the first to third aspects of the present invention, the nitriding step includes the chromium nitride. A plurality of microcrystalline portions having a triangular pyramid shape are formed on the surface of the film.
本発明の第５側面に係る半導体基板の製造方法は、本発明の第１側面から第４側面のいずれかに係る半導体基板の製造方法の特徴に加えて、前記クロム窒化物膜をエッチングして前記ＩＩＩ族窒化物半導体の結晶を前記下地基板から分離する分離工程をさらに備えたことを特徴とする。 According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor substrate, comprising: etching the chromium nitride film in addition to the characteristics of the method for manufacturing a semiconductor substrate according to any one of the first to fourth aspects of the present invention. The method further includes a separation step of separating the group III nitride semiconductor crystal from the base substrate.
本発明によれば、ＩＩＩ族窒化物半導体の結晶層の結晶性を向上できる。 According to the present invention, the crystallinity of the crystal layer of the group III nitride semiconductor can be improved.
本明細書において、「膜」は、連続した膜でもよいし、不連続な膜でもよいものとする。「膜」は、厚さを持って形成されている状態を表す。 In this specification, the “film” may be a continuous film or a discontinuous film. The “film” represents a state where the film is formed with a thickness.
本発明の実施形態に係る半導体基板の製造方法を、図１〜図８を用いて説明する。以下では、結晶層としてＩＩＩ族窒化物半導体のＧａＮを例として説明するが、他のＩＩＩ族窒化物半導体に関しても同様である。なお、後述のように結晶層を自立基板として用いてダイオード等に応用することを考えると、結晶層の材質となるＩＩＩ族窒化物半導体は、ＧａＮであることが好ましい。 A method for manufacturing a semiconductor substrate according to an embodiment of the present invention will be described with reference to FIGS. In the following, GaN as a group III nitride semiconductor will be described as an example of the crystal layer, but the same applies to other group III nitride semiconductors. As will be described later, considering that the crystal layer is used as a free-standing substrate and applied to a diode or the like, the group III nitride semiconductor used as the material of the crystal layer is preferably GaN.
図１及び図２は、本発明の実施形態に係る半導体基板の製造方法を示す工程断面図である。図３及び図４は、ＸＲＤ（Ｘ−Ｒａｙ Ｄｉｆｆｒａｃｔｉｏｎ）チャ−トである。図５は、試料表面を撮影したＳＥＭ写真である。図８は、試料表面を撮影した顕微鏡写真である。図６は、クロム窒化物膜の表面モフォロジ−の模式図である。図７は、クロム窒化物膜の微結晶部の結晶方位を示す図である。 1 and 2 are process cross-sectional views illustrating a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. 3 and 4 are XRD (X-Ray Diffraction) charts. FIG. 5 is an SEM photograph of the sample surface. FIG. 8 is a photomicrograph of the sample surface. FIG. 6 is a schematic diagram of the surface morphology of the chromium nitride film. FIG. 7 is a diagram showing the crystal orientation of the microcrystalline portion of the chromium nitride film.
図１（ａ）に示す工程では、下地基板１０を準備する。下地基板１０は、サファイアの単結晶で形成されている。下地基板１０の上面１０ａは、サファイアの単結晶の（０００１）面になっている。サファイアの単結晶は、擬似六方晶系の結晶構造を有する。 In the step shown in FIG. 1A, a base substrate 10 is prepared. The base substrate 10 is formed of a single crystal of sapphire. The upper surface 10a of the base substrate 10 is a (0001) plane of sapphire single crystal. A single crystal of sapphire has a pseudo hexagonal crystal structure.
なお、下地基板は、六方晶系及び擬似六方晶系及び立方晶系のいずれかの結晶構造を有する材料であれば、サファイア以外の材料で形成されていてもよい。なお、下地基板が立方晶系の場合には、以下の記載において上面として（１１１）面を用いる。 Note that the base substrate may be formed of a material other than sapphire as long as it has a hexagonal crystal structure, a pseudo hexagonal crystal system, or a cubic crystal structure. When the base substrate is a cubic system, the (111) plane is used as the upper surface in the following description.
図１（ｂ）に示す工程では、下地基板１０の上面１０ａに、クロム層２０を加熱しながら成膜する。すなわち、サファイアの結晶の（０００１）面の上にクロム層２０を成膜する。具体的には、下地基板１０は、通常の半導体基板の洗浄方法（有機洗浄による脱脂、酸・アルカリ・純水洗浄による、汚染物・パ−ティクル除去）で洗浄し表面１０ａの清浄度を確保する。清浄度が確保された表面１０ａの上に、不活性ガス雰囲気中、たとえばＡｒガス雰囲気中でスパッタリング法により金属Ｃｒ膜を加熱しながら成膜してクロム層２０を形成する。その際、加熱温度は、５０℃以上であることが好ましく、２００℃以上であることがさらに好ましく、９００℃以上であることがさらに好ましい。クロム層２０を５０℃以上で成膜することにより、室温付近で成膜する場合に比べて、クロム層２０の結晶性が向上する。クロム層２０を２００℃以上で成膜することにより、５０℃以上で成膜する場合に比べて、クロム層２０の結晶性が向上する。クロム層２０を９００℃以上で成膜することにより、２００℃以上で成膜する場合に比べて、クロム層２０の結晶性が向上する。クロム層２０を高温で成膜するほど、クロム層２０の結晶性が向上する傾向にある。 In the step shown in FIG. 1B, the chromium layer 20 is formed on the upper surface 10a of the base substrate 10 while heating. That is, the chromium layer 20 is formed on the (0001) plane of the sapphire crystal. Specifically, the base substrate 10 is cleaned by a normal semiconductor substrate cleaning method (degreasing by organic cleaning, contamination / particle removal by acid / alkali / pure water cleaning) to ensure the cleanness of the surface 10a. To do. A chromium layer 20 is formed on the surface 10a having a cleanliness while heating a metal Cr film by sputtering in an inert gas atmosphere, for example, an Ar gas atmosphere. At that time, the heating temperature is preferably 50 ° C. or higher, more preferably 200 ° C. or higher, and further preferably 900 ° C. or higher. By forming the chromium layer 20 at 50 ° C. or more, the crystallinity of the chromium layer 20 is improved as compared with the case where the chromium layer 20 is formed near room temperature. By forming the chromium layer 20 at 200 ° C. or higher, the crystallinity of the chromium layer 20 is improved as compared with the case where the chromium layer 20 is formed at 50 ° C. or higher. By forming the chromium layer 20 at 900 ° C. or higher, the crystallinity of the chromium layer 20 is improved as compared with the case where the chromium layer 20 is formed at 200 ° C. or higher. As the chromium layer 20 is formed at a higher temperature, the crystallinity of the chromium layer 20 tends to be improved.
一方、下地基板１０が溶解する温度（サファイアの融点：２０２０℃）又はクロム層２０が溶解する温度（クロムの融点：１８６０℃）以上でクロム層２０を成膜することは好ましくない。 On the other hand, it is not preferable to form the chromium layer 20 at a temperature at which the base substrate 10 is dissolved (melting point of sapphire: 2020 ° C.) or a temperature at which the chromium layer 20 is dissolved (melting point of chromium: 1860 ° C.).
ここで、クロム層２０の平均層厚は、７ｎｍ以上４５ｎｍ以下の範囲内の値であることが好ましく、１０ｎｍ以上４０ｎｍ以下の値であることがさらに好ましい。Ｃｒ層の平均層厚を７ｎｍ以上４５ｎｍ未満とすることで、良好な結晶性の結晶層を成長させることが可能となり、さらに１０ｎｍ以上４０ｎｍ以下とすることで、結晶層のピット密度も低減させることが可能となる。 Here, the average layer thickness of the chromium layer 20 is preferably a value within a range of 7 nm or more and 45 nm or less, and more preferably a value of 10 nm or more and 40 nm or less. By making the average layer thickness of the Cr layer 7 nm or more and less than 45 nm, it becomes possible to grow a crystalline layer having good crystallinity, and further by reducing the pit density of the crystal layer by making it 10 nm or more and 40 nm or less. Is possible.
なお、クロム層２０は、真空（熱）蒸着法により成膜してもよい。 The chromium layer 20 may be formed by a vacuum (thermal) vapor deposition method.
この工程で得られた試料のＸＲＤ解析を行うと、例えば、図３に示す結果が得られる。図３では、縦軸がピ−ク強度（任意単位）を示し、横軸が回折角２θを示す。これにより、下地基板１０（サファイア）の（０００１）面とクロム層２０の（１１０）面とが平行になるように配向していることが分かる。クロム層２０は、体心立方構造の金属である。 When the XRD analysis of the sample obtained in this step is performed, for example, the result shown in FIG. 3 is obtained. In FIG. 3, the vertical axis indicates the peak intensity (arbitrary unit), and the horizontal axis indicates the diffraction angle 2θ. Thus, it can be seen that the (0001) plane of the base substrate 10 (sapphire) and the (110) plane of the chromium layer 20 are aligned in parallel. The chromium layer 20 is a metal having a body-centered cubic structure.
図１（ｃ）に示す工程では、クロム層２０が形成された下地基板１０を、ＧａＮの結晶を成長させるための装置へ移送する。そして、クロム層２０が形成された下地基板１０を、窒素を含有した還元性ガス雰囲気で加熱窒化処理を行う。この窒素を含有した還元性ガスは、好ましくはアンモニアもしくはヒドラジンなどである。その際、加熱温度は、１０００℃以上（１２７３K以上）であることが好ましく、１０４０℃以上であることがさらに好ましく、１０６０℃以上であることがさらに好ましい。加熱温度１０００℃以上で窒化することにより、クロム層２０がほぼ全部窒化して、三角錐形状の複数の微結晶部３１を表面に有するクロム窒化物膜３０が形成される。 In the step shown in FIG. 1C, the base substrate 10 on which the chromium layer 20 is formed is transferred to an apparatus for growing GaN crystals. Then, the base substrate 10 on which the chromium layer 20 is formed is heated and nitrided in a reducing gas atmosphere containing nitrogen. The reducing gas containing nitrogen is preferably ammonia or hydrazine. At that time, the heating temperature is preferably 1000 ° C. or higher (1273 K or higher), more preferably 1040 ° C. or higher, further preferably 1060 ° C. or higher. By nitriding at a heating temperature of 1000 ° C. or higher, the chromium layer 20 is almost entirely nitrided, and a chromium nitride film 30 having a plurality of triangular pyramid-shaped microcrystalline portions 31 on the surface is formed.
ここで、クロム窒化物膜３０の組成は、ＣｒＮであることが好ましい。 Here, the composition of the chromium nitride film 30 is preferably CrN.
また、三角錐形状の凸部の１辺の長さは、窒化処理前のＣｒ膜の層厚や加熱温度条件により変化するが、１０ｎｍから３００ｎｍの範囲である。加熱温度１０４０℃以上で窒化することにより、その上に成長させる後述のＧａＮの結晶層５０の表面５０ａのピット密度が１０２〜１０３/ｃｍ２レベルまで低減する。加熱温度１０６０℃以上で窒化することにより、後述のＧａＮの結晶層５０の表面５０ａのピット密度が数/ｃｍ２レベルまで低減する。加熱温度が高いほど、三角錐形状の不定形性が解消されるためと考えられる。 Further, the length of one side of the triangular pyramid-shaped convex portion varies depending on the thickness of the Cr film before nitriding and the heating temperature condition, but is in the range of 10 nm to 300 nm. By nitriding at a heating temperature of 1040 ° C. or more, the pit density of the surface 50a of the GaN crystal layer 50 described later to be grown thereon is reduced to 10 2 ~10 3 / cm 2 level. By nitriding at a heating temperature of 1060 ° C. or higher, the pit density on the surface 50a of the GaN crystal layer 50 described later is reduced to a few / cm 2 level. This is probably because the higher the heating temperature, the more the irregular shape of the triangular pyramid is resolved.
だだし、過度に高温とするのは、熱負荷増大による装置の部材劣化の問題が生じるとともに、形成されたクロム窒化物膜と下地基板との相互熱拡散などの問題が生じるので、加熱温度は１３００℃以下が好ましい。 However, if the temperature is excessively high, there is a problem of deterioration of the members of the apparatus due to an increase in thermal load, and problems such as mutual thermal diffusion between the formed chromium nitride film and the base substrate occur. 1300 degrees C or less is preferable.
ここで、クロム窒化物膜３０の平均膜厚は、２２．５ｎｍ以上７５ｎｍ以下の範囲内の値であることが好ましく、２９ｎｍ以上３１ｎｍ以下の値であることがさらに好ましい。 Here, the average film thickness of the chromium nitride film 30 is preferably a value in the range of 22.5 nm to 75 nm, and more preferably a value of 29 nm to 31 nm.
この工程で得られた試料のＸＲＤ解析を行うと、例えば、図４に示す結果が得られる。図４は、図１（ｃ）に示す試料についてのＸＲＤチャ−トである。図４では、縦軸がピ−ク強度（任意単位）を示し、横軸が回折角２θを示す。図４のＸＲＤチャ−トでは、サファイアのピ−ク及びＣｒＮのピ−クが観察されるが、Ｃｒのピ−クは観察されない。これにより、クロム層２０の大部分が窒化してクロム窒化物膜３０が形成されたことが分かる。 When the XRD analysis of the sample obtained in this step is performed, for example, the result shown in FIG. 4 is obtained. FIG. 4 is an XRD chart for the sample shown in FIG. In FIG. 4, the vertical axis indicates the peak intensity (arbitrary unit), and the horizontal axis indicates the diffraction angle 2θ. In the XRD chart of FIG. 4, sapphire peaks and CrN peaks are observed, but no Cr peaks are observed. As a result, it can be seen that most of the chromium layer 20 is nitrided to form the chromium nitride film 30.
また、ＣｒＮに関して、（１１１）面及び（２２２）面のピ−クのみが観察され、その半値幅が狭くなっている。これにより、クロム窒化物膜３０は、サファイア基板の（０００１）面に平行に、（１１１）面の方位が揃った状態となっていることが分かる。 Further, regarding CrN, only the peaks of the (111) plane and the (222) plane are observed, and the half-value width is narrow. Thereby, it can be seen that the chromium nitride film 30 is in a state in which the orientation of the (111) plane is aligned in parallel with the (0001) plane of the sapphire substrate.
ここで、クロム層２０の結晶性が向上している場合、クロム窒化物膜３０の結晶性も向上する。図１（ｂ）に示す工程でクロム層２０を５０℃以上で成膜することにより、図１（ｂ）に示す工程において室温付近で成膜する場合に比べて、クロム窒化物膜３０の結晶性が向上する。図１（ｂ）に示す工程でクロム層２０を２００℃以上で成膜することにより、図１（ｂ）に示す工程において５０℃以上で成膜する場合に比べて、クロム窒化物膜３０の結晶性が向上する。図１（ｂ）に示す工程においてクロム層２０を９００℃以上で成膜することにより、図１（ｂ）に示す工程において２００℃以上で成膜する場合に比べて、クロム窒化物膜３０の結晶性が向上する。 Here, when the crystallinity of the chromium layer 20 is improved, the crystallinity of the chromium nitride film 30 is also improved. By forming the chromium layer 20 at 50 ° C. or higher in the step shown in FIG. 1B, the crystal of the chromium nitride film 30 is compared to the case where the chromium layer 20 is formed near room temperature in the step shown in FIG. Improves. By forming the chromium layer 20 at 200 ° C. or higher in the step shown in FIG. 1B, the chromium nitride film 30 is formed at a temperature higher than 50 ° C. in the step shown in FIG. Crystallinity is improved. By forming the chromium layer 20 at 900 ° C. or higher in the step shown in FIG. 1B, the chromium nitride film 30 is formed as compared with the case of forming at 200 ° C. or higher in the step shown in FIG. Crystallinity is improved.
この工程で得られた試料の表面をＳＥＭ観察すると、例えば、図５に示す結果が得られる。図５は、試料表面のＳＥＭ写真である。 When the surface of the sample obtained in this step is observed with an SEM, for example, the result shown in FIG. 5 is obtained. FIG. 5 is an SEM photograph of the sample surface.
図５のＳＥＭ写真によれば、クロム窒化物膜３０が、三角錐形状の複数の微結晶部３１を表面に有していることが分かる。また、クロム窒化物膜３０の各微結晶部３１は、下地基板１０の表面１０ａの略全面に分布している。 According to the SEM photograph of FIG. 5, it can be seen that the chromium nitride film 30 has a plurality of triangular pyramid-shaped microcrystalline portions 31 on the surface. Further, the microcrystalline portions 31 of the chromium nitride film 30 are distributed over substantially the entire surface 10 a of the base substrate 10.
クロム窒化物膜３０の各微結晶部３１は、図６に示すように、底辺の各辺が、下地基板１０の〔１０−１０〕方向、〔０１−１０〕方向及び〔−１１００〕方向のいずれかに沿って延びている。 As shown in FIG. 6, each microcrystalline portion 31 of the chromium nitride film 30 has bottom sides in the [10-10] direction, the [01-10] direction, and the [−1100] direction of the base substrate 10. It extends along either.
また、図１（ｃ）に示す工程で得られた試料の断面をＴＥＭ観察した。その結果、各微結晶部３１の３つの側面（底面以外のファセット面）は、{１００}面郡で形成されていることが分かった。 Further, a cross section of the sample obtained in the step shown in FIG. As a result, it was found that the three side surfaces (facet surfaces other than the bottom surface) of each microcrystalline portion 31 were formed in {100} plane groups.
このように、クロム窒化物膜３０の各微結晶部３１は、個々には単結晶で、二つの結晶方位を有する微結晶（マルチツイン）集合体である。図５及び図６に示すように、三角錐の底辺の向きが１８０°面内回転した二種類の結晶方位（マルチツイン）を有する状態であるが、この上に成長する六方晶系の結晶対称性から、成長したＩＩＩ族窒化物半導体結晶は単結晶となるので、何ら支障はない。すなわち、図７に示すように、クロム窒化物膜３０の各微結晶部３１の格子間隔（図７に示す正三角形部の黒丸の間隔）は、下地基板１０（サファイア）の格子間隔（図７に示す白丸の間隔）と異なる。これにより、各微結晶部３１を構成する原子（図７に示す黒丸）がサファイアの格子（図７に示す白丸）の間の位置で安定的に存在する。これにより、各微結晶部３１は、黒丸で示す結晶格子のパタ−ンが繰り返し配列された微結晶（マルチツイン）となり、三角錐形状の複数の微結晶部を表面に有するようになる。そして、各微結晶部３１は、底辺が〔１０−１０〕方向、〔０１−１０〕方向及び〔−１１００〕方向のいずれかに沿って延び、側面が{１００}面群になる。これにより、微結晶どうしの面内回転による結晶方位ズレは極めて少ない状態となる。また、各微結晶部３１の底面の重心から上端へ向かう方向は、下地基板の（０００１）面に対して垂直、すなわちサファイアの結晶のＣ軸と平行な方位となっている。 Thus, each microcrystalline portion 31 of the chromium nitride film 30 is a single crystal and is a microcrystalline (multi-twin) aggregate having two crystal orientations. As shown in FIG. 5 and FIG. 6, the direction of the base of the triangular pyramid has two kinds of crystal orientations (multi-twin) rotated in the plane of 180 °. Therefore, the grown group III nitride semiconductor crystal becomes a single crystal, so there is no problem. That is, as shown in FIG. 7, the lattice spacing of the microcrystalline portions 31 of the chromium nitride film 30 (the spacing of the black circles of the equilateral triangular portion shown in FIG. 7) is the lattice spacing of the base substrate 10 (sapphire) (FIG. 7). Different from the white circle interval shown in FIG. Thereby, the atoms (black circles shown in FIG. 7) constituting each microcrystalline portion 31 are stably present at positions between sapphire lattices (white circles shown in FIG. 7). Thereby, each microcrystal part 31 becomes a microcrystal (multi-twin) in which patterns of crystal lattices indicated by black circles are repeatedly arranged, and has a plurality of triangular pyramid-shaped microcrystal parts on the surface. Each microcrystalline portion 31 has a base extending along any one of the [10-10] direction, the [01-10] direction, and the [-1100] direction, and the side surface is a {100} plane group. Thereby, the crystal orientation deviation due to the in-plane rotation of the microcrystals becomes extremely small. The direction from the center of gravity of the bottom surface of each microcrystal portion 31 toward the upper end is perpendicular to the (0001) plane of the base substrate, that is, the orientation parallel to the C axis of the sapphire crystal.
ここで、クロム窒化物膜３０の平均膜厚は、１０ｎｍ以上６８ｎｍ以下の範囲内の値であることが好ましく、１５ｎｍ以上６０ｎｍ以下の値であることがさらに好ましい。ここで、ＣｒＮ膜の平均膜厚は、断面ＴＥＭで凹凸を測定して求めることができ、窒化を行う以前のＣｒ層の平均層厚の１．５倍に相当することが確認された。 Here, the average film thickness of the chromium nitride film 30 is preferably a value within a range of 10 nm to 68 nm, and more preferably a value of 15 nm to 60 nm. Here, the average film thickness of the CrN film can be obtained by measuring unevenness with a cross-sectional TEM, and it was confirmed that it corresponds to 1.5 times the average layer thickness of the Cr layer before nitriding.
クロム窒化物膜３０の平均膜厚が１０ｎｍ未満の場合、すなわちクロム層の層厚が７ｎｍ未満の場合、下地基板１０の表面１０ａが部分的に露出することがあるため、後述の図２（ａ）の工程で下地基板１０とクロム窒化物膜３０との両者からＧａＮのバッファ層が成長し始めることになる。これにより、下地基板１０から成長したＧａＮのバッファ層とクロム窒化物膜３０から成長したＧａＮのバッファ層とで結晶方位が異なるので、後述の図２（ｂ）の工程で結晶品質の向上が期待できないおそれがあり、又は、後述の図２（ｂ）の工程で結晶成長後のＧａＮの表面においてピットが多くなるおそれがある。また、クロム窒化物膜３０の平均膜厚が６８ｎｍを越えた場合、上述の加熱窒化処理において、下地基板１０上にクロム窒化物膜３０の固相エピタキシャル成長が均一に進行せずにクロム窒化物膜３０が多結晶となる傾向にある。これにより、後述の図２（ａ）の工程でクロム窒化物膜３０の上に成長するＧａＮがモザイク状乃至多結晶になり、後述の図２（ｂ）の工程で結晶品質の向上が期待できないおそれがある。 When the average thickness of the chromium nitride film 30 is less than 10 nm, that is, when the thickness of the chromium layer is less than 7 nm, the surface 10a of the base substrate 10 may be partially exposed. ), The GaN buffer layer begins to grow from both the base substrate 10 and the chromium nitride film 30. As a result, the crystal orientation differs between the GaN buffer layer grown from the base substrate 10 and the GaN buffer layer grown from the chromium nitride film 30, so that an improvement in crystal quality is expected in the process of FIG. There is a possibility that it may not be possible, or there is a possibility that pits will increase on the surface of GaN after crystal growth in the step of FIG. Further, when the average film thickness of the chromium nitride film 30 exceeds 68 nm, the chromium nitride film 30 does not progress uniformly on the underlying substrate 10 in the above-described heat nitriding process, and the chromium nitride film 30 does not proceed uniformly. 30 tends to be polycrystalline. As a result, GaN grown on the chromium nitride film 30 in the later-described step of FIG. 2A becomes mosaic or polycrystalline, and improvement in crystal quality cannot be expected in the later-described step of FIG. 2B. There is a fear.
なお、図１（ｂ）に示す工程と図１（ｃ）に示す工程とは、同一装置で行っても別の装置で行っても良い。図１（ｂ）に示す工程と図２（ａ）に示す工程との間では、大気開放しないで行うことが好ましい。 Note that the step shown in FIG. 1B and the step shown in FIG. 1C may be performed by the same apparatus or different apparatuses. It is preferable to perform without opening to the atmosphere between the step shown in FIG. 1B and the step shown in FIG.
次に、図２（ａ）に示す工程では、下地基板温度を９００℃まで下げ、ＨＶＰＥ法でＩＩＩ族窒化物（例えば、ＧａＮ）のバッファ層４０を成膜する。バッファ層４０の層厚は、例えば、約１０μｍとする。 Next, in the step shown in FIG. 2A, the base substrate temperature is lowered to 900 ° C., and a buffer layer 40 of group III nitride (for example, GaN) is formed by HVPE. The layer thickness of the buffer layer 40 is about 10 μm, for example.
ここで、バッファ層４０は、クロム窒化物膜３０の三角錐形状の微結晶（微結晶部３１）を成長核に（核生成サイトとして）、{１００}ファセット面群のそれぞれから横方向成長する。これにより、クロム窒化物膜３０とバッファ層４０との界面（成長界面）で発生する転位（貫通転位）が上方向に伝播することを抑制できる。三角錘形状は、鋭角を有するものや、一辺が直線であるようなもののみに限定するものではなく、概ね三角錐形状のことを称している。形状を擬似的に加工し、または、成長過程で多面体にする物も含む。 Here, the buffer layer 40 grows laterally from each of the {100} facet plane groups using the triangular pyramid-shaped microcrystal (microcrystal portion 31) of the chromium nitride film 30 as a growth nucleus (as a nucleation site). . Thereby, it is possible to suppress the dislocation (threading dislocation) generated at the interface (growth interface) between the chromium nitride film 30 and the buffer layer 40 from propagating upward. The triangular pyramid shape is not limited to those having an acute angle or having a straight line on one side, but generally refers to a triangular pyramid shape. It also includes an object whose shape is artificially processed or made into a polyhedron during the growth process.
また、クロム窒化物膜３０の微結晶（微結晶部３１）の結晶方位が揃っているので、ＩＩＩ族窒化物の横方向成長において異なる方向から成長した結晶どうしが合体する際に、面内回転による方位ズレや成長厚み方向の結晶軸ズレ（Ｃ軸のズレ）を小さくできる。これにより、結晶方位が揃った状態で合体させることができるので、異なる方向から成長した結晶どうしが合体する部分において、ＩＩＩ族窒化物の転位の発生を抑制することができる。 In addition, since the crystal orientations of the microcrystals (microcrystal part 31) of the chromium nitride film 30 are aligned, in-plane rotation occurs when crystals grown from different directions are combined in the lateral growth of the group III nitride. Misalignment due to, and crystal axis misalignment (C axis misalignment) in the growth thickness direction can be reduced. As a result, the crystallographic orientations can be merged, so that the occurrence of group III nitride dislocations can be suppressed in the portion where the crystals grown from different directions merge.
さらに、核生成サイトとなる微結晶部３１が、下地基板１０の上において、ほぼ一様な大きさを有しており、概略一様な間隔で分布している。これにより、クロム窒化物膜３０の上においてバッファ層４０が一様な方向に成長するので、この点からも転位の発生を抑制することができる。 Further, the microcrystalline portions 31 serving as nucleation sites have a substantially uniform size on the base substrate 10 and are distributed at substantially uniform intervals. Thereby, since the buffer layer 40 grows in a uniform direction on the chromium nitride film 30, the occurrence of dislocation can be suppressed also from this point.
図２（ｂ）に示す工程では、下地基板温度を１０４０℃まで昇温し、ＧａＮの結晶層５０を成長する。成長時の結晶層５０の層厚は、例えば、約１０μｍとする。 In the step shown in FIG. 2B, the temperature of the base substrate is raised to 1040 ° C., and the GaN crystal layer 50 is grown. The thickness of the crystal layer 50 during the growth is, for example, about 10 μm.
上述のように転位が低減したバッファ層４０の上に結晶層５０を成長するので、結晶層５０の転位密度は１０７〜１０８/ｃｍ２にまで低減する。すなわち、いわゆる低温バッファ層技術よりも１〜２桁の転位密度が低減する。 As described above, since the crystal layer 50 is grown on the buffer layer 40 in which dislocations are reduced, the dislocation density of the crystal layer 50 is reduced to 10 7 to 10 8 / cm 2 . That is, the dislocation density is reduced by 1 to 2 digits compared to the so-called low temperature buffer layer technology.
この工程で得られた試料の表面を顕微鏡観察すると、例えば、図８に示す結果が得られる。図８は、試料表面の顕微鏡写真である。 When the surface of the sample obtained in this step is observed with a microscope, for example, the result shown in FIG. 8 is obtained. FIG. 8 is a photomicrograph of the sample surface.
図８の顕微鏡写真によれば、結晶層５０の表面５０ａには、ほとんどピットがないことが分かる。すなわち、表面ピット密度は、０〜１０２/ｃｍ２にまで低減する。すなわち、金属バッファ層を用いる方法（例えば、特開２００２−２８４６００に示されるＡｌ，Ａｕ，Ａｇ，Ｎｉ，Ｔｉ，Ｃｕを用いた方法を用いた場合、表面ピット密度は１０４〜１０５／ｃｍ２）に比べ、エピシャル成長膜の表面ピット密度を３〜４桁以上低減することができる。これにより、ピットに起因した歩留まりの低下が生じない。また、結晶層５０における転位密度を低減できていることが推定される。 According to the micrograph of FIG. 8, it can be seen that the surface 50a of the crystal layer 50 has almost no pits. That is, the surface pit density is reduced to 0 to 10 2 / cm 2 . That is, when a method using a metal buffer layer (for example, a method using Al, Au, Ag, Ni, Ti, Cu disclosed in JP-A-2002-284600 is used, the surface pit density is 10 4 to 10 5 / cm. Compared with 2 ), the surface pit density of the epitaxially grown film can be reduced by 3 to 4 digits or more. As a result, the yield is not reduced due to the pits. It is also estimated that the dislocation density in the crystal layer 50 can be reduced.
図２（ｃ）に示す工程では、化学溶液を用いてクロム窒化物膜３０を選択的にエッチングする。ＧａＮの基板ＳＢを下地基板１０から分離できる。すなわち、ＧａＮの基板ＳＢを自立基板として得ることができる。ここで、基板ＳＢは、バッファ層４０と結晶層５０とを含んでいる。 In the step shown in FIG. 2C, the chromium nitride film 30 is selectively etched using a chemical solution. The GaN substrate SB can be separated from the base substrate 10. That is, the GaN substrate SB can be obtained as a free-standing substrate. Here, the substrate SB includes the buffer layer 40 and the crystal layer 50.
副次的な効果として、バッファ層４０の裏面には、クロム窒化物膜３０の微結晶部３１に対応した凹部４１が形成されている。この凹部４１は、数十ｎｍから数百オ−ダ−の三角錐形状であるため、デバイスに用いた際に発光ダイオ−ドの光取り出し効率を向上できる。また、結晶欠陥密度の低減により、発光ダイオードの内部量子効率も向上するので、発光ダイオードの全体発光効率も大幅に改善される効果が得られる。 As a secondary effect, a recess 41 corresponding to the microcrystalline portion 31 of the chromium nitride film 30 is formed on the back surface of the buffer layer 40. Since the recess 41 has a triangular pyramid shape of several tens of nm to several hundreds of orders, the light extraction efficiency of the light emitting diode can be improved when used in a device. Moreover, since the internal quantum efficiency of the light emitting diode is improved by reducing the crystal defect density, an effect that the overall light emitting efficiency of the light emitting diode is greatly improved can be obtained.
なお、上記バッファ層４０の上にさらにＩＩＩ族系窒化物の半導体層を積層し、素子構造とすれば、優れた半導体素子が得られる。 An excellent semiconductor element can be obtained by further laminating a group III-based nitride semiconductor layer on the buffer layer 40 to obtain an element structure.
以上のように、クロム層２０を成膜する際の温度（成膜温度）により、得られるクロム窒化物膜３０の結晶性が変化する。それにより、その上に成長させるバッファ層及び結晶層の結晶性が変化する。そこで、上述の図１〜図２（ｃ）と同様の工程により試料を作成した。ここで、成膜温度（図１（ｂ）に示す工程における加熱温度）を変えた場合において、結晶層のＸＲＤ解析結果からＧａＮのピ−ク半値幅を評価した。その結果を図９及び図１０に示す。図９は、ＧａＮ（結晶層）の（０００２）面のピ−ク半値幅の変化を表し、図１０は、ＧａＮ（結晶層）の（１０−１１）面のピ−ク半値幅の変化を表す。ピ−ク半値幅は、小さいほど結晶性が良好であることを示す。 As described above, the crystallinity of the resulting chromium nitride film 30 varies depending on the temperature (deposition temperature) at which the chromium layer 20 is formed. As a result, the crystallinity of the buffer layer and the crystal layer grown thereon changes. Therefore, a sample was prepared by the same process as that shown in FIGS. Here, when the film formation temperature (the heating temperature in the step shown in FIG. 1B) was changed, the FWHM of the GaN peak was evaluated from the XRD analysis result of the crystal layer. The results are shown in FIG. 9 and FIG. FIG. 9 shows a change in peak half-value width of the (0002) plane of GaN (crystal layer), and FIG. 10 shows a change in peak half-value width of the (10-11) plane of GaN (crystal layer). To express. The smaller the peak half-value width, the better the crystallinity.
図９及び図１０に示す結果より、クロム層を成膜する際の加熱処理において、加熱温度は、５０℃以上であることが好ましく、２００℃以上であることがさらに好ましく、９００℃以上であることがさらに好ましい。クロム層２０を５０℃以上で成膜することにより、室温付近で成膜する場合に比べて、ＧａＮ（結晶層）の結晶性が向上する。クロム層２０を２００℃以上で成膜することにより、５０℃以上で成膜する場合に比べて、ＧａＮ（結晶層）の結晶性が向上する。クロム層２０を９００℃以上で成膜することにより、２００℃以上で成膜する場合に比べて、ＧａＮ（結晶層）の結晶性が向上する。 From the results shown in FIGS. 9 and 10, in the heat treatment for forming the chromium layer, the heating temperature is preferably 50 ° C. or higher, more preferably 200 ° C. or higher, and 900 ° C. or higher. More preferably. By forming the chromium layer 20 at 50 ° C. or higher, the crystallinity of GaN (crystalline layer) is improved as compared with the case where the chromium layer 20 is formed near room temperature. By forming the chromium layer 20 at 200 ° C. or higher, the crystallinity of GaN (crystalline layer) is improved as compared with the case of forming the film at 50 ° C. or higher. By forming the chromium layer 20 at 900 ° C. or higher, the crystallinity of GaN (crystalline layer) is improved as compared with the case of forming at 200 ° C. or higher.
以上のように、クロム層２０を成膜する際の加熱温度が高いほど、その上に形成するクロム窒化物膜３０の微結晶部３１における三角錐形状の不定形性が解消されるため、さらにその上に形成されるバッファ層４０及び結晶層５０の結晶性が向上すると考えられる。だだし、過度に高温とするのは、熱負荷増大による装置の部材劣化の問題が生じるとともに、形成されたクロム窒化物膜と下地基板との相互熱拡散などの問題が生じるので、加熱温度は１３００℃以下が好ましい。 As described above, the higher the heating temperature at the time of forming the chromium layer 20 is, the more the triangular pyramid-shaped irregularity in the microcrystalline portion 31 of the chromium nitride film 30 formed thereon is eliminated. It is considered that the crystallinity of the buffer layer 40 and the crystal layer 50 formed thereon is improved. However, if the temperature is excessively high, there is a problem of deterioration of the members of the apparatus due to an increase in thermal load, and problems such as mutual thermal diffusion between the formed chromium nitride film and the base substrate occur. 1300 degrees C or less is preferable.
１０ 下地基板
２０ クロム層
３０ クロム窒化物膜
４０ バッファ層
５０ 結晶層
DESCRIPTION OF SYMBOLS 10 Base substrate 20 Chromium layer 30 Chromium nitride film 40 Buffer layer 50 Crystal layer
Claims (5)
前記クロム層を１０００℃以上の温度で窒化してクロム窒化物膜にする窒化工程と、
前記クロム窒化物膜の上にＩＩＩ族窒化物半導体の結晶層を成長させる結晶層成長工程と、
を備えたことを特徴とする半導体基板の製造方法。 A chromium layer forming step of forming a chromium layer on the base substrate at a temperature of 50 ° C. or higher;
A nitriding step of nitriding the chromium layer at a temperature of 1000 ° C. or higher to form a chromium nitride film;
A crystal layer growth step of growing a crystal layer of a group III nitride semiconductor on the chromium nitride film;
A method for manufacturing a semiconductor substrate, comprising:
ことを特徴とする請求項１に記載の半導体基板の製造方法。 2. The semiconductor substrate manufacturing method according to claim 1 , wherein the upper surface of the base substrate is a hexagonal or pseudo-hexagonal (0001) plane or a cubic (111) plane. 3. Method.
ことを特徴とする請求項１又は２に記載の半導体基板の製造方法。 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the nitriding step, a plurality of triangular pyramid-shaped microcrystalline portions are formed on a surface of the chromium nitride film.
ことを特徴とする請求項３に記載の半導体基板の製造方法。 4. The method of manufacturing a semiconductor substrate according to claim 3 , wherein the triangular pyramid-shaped microcrystalline portion of the chromium nitride film has a side length of 10 nm or more and 300 nm or less.
ことを特徴とする請求項１から４のいずれか１項に記載の半導体基板の製造方法。 The semiconductor substrate according to claim 1, any one of 4, characterized in that the chromium nitride film is etched in the group III nitride semiconductor crystal, further comprising a separation step of separating from said starting substrate Manufacturing method.
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