JP4234023B2 - Display device and manufacturing method of display device - Google Patents

Display device and manufacturing method of display device Download PDF

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JP4234023B2
JP4234023B2 JP2004014360A JP2004014360A JP4234023B2 JP 4234023 B2 JP4234023 B2 JP 4234023B2 JP 2004014360 A JP2004014360 A JP 2004014360A JP 2004014360 A JP2004014360 A JP 2004014360A JP 4234023 B2 JP4234023 B2 JP 4234023B2
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signal line
line
display device
auxiliary capacitance
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慎吾 永野
雄一 升谷
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Mitsubishi Electric Corp
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Description

本発明は、配線群が形成された絶縁性基板の製造工程における静電破壊を防止可能な表示装置および表示装置の製造方法に関する。   The present invention relates to a display device and a display device manufacturing method capable of preventing electrostatic breakdown in a manufacturing process of an insulating substrate on which a wiring group is formed.

従来の表示装置は、ショートリング形成以前における静電荷の放電用として、走査線、補助容量線それぞれの配線部に突起部を形成し、この突起部の配置位置として他層の信号線のような導体パターンが形成されない位置を選択することにより、放電によって生じた絶縁膜の損傷等を介して信号線のような他層の導体パターンと走査線または補助容量線とがショートすることなく、静電破壊を防止できるというものであった(例えば、特許文献1参照)。   In the conventional display device, for discharging electrostatic charges before the formation of the short ring, a protrusion is formed in each wiring portion of the scanning line and the auxiliary capacitance line, and the position of the protrusion is arranged like a signal line in another layer. By selecting the position where the conductor pattern is not formed, the conductor pattern of the other layer such as the signal line and the scanning line or the auxiliary capacitance line are not short-circuited through the damage of the insulating film caused by the discharge. The destruction can be prevented (see, for example, Patent Document 1).

特開平8−234227号公報(図1)JP-A-8-234227 (FIG. 1)

しかしながら、上記した従来の表示装置においては、製造工程中に静電気が発生した場合、走査線と補助容量線との間の突起部にて放電させて静電破壊を防止しているが、数千ボルトにも達する静電気を放電した走査線と補助容量線の間の突起部は短絡してしまう場合があり、短絡が発生した場合、結果的に走査線と補助容量線とが短絡され、表示不良となってしまうという問題があった。   However, in the conventional display device described above, when static electricity is generated during the manufacturing process, electrostatic discharge is prevented by discharging at the protruding portion between the scanning line and the auxiliary capacitance line. The protrusion between the scanning line that discharges static electricity that reaches the volt and the auxiliary capacitance line may be short-circuited. When a short circuit occurs, the scanning line and the auxiliary capacitance line are short-circuited as a result, resulting in poor display. There was a problem of becoming.

本発明はこのような問題点に鑑みてなされたものであり、製造工程中の静電破壊を防止し、かつ走査線と補助容量線との間の短絡も防止可能な表示装置および表示装置の製造方法を提供することを目的とする。   The present invention has been made in view of such problems, and it is possible to prevent electrostatic breakdown during a manufacturing process and to prevent a short circuit between a scanning line and an auxiliary capacitance line. An object is to provide a manufacturing method.

本発明の表示装置は、絶縁性基板上に形成された表示領域を形成する画素と、前記画素と接続される第1の信号線と、前記第1の信号線と同一層の導電膜で、かつ前記第1の信号線と並行に形成され、前記第1の信号線と異なる信号を供給する第2の信号線と、前記表示領域外の領域において、前記第1の信号線および前記第2の信号線と同一層の導電膜で形成され、かつ前記第1の信号線および前記第2の信号線のそれぞれに対し、放電可能な間隔を有した独立のパターンとを備えたことを特徴とする。
The display device of the present invention includes a pixel that forms a display region formed over an insulating substrate, a first signal line connected to the pixel, and a conductive film in the same layer as the first signal line . and are formed in parallel with said first signal line, the first signal line and the different signal second signal line for supplying a, in the display area outside the region, the first signal line and the second And an independent pattern having a dischargeable interval with respect to each of the first signal line and the second signal line. To do.

本発明によれば、表示装置の製造工程中の静電破壊を防止し、かつ走査線と補助容量線との間の短絡も防止することが可能である。   According to the present invention, it is possible to prevent electrostatic breakdown during the manufacturing process of the display device and to prevent a short circuit between the scanning line and the auxiliary capacitance line.

実施の形態1.
本発明の実施の形態1を図1〜図2により説明する。図1は本発明の実施の形態1における表示装置の等価回路図を示し、図2は図1における主要部の拡大図を示している。
Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an equivalent circuit diagram of a display device according to Embodiment 1 of the present invention, and FIG. 2 shows an enlarged view of a main part in FIG.

図1において、絶縁性基板1上に表示領域2を形成する画素が配設され、各画素は薄膜トランジスタ3を具備している。なお、薄膜トランジスタ3のゲートは走査線4に接続され、ソースは映像信号線5に接続され、ドレインは補助容量6を介して補助容量線7に接続されている。また、図示されてはいないが、ドレインには透明電極などからなる画素電極も接続されている。上記補助容量線7は、一般的に表示装置全体として同一の電圧が印加されるため、図1に示すように表示領域2の外側においてそれぞれ共通補助容量線8に接続されている。各走査線4および各映像信号線5は、表示領域2から引き出し走査線9および引き出し映像信号線10によりそれぞれ引き出され、絶縁性基板端部近傍に形成された走査線側外部接続端子11と映像信号線側外部接続端子12にそれぞれ接続されている。共通補助容量線8も、前記走査線側外部接続端子、映像信号線側外部接続端子と並行に形成された補助容量用外部端子13に接続されている。該外部接続端子11、12、13に、例えばACF(Anisotropic Conductive Film:異方性導電膜)などの導電性材料により、フィルム基板に実装された駆動回路などが接続されている。   In FIG. 1, pixels for forming a display region 2 are provided on an insulating substrate 1, and each pixel includes a thin film transistor 3. The thin film transistor 3 has a gate connected to the scanning line 4, a source connected to the video signal line 5, and a drain connected to the auxiliary capacitance line 7 via the auxiliary capacitance 6. Although not shown, a pixel electrode made of a transparent electrode or the like is also connected to the drain. Since the same voltage is generally applied to the storage capacitor line 7 as a whole display device, the storage capacitor line 7 is connected to the common storage capacitor line 8 outside the display area 2 as shown in FIG. Each scanning line 4 and each video signal line 5 are led out from the display area 2 by a drawing scanning line 9 and a drawing video signal line 10, respectively, and the scanning line side external connection terminal 11 formed near the edge of the insulating substrate and the video. Each is connected to the signal line side external connection terminal 12. The common auxiliary capacitance line 8 is also connected to the auxiliary capacitance external terminal 13 formed in parallel with the scanning line side external connection terminal and the video signal line side external connection terminal. The external connection terminals 11, 12, 13 are connected to a drive circuit or the like mounted on a film substrate by a conductive material such as ACF (Anisotropic Conductive Film).

図2は、図1における主要部の拡大図を示しており、具体的には表示領域2の外側の走査線2本と補助容量線2本分のパターニング図を示しており、図中の表示領域内の薄膜トランジスタなどについては、記載を省略している。また、図中の補助容量線7は、図1に示したように、図示しないさらに外側の領域などで、共通補助容量線8にそれぞれ接続されるものであり、走査線4については、図2においては左側に引き出され、走査線側外部接続端子11に接続される構成となっている。図2のように、本発明においては、絶縁性基板上の表示領域外の領域において、同一の製造工程で形成された、即ち同一層の導電膜で形成された走査線と補助容量線との間に、該走査線と補助容量線と同一層の導電膜により形成された独立したパターン14を設け、かつ該独立パターン14は、走査線4および補助容量線7それぞれとの距離を、放電可能な間隔Xを有して形成されているものである。該放電可能な間隔Xとは、絶縁性基板上に各配線等をパターニングする製造工程中に、例えば数千ボルトに達する静電気が発生した場合に放電可能な距離を表し、好ましくは3〜10μm程度である。該放電可能な間隔Xが3〜10μmであれば、確実に放電を行なうことができ、かつ放電後に該走査線と補助容量線との短絡および製造工程中の異物の発生等による該走査線と補助容量線との短絡も抑制可能である。   FIG. 2 shows an enlarged view of the main part in FIG. 1, and specifically shows a patterning diagram for two scanning lines and two auxiliary capacitance lines outside the display region 2, and the display in FIG. The description of the thin film transistor in the region is omitted. Further, as shown in FIG. 1, the auxiliary capacitance line 7 in the figure is connected to the common auxiliary capacitance line 8 in a further outer region (not shown), and the scanning line 4 is shown in FIG. In FIG. 2, the structure is drawn to the left side and connected to the scanning line side external connection terminal 11. As shown in FIG. 2, in the present invention, in the region outside the display region on the insulating substrate, the scanning line and the auxiliary capacitance line formed by the same manufacturing process, that is, formed by the conductive film of the same layer. An independent pattern 14 formed of a conductive film of the same layer as the scanning line and the auxiliary capacitance line is provided therebetween, and the independent pattern 14 can discharge the distance between the scanning line 4 and the auxiliary capacitance line 7 respectively. It is formed with a small interval X. The dischargeable interval X represents a distance that can be discharged when static electricity reaching, for example, several thousand volts occurs during the manufacturing process of patterning each wiring on the insulating substrate, and preferably about 3 to 10 μm. It is. If the dischargeable interval X is 3 to 10 μm, the discharge can be surely performed, and after the discharge, the scanning line and the auxiliary capacitance line are short-circuited, and the scanning line is caused by the generation of foreign matters during the manufacturing process. Short-circuiting with the auxiliary capacitance line can also be suppressed.

上述の構成とすることで、絶縁性基板上に各配線等をパターニングする製造工程中に、例えば数千ボルトに達する静電気が発生した場合に、各独立パターンと走査線または補助容量線との間で放電させることで、他の層(映像信号線等)との間の絶縁破壊などを抑制することが可能となる。なお、本実施の形態では、独立パターンは、走査線および補助容量線それぞれに対して、放電可能な間隔をもって形成されているため、放電後にどこか1箇所の独立パターンと走査線または補助容量線とが短絡されたとしても、走査線と補助容量線との短絡とはならず、製造歩留を低下させることもない。   With the above-described configuration, during the manufacturing process of patterning each wiring and the like on the insulating substrate, for example, when static electricity reaching several thousand volts occurs, between each independent pattern and the scanning line or auxiliary capacitance line It is possible to suppress dielectric breakdown with other layers (video signal lines and the like) by discharging with. In the present embodiment, the independent pattern is formed with a dischargeable interval with respect to each of the scanning line and the auxiliary capacitance line. Are short-circuited between the scanning line and the auxiliary capacitance line, and the manufacturing yield is not lowered.

実施の形態2.
本発明の実施の形態2を図3により説明する。図3は本発明の実施の形態2における図1の主要部の拡大図を示している。
Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows an enlarged view of the main part of FIG. 1 in Embodiment 2 of the present invention.

図3において、図1、図2と同じ構成部分については同一の符号を付し、差異について説明する。図3においては、図2の独立パターン14に加えて、補助容量線7において、隣接する補助容量線との間に、放電可能な間隔Yを有した突起部15が形成されている。該放電可能な間隔Yは、上記実施の形態1と同様に、好ましくは3〜10μm程度である。また、上述の図2の場合と同様に、図3の補助容量線7は、図1に示したように、図示しないさらに外側の領域などで、共通補助容量線8にそれぞれ接続されるものであり、走査線4については、図3においては左側に引き出され、走査線側外部接続端子11に接続される構成となっている。   3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and differences will be described. In FIG. 3, in addition to the independent pattern 14 of FIG. 2, in the auxiliary capacitance line 7, a protrusion 15 having a dischargeable interval Y is formed between adjacent auxiliary capacitance lines. The dischargeable interval Y is preferably about 3 to 10 μm as in the first embodiment. Similarly to the case of FIG. 2 described above, the auxiliary capacitance line 7 in FIG. 3 is connected to the common auxiliary capacitance line 8 in a further outer region (not shown) as shown in FIG. The scanning line 4 is drawn to the left in FIG. 3 and connected to the scanning line side external connection terminal 11.

上述した構成により、実施の形態1の効果に加えて、上述のように補助容量線は表示装置全体として一般的に同一の電圧が印加されることから、隣接する補助容量線にも同一の電圧が印加されており、もし放電後に短絡しても何ら不都合はなく、放電可能な間隔をもった部分を増加させることが可能となり、より確実に静電破壊を防止することが可能である。図3においては、補助容量線について、隣接する補助容量線との間に突起部を形成する構成について示したが、同様の構成を走査線に適用してもよい。しかしながら、該走査線に適用し、放電後に隣接する走査線と短絡してしまった場合、表示不良をもたらしてしまうため、放電可能な間隔の設定の際に注意が必要である。走査線と隣接する走査線との間の放電可能な間隔は、放電後の短絡抑制のため5〜10μm程度が好ましい。該走査線については、例えば表示装置が完成する前に切り落とされ、かつ絶縁性基板の周縁部に走査線と同一層の導電膜で形成されたショートリングと、走査線との間に放電可能な間隔(3〜10μm程度)を有する部分を形成することで、上記補助容量線の場合と同様の効果を奏することが可能である。この場合、該ショートリングと放電可能な間隔を有して形成された走査線の部分とが、放電後に短絡したとしても、上述のように該部分は表示装置が完成する前に切り落とされることから、何ら問題は生じない。該ショートリングと走査線との間に放電可能な間隔を設ける構成は、上記実施の形態1の構成と併用して用いてもよい。   With the above-described configuration, in addition to the effects of the first embodiment, since the same voltage is generally applied to the auxiliary capacitance line as the entire display device as described above, the same voltage is applied to the adjacent auxiliary capacitance lines. Is applied, and there is no inconvenience even if a short circuit occurs after the discharge, and it is possible to increase the portion having a dischargeable interval, and it is possible to more reliably prevent electrostatic breakdown. Although FIG. 3 shows the configuration in which the protruding portion is formed between the auxiliary capacitance line and the adjacent auxiliary capacitance line, the same configuration may be applied to the scanning line. However, if it is applied to the scanning line and is short-circuited with an adjacent scanning line after discharging, it will cause a display defect, so care must be taken when setting the dischargeable interval. The dischargeable interval between the scan line and the adjacent scan line is preferably about 5 to 10 μm in order to suppress a short circuit after discharge. For example, the scan line is cut off before the display device is completed, and discharge is possible between the scan line and a short ring formed of a conductive film in the same layer as the scan line at the periphery of the insulating substrate. By forming a portion having an interval (about 3 to 10 μm), it is possible to achieve the same effect as in the case of the auxiliary capacitance line. In this case, even if the short ring and the portion of the scanning line formed with a dischargeable interval are short-circuited after the discharge, the portion is cut off before the display device is completed as described above. , No problem arises. A configuration in which a dischargeable interval is provided between the short ring and the scanning line may be used in combination with the configuration of the first embodiment.

以上、上記実施の形態1、2においては、薄膜トランジスタを有する表示装置について説明しているが、これに限定されるものではなく、同一層の導電膜で並行に形成される少なくとも2種の信号線を有する表示装置に適用可能である。さらに、上記実施の形態においては、走査線と映像信号線とが、表示領域におけるそれぞれ異なる一辺側に引き出され、該それぞれ異なる一辺にそれぞれの外部接続端子が形成される場合について説明しているが、何れかの一辺に走査線と映像信号線の両方がの外部接続端子が形成される表示装置に適用してもよい。本発明は、同一層の導電膜で並行に形成される少なくとも2種の信号線を有する、液晶またはエレクトロルミネセンス(EL)素子などを用いたあらゆる表示装置に適用して好適なものである。   As described above, in the first and second embodiments, the display device having the thin film transistor has been described. However, the present invention is not limited to this, and at least two kinds of signal lines formed in parallel with the same layer of conductive film are used. It is applicable to a display device having Further, in the above-described embodiment, a case has been described in which the scanning lines and the video signal lines are drawn out to different one sides in the display area, and the respective external connection terminals are formed on the different sides. The present invention may be applied to a display device in which external connection terminals for both scanning lines and video signal lines are formed on any one side. The present invention is suitable for application to any display device using a liquid crystal or an electroluminescence (EL) element having at least two kinds of signal lines formed in parallel by the same conductive film.

本発明の実施の形態1における表示装置の等価回路図である。FIG. 3 is an equivalent circuit diagram of the display device in the first embodiment of the present invention. 図1における主要部の拡大図である。It is an enlarged view of the principal part in FIG. 本発明の実施の形態2における図1の主要部の拡大図である。It is an enlarged view of the principal part of FIG. 1 in Embodiment 2 of this invention.

符号の説明Explanation of symbols

1 絶縁性基板、2 表示領域、3 薄膜トランジスタ、4 走査線、5 映像信号線、6 補助容量、7 補助容量線、8 共通補助容量線、9 引き出し走査線、
10 引き出し映像信号線、11 走査線側外部接続端子、
12 映像信号線側外部接続端子、13 補助容量用外部接続端子、14 独立パターン、15 突起部
DESCRIPTION OF SYMBOLS 1 Insulating substrate, 2 Display area, 3 Thin-film transistor, 4 Scan line, 5 Video signal line, 6 Auxiliary capacity, 7 Auxiliary capacity line, 8 Common auxiliary capacity line, 9 Lead-out scanning line,
10 lead-out video signal line, 11 scanning line side external connection terminal,
12 video signal line side external connection terminal, 13 auxiliary capacity external connection terminal, 14 independent pattern, 15 protrusion

Claims (5)

絶縁性基板上に形成された表示領域を形成する画素と、
前記画素と接続される第1の信号線と、
前記第1の信号線と同一層の導電膜で、かつ前記第1の信号線と並行に形成され、前記第1の信号線と異なる信号を供給する第2の信号線と、
前記表示領域外の領域において、前記第1の信号線および前記第2の信号線と同一層の導電膜で形成され、かつ前記第1の信号線および前記第2の信号線のそれぞれに対し、放電可能な間隔を有した独立のパターンと、
を備えたことを特徴とする表示装置。
A pixel forming a display region formed on an insulating substrate;
A first signal line connected to the pixel;
A second signal line that is formed of a conductive film in the same layer as the first signal line and is formed in parallel with the first signal line, and supplies a signal different from the first signal line ;
In the region outside the display region, the first signal line and the second signal line are formed of a conductive film in the same layer, and each of the first signal line and the second signal line , An independent pattern with dischargeable spacing;
A display device comprising:
前記独立のパターンと、前記第1の信号線および前記第2の信号線のそれぞれとの放電可能な間隔は、3〜10μmであることを特徴とする請求項1記載の表示装置。 The display device according to claim 1, wherein a dischargeable distance between the independent pattern and each of the first signal line and the second signal line is 3 to 10 μm. 前記第2の信号線または前記第1の信号線は、表示領域外の領域において、前記第2の信号線と隣接する第2の信号線との間、または前記第1の信号線と隣接する第1の信号線との間に放電可能な間隔を有した、突起部を有することを特徴とする請求項1または2記載の表示装置。 The second signal line or the first signal line is adjacent to the first signal line or between the second signal line and the second signal line adjacent to the second signal line in a region outside the display region. The display device according to claim 1, further comprising a protrusion having a dischargeable gap between the first signal line and the first signal line . 絶縁性基板上に形成された表示領域を形成する画素を備えた表示装置の製造方法であって、
前記画素と接続される第1の信号線と、該第1の信号線と並行に前記第1の信号線と異なる信号を供給する第2の信号線を形成する工程と、
前記表示領域外の領域において、前記第1の信号線および前記第2の信号線のそれぞれに対し、放電可能な間隔を有した独立のパターンを形成する工程と、
が同一の製造工程であることを特徴とする表示装置の製造方法。
A method of manufacturing a display device including pixels that form a display region formed on an insulating substrate,
A first signal line connected to the pixel, and forming a second signal line said supplying the first different signal to the signal line in parallel with the first signal line,
Forming an independent pattern having a dischargeable interval for each of the first signal line and the second signal line in a region outside the display region;
Are the same manufacturing process, The manufacturing method of the display apparatus characterized by the above-mentioned.
前記独立のパターンと、前記第1の信号線および前記第2の信号線のそれぞれとの放電可能な間隔は、3〜10μmであることを特徴とする請求項4記載の表示装置の製造方法。 5. The method of manufacturing a display device according to claim 4, wherein a dischargeable interval between the independent pattern and each of the first signal line and the second signal line is 3 to 10 [mu] m.
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