JP4233967B2 - Display panel driving device and display device - Google Patents

Description

  The present invention relates to a generally rectangular display panel driving device arranged on the outer edge of a display panel to drive a display panel such as a liquid crystal display panel, and a display device such as a liquid crystal display device using the same.

  FIG. 9 shows a block configuration of a TFT (thin film transistor) type liquid crystal display device which is a typical example of a conventional active matrix type.

  The liquid crystal display device includes a liquid crystal display unit and a liquid crystal driving device 900 that drives the liquid crystal display unit. The liquid crystal display unit includes a TFT liquid crystal panel (display panel) 901. In the liquid crystal panel 901, a liquid crystal display element (not shown) and a counter electrode (common electrode) 906 described later are provided.

  On the other hand, the liquid crystal driving device 900 includes a source driver 902 and a gate driver 903 each made of an IC (Integrated Circuit) chip, a controller 904, and a liquid crystal driving power source 905.

  The source driver 902 and the gate driver 903 are generally a film in which the IC chip is mounted on a film with wiring, for example, a TCP (Tape Carrier Package), and an ITO (Indium Tin Oxide) of the liquid crystal panel 901. A method of mounting and connecting on a terminal such as a film) terminal, or thermocompression bonding the IC chip directly to a terminal such as an ITO terminal of the liquid crystal panel 901 via an ACF (Anisotropic Conductive Film). And connected to the liquid crystal panel 901 by a method of mounting and connecting.

  In order to cope with the downsizing of the liquid crystal display device, the controller 904, the liquid crystal driving power source 905, the source driver 902, and the gate driver 903 described above may be configured by one chip or by two to three chips. There is also. FIG. 9 shows these configurations separated by function.

  The controller 904 outputs digitized display data (for example, RGB signals corresponding to red, green, and blue) and various control signals to the gate driver 903.

  Main control signals to the source driver 902 include a horizontal synchronization signal, a start pulse signal, a source driver clock signal, and the like, which are indicated by S11 in the drawing. On the other hand, main control signals to the gate driver 903 include a vertical synchronization signal, a gate driver clock signal, and the like, which are indicated by S12 in the drawing. In the figure, a power source for driving each IC (source driver 902 and gate driver 903) is omitted.

  A liquid crystal driving power source 905 supplies a liquid crystal panel display voltage (reference voltage for generating a gradation display voltage) to the source driver 902 and the gate driver 903.

  Display data input from the outside is input as the display data D to the source driver 902 as a digital signal through the controller 904.

  The source driver 902 latches the input display data D in a time division manner, and then performs DA (digital-analog) conversion in synchronization with the horizontal synchronizing signal (also referred to as a latch signal Ls) input from the controller 904. To do. Then, the source driver 902 converts the analog voltage for gradation display obtained by DA conversion from a liquid crystal drive voltage output terminal (a liquid crystal drive voltage output terminal 1308 described later) via a source signal line 104 described later. The data is output to a liquid crystal display element (not shown) in the liquid crystal panel 901 corresponding to the liquid crystal drive voltage output terminal.

  The liquid crystal panel 901 will be described with reference to FIG. FIG. 10 shows the configuration of the liquid crystal panel 901. The liquid crystal panel 901 includes a pixel electrode 101, a pixel capacitor 102 made of liquid crystal, a TFT 103 as a switching element for turning on / off voltage application to the pixel capacitor 102, a source signal line 104, a gate signal line 105, and a counter electrode of the liquid crystal panel. 106 is provided. In the figure, a region indicated by A is a liquid crystal display element for one pixel, and is composed of one pixel electrode 101, a pixel capacitor 102 composed of liquid crystal in a portion overlapping with one pixel electrode 101, and one TFT 103. ing.

  The source signal line 104 is supplied with a gradation display voltage from the source driver 902 in accordance with the brightness of the display target pixel. The gate signal line 105 is supplied with a scanning signal from the gate driver 903 so that the TFTs 103 arranged in the vertical direction are sequentially turned on. The voltage of the source signal line 104 is applied to the pixel electrode 101 connected to the drain of the TFT 103 through the TFT 103 in the on state, and is accumulated in the pixel capacitor 102 between the counter electrode 106. Thereby, the light transmittance is changed in the liquid crystal, and display is performed.

  11 and 12 show an example of the liquid crystal driving waveform. In these drawings, drive waveforms 1101 and 1201 are drive waveforms of output signals from the source driver 902, and drive waveforms 1102 and 1202 are drive waveforms of output signals from the gate driver 903. Potentials 1103 and 1203 are counter electrode potentials, and voltage waveforms 1104 and 1204 are pixel electrode voltage waveforms. The voltage applied to the liquid crystal is a potential difference between the pixel electrode 101 and the counter electrode 106, and is indicated by hatching in the drawing.

  For example, in FIG. 11, when the output signal from the gate driver 903 indicated by the driving waveform 1102 is at a high level, the TFT 103 is turned on, and the difference between the output signal from the source driver 902 indicated by the driving waveform 1101 and the potential 1103 of the counter electrode 106. Is applied to the pixel electrode 101. Thereafter, as indicated by the drive waveform 1102, the output signal from the gate driver 903 goes to a low level, and the TFT 103 is turned off. At this time, since the pixel has the pixel capacitor 102, the above-described voltage is maintained. The same applies to the case of FIG.

  FIG. 11 and FIG. 12 show the case where the voltages applied to the liquid crystals are different. In the case of FIG. 12, the applied voltage is lower than in the case of FIG. In this way, by changing the voltage applied to the liquid crystal as an analog voltage, the light transmittance of the liquid crystal is changed in an analog manner to realize multi-gradation display. The number of gradations that can be displayed is determined by the number of analog voltage options applied to the liquid crystal.

  FIG. 13 shows a block diagram configuration of the source driver 902. Only the basic part will be described below. Each display data DR, DG, DB (for example, 6 bits each) transferred from the controller 904 is once latched by the input latch circuit 1301. The display data DR, DG, and DB correspond to red, green, and blue, respectively.

  On the other hand, the start pulse signal SSPI is synchronized with the clock signal SCK, transferred in the shift register circuit 1302, and output as a start pulse signal SSPO (cascade signal) from the final stage of the shift register circuit 1302 to the source driver of the next stage. The

  In synchronization with the output signal from each stage of the shift register circuit 1302, the display data DR, DG, and DB latched by the input latch circuit 1301 are temporarily stored in the sampling memory circuit 1303 in a time division manner. At the same time, it is output to the next hold memory circuit 1304.

  When display data for one horizontal synchronization period is stored in the sampling memory circuit 1303, the hold memory circuit 1304 takes in an output signal from the sampling memory circuit 1303 based on the horizontal synchronization signal (latch signal Ls), and the next horizontal synchronization is performed. The display data is maintained until a signal is input.

  The level shifter circuit 1305 converts the signal level of the display data by signal level boosting or the like in order to adapt the signal level of the display data to the DA conversion circuit 1306 of the next stage that performs processing related to the analog voltage applied to the liquid crystal panel 901. It is a circuit to do. The reference voltage generation circuit 1309 generates various analog voltages for gradation display based on the reference voltage VR from the liquid crystal driving power source 905 described above, and outputs the analog voltage to the DA conversion circuit 1306.

  The DA conversion circuit 1306 selects an analog voltage from various analog voltages supplied from the reference voltage generation circuit 1309 according to display data level-converted by the level shifter circuit 1305. The analog voltage representing the gradation display is output from each liquid crystal driving voltage output terminal 1308 to each source signal line of the liquid crystal panel 901 via the output circuit 1307. The output circuit 1307 is basically a buffer circuit, and is composed of, for example, a voltage follower circuit using a differential amplifier circuit.

  Next, FIG. 14 shows a connection configuration example between the electrode pad in the source driver 902 and the liquid crystal drive output circuit. Although not shown in FIG. 14, the liquid crystal drive output circuit 2003 is similar to the source driver 902 of FIG. 13 in that the shift register circuit 1302, the sampling memory circuit 1303, the hold memory circuit 1304, the level shifter circuit 1304, and the DA conversion circuit 1306 And an output circuit 1307.

  The source driver 902 includes a power supply terminal 2000, an input terminal 2001, and liquid crystal drive voltage output terminals 2002 (Y1 to Y384) as electrode pads. The source driver 902 generally has a rectangular planar shape. A plurality of electrode pads (liquid crystal drive voltage output terminals) 2002 (Y1 to Y384) for electrical connection between the metal wiring pattern 2005 and the liquid crystal drive output circuit 2003 are arranged along the periphery of the source driver 902 at a predetermined arrangement pitch. ing. The liquid crystal drive voltage output terminal 2002 is composed of 384 output terminals Y1 to Y384, which are arranged in parallel on the three sides or four sides (four sides in the figure) of the source driver chip. Electrode pads such as image signal input terminals 2001... And power supply terminals 2000... Are arranged on the side. A plurality of arranged liquid crystal drive output circuits 2003 are formed inside the liquid crystal drive voltage output terminal 2002, and the arrangement of the cells by the liquid crystal drive output circuit 2003 is regular in the arrangement order of the output circuit cells and the shift order of the shift registers. They are arranged in the same order (the same order as the arrangement order of the liquid crystal drive voltage output terminals 2002).

Patent Document 1 discloses a pair of connection pads connected to input / output signal external connection terminals provided at the left end and the right end of a tape carrier package base material, and an interior for electrically connecting the pair of connection pads. A liquid crystal driver IC having wiring is disclosed.
Japanese Laid-Open Patent Publication No. 6-3684 (published January 14, 1994; corresponding to Japanese Patent No. 2837027; see FIGS. 1 and 2)

  In recent years, price destruction of LCD panel products due to severe deflation has become more severe year by year not only for set manufacturers but also for component manufacturers, and further cost reductions can be achieved for source drivers, gate drivers, controllers, etc. The current situation is strongly demanded. In particular, the present invention is intended to reduce the cost of the source driver chip. Hereinafter, the problems of the prior art will be described.

  The conventional source driver chip shown in FIG. 14 generally has a rectangular planar shape as shown in FIG. 14, and a pad for electrical connection between the wiring pattern and the liquid crystal drive output circuit along its periphery, that is, Liquid crystal drive voltage output terminals (Y1 to Y384) are arranged in parallel on four sides at a predetermined arrangement pitch. Here, the arrangement of the cells of the liquid crystal drive output circuit is arranged in the same order (the same order as the arrangement order of the liquid crystal drive voltage output terminals 2002) in the order of arrangement of the output circuit cells and the shift order of the shift registers.

  However, when wiring patterns are routed from the cells of the liquid crystal drive output circuit arranged in ascending order to the liquid crystal drive voltage output terminals (Y1 to Y384) provided on the long side, stacking due to wiring may occur due to restrictions between the wirings. Since it concentrates, it has the problem that wiring efficiency worsens. As a result, the pattern area of the routing wiring is increased, and as a result, the external dimensions of the source driver chip are increased, resulting in an increase in manufacturing cost.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce the short side length by reducing the area of the routing wiring, thereby reducing the size and cost of the display panel drive. It is to provide a device and a display device.

  In order to solve the above problems, the display panel driving device of the present invention drives the display pixels with respect to a display panel including a plurality of display pixels and a plurality of drive wirings for driving the display pixels. A display panel driving device for applying a driving voltage to the display pixel via the driving wiring, the substrate having a rectangular shape or a similar shape, and the peripheral portion of the substrate, A plurality of electrode pads for outputting a drive voltage; a drive voltage output circuit for outputting the drive voltage to the display panel; and the drive voltage output circuit, disposed inside the electrode pads on the substrate. And a plurality of wirings that connect the electrode pads, and a part of the wiring passes from the connection point with the driving voltage output circuit through the region overlapping with the driving voltage output circuit, and the region and the outside of the region It is characterized in that the are routed drawn to the electrode pad across the portion of the substrate the short side at the boundary line.

  In the present specification, the term “rectangular shape or similar shape” includes, in addition to the rectangular shape, a shape obtained by deforming the rectangular shape so that the short side and the long side can be distinguished.

In order to solve the above problems, the display panel driving device of the present invention drives the display pixels with respect to a display panel including a plurality of display pixels and a plurality of drive wirings for driving the display pixels. A display panel driving device for applying a driving voltage for driving to the display pixel via the driving wiring, wherein a plurality of the driving voltages are arranged on a substrate and at a peripheral portion of the substrate for outputting the driving voltage. A drive voltage output circuit for outputting the drive voltage to the display panel, and the drive voltage output circuit and the electrode pad, which are disposed on the inner side of the electrode pad on the substrate. and a plurality of wirings, the driving voltage output circuit is divided into a plurality of blocks, a portion of the wiring from the connection point between the drive voltage output circuit, the electrode paths through the spaces between the blocks It is characterized by being pulled fucked up mode.

  Each of the above circuit cells typically has a shift register circuit for sequentially shifting the pulse signal, and sampling for storing the display data signal in a time division manner in synchronization with the pulse signal output from the shift register circuit. A memory circuit, a hold memory circuit for holding the display data signal output from the shift register circuit for a predetermined period, and then outputting it, and a level shifter circuit for converting the level of the display data signal output from the hold memory circuit A DA conversion circuit for selecting and outputting an analog voltage corresponding to the display data signal level-converted by the level shifter circuit from a plurality of types of analog voltages, and the analog voltage output from the DA conversion circuit to the display panel And an output circuit for outputting. The display panel is typically a liquid crystal display panel including liquid crystal as the display pixel.

  In order to solve the above problems, a display device of the present invention includes a display panel including a plurality of display pixels and a plurality of drive wirings for driving the display pixels, and a display panel drive device having the above-described configuration. It is characterized by that.

  A display panel driving device according to the present invention is disposed inside a rectangular substrate, a plurality of electrode pads arranged on the peripheral edge of the substrate for outputting the driving voltage, and an electrode pad on the substrate. A driving voltage output circuit for outputting the driving voltage to the display panel; and a plurality of wirings for connecting the driving voltage output circuit and the electrode pads. From the connection point to the electrode voltage pad through the region overlapping with the drive voltage output circuit and straddling the short side of the substrate on the boundary line between the region and the outside of the region.

  Therefore, a part of the wiring that has been routed around the outside of the driving voltage output circuit in the past is overlapped with the driving voltage output circuit, so that the wiring area outside the driving voltage output circuit (in order to arrange the wiring) Area required on the substrate) can be reduced, and the size of the short side length can be reduced. As a result, the present invention has the effect of providing a small and low-cost display panel driving device.

  In the display panel driving device, the driving voltage output circuit includes a plurality of circuit cells corresponding to individual driving wirings of the display panel arranged in the long side direction of the substrate, and the plurality of circuit cells are arranged in the circuit cells. The connected wiring is routed from the connection point with the circuit cell to the electrode pad through the area overlapping the drive voltage output circuit and straddling the short side of the substrate on the boundary line between that area and the outside of the area. The first circuit cell group and the wiring connected to the circuit cell are routed from the connection point with the circuit cell to the electrode pad without passing through the region overlapping the drive voltage output circuit. The first circuit cell group is arranged so that the arrangement order of the connection points between the circuit cell and the wiring is opposite to the arrangement order of the electrode pads connected to the circuit cell. And the second circuit cell If the arrangement is such that the arrangement order of the connection points between the circuit cell and the wiring is the same as the arrangement order of the electrode pads connected to the circuit cell, the following effects are further obtained. . That is, in this configuration, the arrangement order of the electrode pads matches the arrangement order of the drive wirings of the display panel, so that it is easy to use the normal specification TCP or the like for the current normal specification display panel. Can be connected.

  In the display panel driving device, each circuit cell includes a shift register, and the plurality of circuit cells have a shift order between shift registers in the first circuit cell group. If the arrangement is arranged in the reverse order of the shift order, the following effects are further obtained. That is, in this configuration, the arrangement order of the electrode pads matches the arrangement order of the drive wirings of the display panel, so that it is easy to use the normal specification TCP or the like for the current normal specification display panel. Can be connected.

  In the display panel driving device, the driving voltage output circuit includes a plurality of circuit cells corresponding to individual driving wirings of the display panel arranged in the long side direction of the substrate, and the plurality of circuit cells are arranged in the circuit cells. The connected wiring is routed from the connection point with the circuit cell to the electrode pad through the area overlapping the drive voltage output circuit and straddling the short side of the substrate on the boundary line between that area and the outside of the area. The first circuit cell group and the wiring connected to the circuit cell are routed from the connection point with the circuit cell to the electrode pad without passing through the region overlapping the drive voltage output circuit. Each of the circuit cells includes a shift register, and the plurality of circuit cells have a shift order between the shift registers in the first circuit cell group, the shift register in the second cell group. If arranged Configurations such that the shift in the reverse order during further has the following effects. That is, in this configuration, the arrangement order of the electrode pads matches the arrangement order of the drive wirings of the display panel, so that it is easy to use the normal specification TCP or the like for the current normal specification display panel. Can be connected.

In the display panel driving device, the driving voltage output circuit is divided into a plurality of blocks, and a part of the wiring is routed from a connection point with the driving voltage output circuit to the electrode pad through a space between the blocks. If so, the following effects are further obtained. In other words, in this configuration, a part of the wiring that has been conventionally routed to the long side region outside the drive voltage output circuit to increase the size of the short side length is replaced with a space between the blocks of the liquid crystal drive output circuit. As a result, the width of the wiring region on the long side outside the drive voltage output circuit (the size of the short side of the substrate) can be reduced, and the size of the short side can be reduced. As a result, the present invention has the effect of providing a small and low-cost display panel driving device.

Further, the display panel driving device of the present invention is arranged on the inner side of the substrate, the plurality of electrode pads arranged on the peripheral edge of the substrate for outputting the driving voltage, and the electrode pad on the substrate. A drive voltage output circuit for outputting the drive voltage to the display panel;
A plurality of wirings for connecting the driving voltage output circuit and the electrode pad, the driving voltage output circuit is divided into a plurality of blocks, and a part of the wiring is connected to a connection point with the driving voltage output circuit. In this configuration, the electrode pads are routed through the space between the blocks.

Therefore, part of the wiring that has been conventionally routed to the long side area outside the drive voltage output circuit and has increased the size of the short side length is routed through the space between the blocks of the drive voltage output circuit. As a result, the width of the wiring region on the long side outside the drive voltage output circuit (the size of the short side of the substrate) can be reduced, and the size of the short side can be reduced. As a result, the present invention has the effect of providing a small and low-cost display panel driving device.

  In addition, according to the present invention, since the display panel including the plurality of display pixels and the plurality of drive wirings for driving the display pixels and the display panel driving device having the above configuration are provided, a small and low-cost display is provided. There exists an effect that an apparatus can be provided.

[Embodiment 1]
Embodiments of a liquid crystal drive device and a drive circuit thereof according to the present invention will be described with reference to the drawings.

An embodiment of the present invention will be described below with reference to the drawings.
The liquid crystal panel configuration and the liquid crystal driving waveform of the liquid crystal display device including the liquid crystal driving device described below are the same as the conventional configuration described above with reference to FIGS. The description is omitted here. Below, the drive circuit (source driver) of the liquid crystal drive device, which is a feature of the present invention, will be mainly described.

  FIG. 1 shows a block configuration of a TFT (Thin Film Transistor) type liquid crystal display device which is a typical example of an active matrix type in an embodiment of the present invention.

  The liquid crystal display device includes a liquid crystal display unit and a liquid crystal driving device 10 that drives the liquid crystal display unit. The liquid crystal display unit includes a TFT liquid crystal panel 11. In the liquid crystal panel 11, a liquid crystal display element made up of liquid crystal, pixel electrodes, TFTs and the like (not shown) and a counter electrode (common electrode) 16 described later are provided. Further, in the liquid crystal panel 11, although not shown, a source signal line (drive wiring) for supplying a signal from a source driver (display panel driving device) 12 described later to a TFT of a liquid crystal display element (not shown). And a gate signal line for supplying a signal from the gate driver 13 to a liquid crystal display element (not shown).

  On the other hand, the liquid crystal driving device 10 includes a source driver (display panel driving device) 12 and a gate driver 13 each composed of an IC (Integrated Circuit), a controller 14, and a liquid crystal driving power source 15.

  The source driver 12 and the gate driver 13 are generally a method in which the IC chip is mounted on a film with wiring, for example, a TCP is mounted on a terminal such as an ITO terminal of the liquid crystal panel 11 and connected. The IC chip is connected to the liquid crystal panel 11 by a method in which the IC chip is directly bonded to a terminal such as an ITO terminal of the liquid crystal panel 11 via an ACF (Anisotropic Conductive Film) and is connected. ing.

  In order to cope with the downsizing of the liquid crystal display device, the controller 14, the liquid crystal driving power source 15, the source driver 12, and the gate driver 13 may be configured by one chip or by two to three chips. . In FIG. 1, these structures are shown in a form separated by function.

  The controller 14 outputs digitized display data (for example, RGB signals corresponding to red, green, and blue) and various control signals to the gate driver 13.

  Main control signals to the source driver 12 include a horizontal synchronization signal, a start pulse signal, a source driver clock signal, and the like, which are indicated by S11 in the drawing. On the other hand, main control signals to the gate driver 13 include a vertical synchronization signal, a gate driver clock signal, and the like, which are indicated by S12 in the drawing. In the figure, a power source for driving each IC is omitted.

  The liquid crystal drive power supply 15 supplies the source driver 12 and the gate driver 13 with a liquid crystal panel display voltage (a reference voltage for generating a gradation display voltage as related to the present invention).

  Display data D input from the outside is input as the display data D to the source driver 12 as a digital signal through the controller 14.

  The source driver 12 latches the input display data internally in a time division manner, and then performs DA (digital-analog) conversion in synchronization with the horizontal synchronization signal (also referred to as a latch signal Ls) input from the controller 14. Do. Then, the source driver 12 converts the analog voltage for gradation display (drive voltage for driving the display pixels of the liquid crystal panel 11) obtained by DA conversion into a liquid crystal drive voltage output terminal (electrode pad) 1002 (described later). Therefore, the liquid crystal drive voltage output terminal via a plurality of source signal lines (drive wirings for driving display pixels of the liquid crystal panel 11) in the liquid crystal panel 11 corresponding to the liquid crystal drive voltage output terminal 1002 Are respectively output (applied) to liquid crystal display elements (display pixels; not shown) in the liquid crystal panel 11.

  Next, FIG. 2 shows a connection configuration example between the electrode pad and the liquid crystal drive output circuit in the source driver 12.

  The source driver 12 is configured by forming various circuits and wiring patterns on a rectangular substrate 1007. The source driver 12 has a planar shape.

  In the source driver 12, a plurality of liquid crystal driving voltage output terminals 1002 for electrical connection between a metal wiring pattern 1005 composed of a plurality of metal wirings and a liquid crystal driving output circuit 1003 are arranged at a predetermined arrangement pitch along the periphery of the substrate 1007. It is arranged. The liquid crystal drive voltage output terminal 1002 is an output terminal for outputting the analog voltage for gradation display (drive voltage for driving the display pixels of the liquid crystal panel 11) to the liquid crystal panel 11. The source driver 12 of this embodiment has 384 output terminals (electrode pads) Y1 to Y384 as the liquid crystal drive voltage output terminals 1002. The output terminals Y1 to Y384 are arranged in parallel on the four sides of the source driver 12 (four sides of the substrate 1007) as electrode pads electrically connected to the liquid crystal panel 11. On the other long side, in addition to the liquid crystal drive voltage output terminal 1002, a plurality of power supply terminals (electrode pads) 1000, a plurality of input terminals (electrode pads) 1001, and the like are provided.

  The electrode pads 1000 to 1002 are disposed on the peripheral edge of one surface of the substrate 1007. That is, on the surface of the substrate 1007, electrode pads 1000, 1001, and 1002 are formed as a large number of electrodes along both long sides and both short sides of the substrate 1007.

  The electrode pads 1000 to 1002 have gold bumps (not shown) formed by plating on pads made of metal other than gold such as copper and aluminum connected to a metal wiring pattern 1005 described later. It is configured. The height of the gold bump and the size in the planar direction vary depending on the bump pitch (interval between the gold bump and the gold bump). For example, typically, the gold in the planar direction has a size of 40 to 90 μm and a height of 10 to 20 μm. Bumps are used.

  A liquid crystal for outputting the analog voltage for gradation display (drive voltage for driving the display pixel of the liquid crystal panel 11) to the liquid crystal panel 11 on the substrate 1007 inside the electrode pads 1000 to 1002. A drive output circuit (drive voltage output circuit) 1003 and a control circuit 1004 including a reference voltage generation circuit (not shown) and an input latch circuit (not shown) are provided. Each metal wiring of the metal wiring pattern 1005 connects one circuit cell (described later) constituting the liquid crystal driving output circuit 1003 and one liquid crystal driving voltage output terminal 1002.

  FIG. 3 shows a more detailed circuit configuration example of the liquid crystal drive output circuit 1003. The liquid crystal drive output circuit 1003 in FIG. 3 is formed by arranging a plurality of circuit cells corresponding to individual source signal lines (drive wirings) of the liquid crystal panel 11 in the long side direction of the substrate 1007, and each circuit cell is shifted. A register circuit (shift register) 302, a sampling memory circuit 303, a hold memory circuit 304, a level shifter circuit 305, a DA conversion circuit 306, and an output circuit 307 are provided. Hereinafter, each circuit cell is represented by reference numerals (Y1 to Y384) of electrode pads connected thereto.

The function of the basic part will be described below. The control circuit 1004 includes a reference voltage generation circuit 300 and an input latch circuit (not shown). The reference voltage generation circuit 300 generates m kinds of analog voltages corresponding to the display data gradation number m (m is 4 or more) and outputs it to the DA conversion circuit 306. For example, the display data is RGB. Display data (display digital signal; display data signal) DR, DG, and DB, and the display data DR, DG, and DB are each composed of a 6-bit digital signal, the reference voltage generation circuit 300 64 analog voltages V0 to V63 corresponding to 2 ⁶ = 64 gradation display are generated from 64 types of reference voltages VRi (64 values selected from i = 0 to 63), and DA conversion is performed. Output to the circuit 306.

  The input latch circuit 301 is configured to temporarily latch each display data DR, DG, and DB transferred from the controller 14. The control circuit 1004 is a circuit that controls a clock and the like related to the shift register.

  The shift register circuit 302 synchronizes with a clock signal, sequentially shifts a start pulse signal input from the outside at each stage, and outputs it as an output signal (pulse signal). The sampling memory circuit 303 temporarily stores the display data DR, DG, and DB latched by the previous input latch circuit 301 in a time-sharing manner in synchronization with the output signal from each stage of the shift register circuit 302. To the next hold memory circuit 304.

  The hold memory circuit 304 holds the display data output from the shift register circuit 302 after holding it for a predetermined period (generally one horizontal synchronization period). Specifically, when display data for one horizontal synchronization period is stored in the sampling memory circuit 303, the hold memory circuit 304 captures an output signal from the sampling memory circuit 303 based on the horizontal synchronization signal (latch signal Ls). The display data is maintained until the next horizontal synchronizing signal is input.

  The level shifter circuit 305 is a signal level such as a signal level booster for the display data in order to adapt the signal level of the display data to the DA conversion circuit 306 in the next stage that performs processing related to the analog voltage applied to the liquid crystal panel 11. It is a circuit that performs the conversion.

  The DA conversion circuit 306 selects an analog voltage corresponding to the display data level-converted by the level shifter circuit 305 from a plurality of types of analog voltages supplied from the reference voltage generation circuit 300. The analog voltage representing the gradation display is output from each liquid crystal driving voltage output terminal (electrode pad) 1002 (Y1 to Y384) to each source signal line of the liquid crystal panel via the output circuit 307.

  The output circuit 307 is basically a buffer circuit that buffers the analog voltage output from the DA conversion circuit 306, and is configured by a voltage follower circuit using a differential amplifier circuit, for example. Note that one output terminal includes one liquid crystal drive output circuit 1003.

  In the source driver 12 of the present embodiment, among the plurality of wirings constituting the metal wiring pattern 1005, the long side or the short side that is far from the connection point between the metal wiring pattern 1005 and the liquid crystal drive output circuit 1003 on the substrate 1007. The wiring connected to the output terminals Y1 to Y39 and Y344 to Y384 arranged on the side passes from the connection point with the liquid crystal drive output circuit 1003 through the region overlapping the liquid crystal drive output circuit 1003, and the region and the region It is routed to the liquid crystal drive voltage output terminal 1002 across the portion on the short side of the substrate 1007 on the boundary line with the outside (in this case, the short side of the substrate 1007).

  As a result, a part of the wiring that was conventionally routed to the area outside the liquid crystal drive output circuit 1003 is overlapped with the liquid crystal drive output circuit 1003, so that the wiring area outside the liquid crystal drive output circuit 1003 (metal wiring) The area of a region on the substrate 1007 necessary for disposing the pattern 1005) can be reduced, and the size of the short side length of the source driver 12 can be reduced. As a result, the present invention can provide a small and low-cost source driver 12.

  In addition, since a plurality of metal wirings composed of multi-layer metal wirings can be stacked on the output circuit 307 (effective use of wiring patterns is possible), as a result, the short side length of the source driver 12 Can be realized.

  Note that the wiring passing through the region overlapping with the liquid crystal drive output circuit 1003 is preferably formed of a wiring pattern of two or more layers. In addition, a wiring for connecting a circuit cell belonging to the second circuit cell group and the electrode pad is formed with a wiring pattern of two or more layers, and a wiring for connecting the circuit cell belonging to the first circuit cell group and the electrode pad. It is also preferable to form a wiring pattern having three or more layers. According to these, the wiring area can be further reduced.

  In the source driver 12 of the present embodiment, the arrangement order of the circuit cells of the liquid crystal drive output circuit 1003 is not all in ascending order, and the region of the metal wiring pattern 1005 from the liquid crystal drive output circuit 1003 to the liquid crystal drive voltage output terminal 1002 Therefore, a part of the arrangement order of the circuit cells of the liquid crystal drive output circuit 1003 is changed to the reverse order of the ascending order.

  That is, in the plurality of circuit cells, the wiring connected to the circuit cell passes through a region overlapping with the liquid crystal driving output circuit 1003 from the connection point with the circuit cell, and the substrate 1007 at the boundary line between the region and the outside of the region. The first circuit cell group (circuit cells Y1 to Y39 and circuit cells Y344 to Y384) routed to the electrode pad across the short side portion and the wiring connected to the circuit cell are connected to the circuit cell. A second circuit cell group (circuit cells Y40 to Y193 and circuit cells Y194 to Y343) routed from the connection point to the electrode pad without passing through the region overlapping with the drive voltage output circuit, and the first circuit In the cell group, the arrangement order of the connection points between the circuit cell and the wiring is the arrangement order of the output terminals Y1 to Y39 and Y344 to Y384 connected to the circuit cell (ascending order from the right side of the figure). The second circuit cell group is arranged in the reverse order (descending order from the right side of the figure), and the second circuit cell group has an arrangement order of connection points between the circuit cells and wiring (an arrangement order along the periphery of the substrate). The output terminals Y40 to Y193 and Y194 to Y343 connected to the circuit cell are arranged in the same order as the arrangement order (ascending order from the right side of the figure).

  As a result, a plurality of metal wirings composed of multi-layer metal wirings can be stacked on the output circuit 307 (effective use of the metal wiring pattern is possible). The side length can be reduced.

  In the source driver 12 of the present embodiment, the shift order between the shift register circuits 302 of the liquid crystal drive output circuit 1003 is switched corresponding to the switching of the arrangement order of the circuit cells. That is, in the source driver 12 of the present embodiment, the shift order (transfer order) between the shift register circuits 302 in the first circuit cell group is the same as the shift order between the shift register circuits 302 in the second cell group. They are arranged in the reverse order.

  4 and 5 show the relationship between the cell arrangement order of the liquid crystal drive output circuit 1003 arranged in the source driver 12 and the shift direction of the start pulse signal (start signal) SSPI transferred through the shift register circuit 302. FIG. . 4 and 5 each show an example of the shift direction of the start pulse signal SSPI transferred in the shift register circuit 302, FIG. 4 shows an example of left shift Y1 → Y384, and FIG. 5 shows an example of right shift Y384 → Y1. Each is shown.

  In the example of FIG. 4, the start pulse signal SSPI is transferred in the direction from left to right in FIG. 4 in the circuit cells Y1 to Y39 (S1), and the circuit cell Y39 to the circuit cell Y40 is transferred from right to left in FIG. In the circuit cells Y40 to Y343, the start pulse signal SSPI is transferred from the right to the left in FIG. 4 (S3 / S4), and the circuit cell Y343 to the circuit cell Y344 is transferred to the right in FIG. From the left to the right in FIG. 4 in the circuit cells Y344 to Y384 (S6).

  As a result, a plurality of metal wirings composed of multilayer metal wirings can be stacked on the output circuit 307 (effective use of the wiring pattern is possible). As a result, the short side length of the source driver Can be reduced.

  In the example of FIG. 5, the start pulse signal SSPI is transferred in the direction from right to left in FIG. 5 in the circuit cells Y344 to Y384 (S1), and the circuit cell Y344 to the circuit cell Y343 is transferred from left to right in FIG. In the circuit cells Y40 to Y343, the start pulse signal SSPI is transferred from the left to the right in FIG. 5 (S3 · S4), and the circuit cell Y40 to the circuit cell Y39 is shifted to the left in FIG. From the right to the left in FIG. 5 in the circuit cells Y1 to Y39 (S1).

  In order to realize the flow of the start pulse signal SSPI as shown in S2 of FIG. 4, it is necessary to add a special wiring for transferring the start pulse signal SSPI between circuit cells at distant positions. Become. However, the wiring required here is wiring for connecting the shift register circuits 302 belonging to different circuit cells.

  For the wiring connecting the shift register circuits 302, the layout is usually performed using a metal wiring having a fine wiring width (about 1.0 μm per line). Therefore, an increase in the area of the routing wiring region in the source driver 12 due to an increase in the number of wirings connecting the shift register circuits 302 is relatively small.

  On the other hand, the wiring (metal wiring pattern 1005) outside the liquid crystal drive output circuit 1003 is usually laid out using a metal wiring pattern having a thick wiring width of about 5.0 μm per line in consideration of wiring resistance and the like. I do. Therefore, as the number of wirings (number of output terminals) outside the liquid crystal driving output circuit 1003 increases, the area of the routing wiring region in the source driver 12 increases remarkably. Therefore, the increase in the area of the routing wiring region in the source driver 12 due to the increase in the number of wirings outside the liquid crystal drive output circuit 1003 is relatively large.

  Therefore, the amount of increase in the area of the routing wiring area in the source driver 12 due to the addition of one wiring connecting the shift register circuits 302 is that in the source driver 12 due to the reduction in the number of wirings outside the liquid crystal driving output circuit 1003. Compared to the amount of reduction in the area of the routing wiring area, the amount is small and has almost no effect. Therefore, in the present invention, it is possible to reduce the area of the routing wiring region in the source driver 12 and to reduce the outer dimension of the short side length of the source driver 12.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those used in Embodiment 1 will be described with the same reference numerals.

  In the first embodiment, the region of the metal wiring pattern 1005 from the liquid crystal drive output circuit 1003 to the liquid crystal drive voltage output terminal 1002 has a liquid crystal drive output so that the short side length (chip short side length) of the source driver 12 can be reduced. The arrangement order of the circuit cells of the circuit 1003 is rearranged in an ascending order (the same order as the arrangement order of the corresponding electrode pads).

  On the other hand, in the second embodiment, the arrangement order of each circuit cell is rearranged in the reverse order to the ascending order (the same order as the arrangement order of the corresponding electrode pads). As shown in FIG. 6, the liquid crystal drive output circuit 1003 is divided into four blocks 1003-1 to 1003-4, and a part of the metal wiring pattern 1005 that connects the liquid crystal drive output circuit 1003 and the liquid crystal drive voltage output terminal 1002 is formed. From the connection point with the liquid crystal drive output circuit 1003, the liquid crystal drive voltage output terminal 1002 is routed through the space between the blocks 1003-1 and 1003-2 and the space between the blocks 1003-3 and 1003-4. That is, the blocks 1003-1 and 1003- are arranged such that the metal wiring pattern 1005 passes between the blocks 1003-1 and 1003-2 and between the blocks 1003-3 and 1003-4 in the liquid crystal drive output circuit 1003. A wiring space region 1006 for arranging the metal wiring pattern 1005 is provided between the two blocks and between the blocks 1003-3 and 1003-4. A part of the wiring constituting the metal wiring pattern 1005 includes a plurality of power supply terminals (electrode pads) 1000 provided at the edge of one long side and a plurality of input terminals via the wiring space region 1006. (Electrode pad) It is configured to be connected to a liquid crystal drive voltage output terminal (electrode pad) 1002 for electrical connection with a liquid crystal drive output circuit 1003 arranged in a column on the 1001 side. The invention according to the second embodiment is configured such that the size of the short side of the source driver 12 (the chip size of the short side) is further smaller than that of the first embodiment, thereby reducing the chip area. The purpose is to plan.

  In the liquid crystal drive output circuit 1003, the metal wiring pattern 1005 is passed between the block 1003-1 and the block 1003-2 and between the block 1003-3 and the block 1003-4, so that the long side of the source driver 12 However, since the size of the short side (the chip size on the short side) of the source driver 12 can be further reduced, the planar size (chip area) of the source driver 12 can be reduced. ) Can be reduced.

  FIG. 6 shows a connection configuration example between the electrode pad in the source driver 12 and the liquid crystal drive output circuit 1003 according to another embodiment of the present invention.

  The source driver 12 is configured by forming various circuits and wiring patterns on a rectangular substrate 1007. The source driver 12 has a planar shape.

  In the source driver 12, a plurality of liquid crystal driving voltage output terminals 1002 for electrical connection between a metal wiring pattern 1005 composed of a plurality of metal wirings and a liquid crystal driving output circuit 1003 are arranged at a predetermined arrangement pitch along the periphery of the substrate 1007. It is arranged. The liquid crystal drive voltage output terminal 1002 is an output terminal for outputting the analog voltage for gradation display (drive voltage for driving the display pixels of the liquid crystal panel 11) to the liquid crystal panel 11. The source driver 12 of this embodiment has 384 output terminals (electrode pads) Y1 to Y384 as the liquid crystal drive voltage output terminals 1002. The output terminals Y1 to Y384 are arranged in parallel on the four sides of the source driver 12 (four sides of the substrate 1007) as electrode pads electrically connected to the liquid crystal panel 11. On the other long side, in addition to the liquid crystal drive voltage output terminal 1002, a plurality of power supply terminals (electrode pads) 1000, a plurality of input terminals (electrode pads) 1001, and the like are provided.

  The electrode pads 1000 to 1002 are disposed on the peripheral edge of one surface of the substrate 1007. That is, on the surface of the substrate 1007, electrode pads 1000, 1001, and 1002 are formed as a large number of electrodes along both long sides and both short sides of the substrate 1007.

  The electrode pads 1000 to 1002 have gold bumps (not shown) formed by plating on pads made of metal other than gold such as copper and aluminum connected to a metal wiring pattern 1005 described later. It is configured. The height of the gold bump and the size in the planar direction vary depending on the bump pitch (interval between the gold bump and the gold bump). For example, typically, the gold in the planar direction has a size of 40 to 90 μm and a height of 10 to 20 μm. Bumps are used.

  A liquid crystal for outputting the analog voltage for gradation display (drive voltage for driving the display pixel of the liquid crystal panel 11) to the liquid crystal panel 11 on the substrate 1007 inside the electrode pads 1000 to 1002. A drive output circuit (drive voltage output circuit) 1003 and a control circuit 1004 including a reference voltage generation circuit (not shown) and an input latch circuit (not shown) are provided. Each metal wiring of the metal wiring pattern 1005 connects one circuit cell (described later) constituting the liquid crystal driving output circuit 1003 and one liquid crystal driving voltage output terminal 1002.

  6 includes a block 1003-1 including circuit cells Y344 to Y364, a block 1003-2 including circuit cells Y194 to Y343 and Y365 to Y384, and circuit cells Y1 to Y19 and Y41 to Y193. The block 1003-3 is divided into four blocks, and the block 1003-4 is composed of circuit cells Y20 to Y40. The liquid crystal drive output circuit 1003 may be divided into a plurality of blocks other than four.

  FIG. 7 shows a more detailed circuit configuration example of the liquid crystal drive output circuit 1003. As already described with reference to FIG. 6, the liquid crystal drive output circuit 1003 is divided into four blocks 1003-1 to 1003-4, and the block 1003-1 and the block 1003-2 in the liquid crystal drive output circuit 1003 are configured. Between the blocks 1003-1 and 1003-2 and between the blocks 1003-3 and 1003-4 so that the metal wiring pattern 1005 passes between the blocks 1003-3 and 1003-4. A wiring space area 1006 for arranging 1005 is provided. The wiring connected to the circuit cells Y365 to Y384 of the block 1003-2 and the circuit cells Y1 to Y19 of the block 1003-3 is connected to one long side (metal wiring on the substrate 1007) via the wiring space region 1006. Output provided at the edge of the long side far from the connection point between the pattern 1005 and the liquid crystal drive output circuit 1003, that is, at the edges of the plurality of power supply terminals (electrode pads) 1000 and input terminals (electrode pads) 1001. Terminals (electrode pads) Y1 to Y19 and Y365 to Y384 are connected.

  Further, the wiring connected to the output terminals (electrode pads) Y1 to Y19 and Y365 to Y384 passes from the connection point with the liquid crystal drive output circuit 1003 through the region overlapping with the liquid crystal drive output circuit 1003, and the region and the outside of the region. Is routed to the liquid crystal drive voltage output terminal 1002 across the portion on the short side of the substrate 1007 (in this case, the short side of the substrate 1007). The arrangement order of the circuit cells Y1 to Y19 and Y365 to Y384 of the liquid crystal drive output circuit 1003 is such that the region of the metal wiring pattern 1005 from the liquid crystal drive output circuit 1003 to the liquid crystal drive voltage output terminal (electrode pad) 1002 As in FIG. 3, the output terminals Y1 to Y19 and Y365 to Y384 connected to the circuit cells Y1 to Y19 and Y365 to Y384 are not arranged in the ascending order (ascending order). Arranged in reverse order. Further, the shift order of the shift register circuit 302 of the circuit cells Y1 to Y19 and Y365 to Y384 is also switched to the reverse order of the shift order of the other circuit cells. Since the other configuration is the same as that of FIG. 3, the description thereof is omitted here.

  FIG. 8 shows the liquid crystal drive output circuit 1003 and the metal wiring pattern 1005 around it. The metal wiring for connecting the liquid crystal driving output circuit 1003 and the liquid crystal driving voltage output terminal (electrode pad) 1002 according to the present invention includes two-layer metal wiring (2MR wiring) and three-layer metal wiring (3MR wiring). ) And both. The three-layer metal wiring (3MR wiring) is used for the circuit cells Y1 to Y19 and Y365 to Y384, and the liquid crystal driving voltage output terminal 1002 (output terminals Y1 to Y19 and Y365) from the inside of the liquid crystal driving output circuit 1003. To Y384). As a result, the stacking (upper side) of wiring can be reduced, and the size of the source driver 12 in the short side direction (chip size on the short side) can be reduced as in the first embodiment. Further, the metal wiring (2MR wiring) composed of the two layers is used for the circuit cells Y20 to Y364, but the stacking of the 2MR wirings, that is, the height H can be reduced.

  In the present embodiment, in order to further reduce the height H of the 2MR wiring, the metal wiring pattern 1005 is provided between the block 1003-1 and the block 1003-2 in the liquid crystal drive output circuit 1003 and between the block 1003-3 and the block 1003. -4, a wiring space region 1006 is provided, and a plurality of power supply terminals (electrode pads) 1000 provided on the edge of one long side from the liquid crystal drive output circuit 1003 are provided. It is connected to a liquid crystal drive voltage output terminal (electrode pad) 1002 arranged in a column on the input terminal (electrode pad) 1001 side. As a result, the height H of the 2MR wiring can be reduced, and as a result, it is possible to further reduce the size of the source driver 12 in the short side direction (chip size on the short side).

  In the present embodiment, as in the first embodiment, the arrangement order of part of the circuit cells is changed in the reverse order to the arrangement order of FIG. 14, and the wiring connecting the circuit cells and the electrode pads is changed to the liquid crystal drive output circuit. The circuit 1003 is routed through the region overlapping with the circuit 1003. However, the arrangement order of all the circuit cells is matched with the arrangement order of FIG. 14, and the wiring connecting all the circuit cells and the electrode pads is passed through the region overlapping with the liquid crystal drive output circuit 1003. You may circulate without. Also in this case, the size of the source driver 12 in the short side direction (chip size on the short side) can be reduced as compared with the conventional configuration of FIG.

  In the first embodiment and the second embodiment, a part of the wiring is routed through a region overlapping with the liquid crystal drive output circuit 1003, and the arrangement order of the circuit cells connected to the part of the wiring is the arrangement order of 14. Although the order has been changed in the reverse order, it is possible to simply route a part of the wiring through a region overlapping with the liquid crystal drive output circuit 1003 so that the arrangement order of all circuit cells remains the same as the arrangement order of 14. In this configuration, since the arrangement order of the electrode pads does not coincide with the arrangement order of the drive wirings of the display panel, it is necessary to partially change the connection order of the electrode pads and the source signal lines of the display panel.

  Although an example in which the present invention is applied to a source driver has been described here, the present invention can also be applied to a gate driver. Although the display panel driving device for driving the TFT type liquid crystal panel has been described here, the present invention can be applied to a driving device for driving another type of liquid crystal panel, for example, a simple matrix type liquid crystal panel. The present invention can also be applied to matrix display panels other than liquid crystal panels, such as TFT organic EL panels.

  As described above, the liquid crystal display device and the driving circuit thereof according to the present invention include a rectangular semiconductor element disposed on the outer edge of the liquid crystal display panel to drive the liquid crystal display device, and the semiconductor element is generally a rectangular plane. The semiconductor element has an input terminal for image signal input, a power supply terminal, and an electrode pad for a liquid crystal drive voltage output terminal formed on the semiconductor element, and a metal wiring pattern and a liquid crystal drive along its periphery. A plurality of pads for electrical connection with the output circuit are arranged at a predetermined arrangement pitch, the liquid crystal drive output circuit is composed of a plurality of circuit cells, and the arrangement order of each cell of the shift register provided in the liquid crystal drive output circuit Is a configuration in which the shift order of the shift registers is changed.

  Further, as described above, the liquid crystal display device and the drive circuit thereof according to the present invention include a rectangular semiconductor element disposed on the outer edge of the liquid crystal display panel to drive the liquid crystal display device, and the semiconductor element is generally rectangular. The semiconductor element is formed with an input terminal for image signal input and a power supply terminal and an electrode pad for liquid crystal drive voltage output terminal on the semiconductor element, and a metal wiring pattern along the periphery thereof. A plurality of pads for electrical connection with the liquid crystal drive output circuit are arranged at a predetermined arrangement pitch, the liquid crystal drive output circuit is composed of a plurality of circuit cells, and the arrangement order of the cells of the liquid crystal drive output circuit is changed. It is the structure arranged.

  As described above, in the liquid crystal display device having the above-described configuration and its driving circuit, each of the cells includes a shift register circuit, a sampling memory circuit, a hold memory circuit, a level shifter circuit, a DA conversion circuit, and an output circuit. Also good.

  Further, as described above, in the liquid crystal display device having the above-described configuration and its driving circuit, the arrangement order of the shift registers provided in the liquid crystal driving output circuit is arranged by changing the shift order of the shift registers. It may be a configuration.

  Further, as described above, in the liquid crystal display device having the above-described configuration and its drive circuit, a plurality of metal multilayer metal wiring patterns may be stacked on the liquid crystal drive output circuit.

  Further, as described above, the liquid crystal display device and the drive circuit thereof according to the present invention include a rectangular semiconductor element disposed on the outer edge of the liquid crystal display panel to drive the liquid crystal display device, and the semiconductor element is generally rectangular. The semiconductor element has an input terminal for image signal input, a power supply terminal, and an electrode pad for liquid crystal drive voltage output terminal formed on the semiconductor element, and a metal wiring pattern and a liquid crystal around it. A plurality of pads for electrical connection with the drive output circuit are arranged at a predetermined arrangement pitch, and the liquid crystal drive output circuit is formed with a plurality of blocks composed of cells, and a dedicated metal wiring is provided between the blocks. A wiring space area is provided, and the metal wiring from the liquid crystal driving output circuit is connected to a pad for a liquid crystal driving voltage output terminal via a wiring space area dedicated to metal wiring. A configuration that is.

  As described above, in the liquid crystal display device having the above-described configuration and its driving circuit, each of the cells includes a shift register circuit, a sampling memory circuit, a hold memory circuit, a level shifter circuit, a DA conversion circuit, and an output circuit. Also good.

  Further, as described above, in the liquid crystal display device having the above-described configuration and its driving circuit, the arrangement order of the shift registers provided in the liquid crystal driving output circuit is arranged by changing the shift order of the shift registers. It may be a configuration.

  In addition, as described above, the liquid crystal display device having the above-described configuration and its driving circuit have two layers of metal wiring (2MR) as wiring for connecting the liquid crystal driving output circuit and the liquid crystal driving voltage output terminal pad. ) And a three-layer metal wiring (3MR) are used, and the three-layer metal wiring (3MR) is connected to the liquid crystal drive voltage output terminal pad from the inside of the chip. It may be.

  According to the liquid crystal display device and the driving circuit thereof of the present invention, the arrangement of the cells of the liquid crystal driving output circuit is not in ascending order, and the wiring pattern from the liquid crystal driving output circuit and the electrical connection pad, that is, the liquid crystal driving voltage are arranged. The arrangement order of the cells of the liquid crystal drive output circuit is changed so that the wiring pattern area to the output terminal can be reduced (including the arrangement order of the cells of the shift register). Thereby, it can form on an output circuit using a stacked wiring. Thus, by efficiently performing the wiring pattern between the liquid crystal drive output circuit and the liquid crystal drive voltage output terminal in the source driver chip, the area of the routing wiring area in the source driver chip is reduced, and accordingly, the source driver chip It is possible to reduce the outer dimension of the short side length, and there is an effect that the manufacturing cost can be reduced.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a display panel driving device disposed on the outer edge of a display panel so as to drive a display panel such as a liquid crystal display panel, and a display device such as a liquid crystal display device using the display panel driving device. This is useful for applications that require a reduction in size.

1 is a block diagram illustrating a schematic configuration of an active matrix liquid crystal display device according to a representative embodiment of the present invention. It is a top view which shows the outline of the connection structural example of the electrode pad and liquid crystal drive output circuit in the source driver which concerns on one Embodiment of this invention. It is a top view which shows the more detailed circuit structure of the said liquid-crystal drive output circuit. It is a figure which shows an example of the relationship between the arrangement | positioning order of the cell of the liquid crystal drive output circuit arrange | positioned at the source driver of this invention, and the flow of the start pulse signal transferred in the shift register circuit. It is a figure which shows the other example of the relationship between the arrangement | positioning order of the cell of the liquid crystal drive output circuit arrange | positioned at the source driver of this invention, and the flow of the start pulse signal transferred in the shift register circuit. FIG. 11 is a plan view schematically showing an example of a connection configuration between an electrode pad in a source driver and a liquid crystal drive output circuit in an active matrix liquid crystal display device according to another embodiment of the present invention. It is a top view which shows the more detailed circuit structural example of the liquid crystal drive output circuit in the liquid crystal display device of FIG. It is a figure which shows the liquid crystal drive output circuit in the liquid crystal display device of FIG. 6, and its peripheral part. It is a block diagram which shows the schematic structure of the conventional liquid crystal display device which contains a liquid crystal drive device and a liquid crystal panel at least. It is a figure which shows the schematic structure of the liquid crystal panel in the said conventional liquid crystal display device. It is a wave form diagram which shows an example of the liquid crystal drive waveform in the said conventional liquid crystal display device. It is a wave form diagram which shows another example of the liquid crystal drive waveform in the said conventional liquid crystal display device. It is a block diagram which shows schematic structure of an example of the source driver in the said conventional liquid crystal display device. It is a top view which shows the outline of the connection structural example of the electrode pad and liquid crystal drive output circuit by the source driver in the said conventional liquid crystal display device.

Explanation of symbols

11 Liquid crystal panel (display panel)
12 Source driver (display panel drive)
1002 Liquid crystal drive voltage output terminal (electrode pad)
1003 Liquid crystal drive output circuit (drive voltage output circuit)
1003-1 to 1003-4 Block 1004 Control circuit 1005 Metal wiring pattern (wiring)
1006 Wiring space region 1007 Substrate Y1-Y384 circuit cell Y1-Y384 Output terminal Y1-Y39 / Y344-Y384 circuit cell (first circuit cell group)
Y40 to Y193 and Y194 to Y343 circuit cell (second circuit cell group)

Claims (9)

For a display panel including a plurality of display pixels and a plurality of drive wirings for driving the display pixels, a drive voltage for driving the display pixels is applied to the display pixels via the drive wirings. A display panel driving device which is a source driver or a gate driver for
A substrate having a rectangular or similar shape;
A plurality of electrode pads for outputting the drive voltage, which are arranged on a peripheral portion of the substrate;
A drive voltage output circuit arranged on the inner side of the electrode pad on the substrate for outputting the drive voltage to the display panel;
A plurality of wirings connecting the drive voltage output circuit and the electrode pads ,
The drive voltage output circuit is formed by arranging a plurality of circuit cells corresponding to individual drive wirings of the display panel and each having a shift register in the long side direction of the substrate,
The plurality of circuit cells are:
The connection order of the connection points between the circuit cell and the wiring is arranged in the reverse order of the order of the electrode pads connected to the circuit cell, and the wiring connected to the circuit cell is connected to the circuit cell. A first circuit cell group routed from the point to the electrode pad through the region overlapping with the drive voltage output circuit, straddling the portion on the short side of the substrate in the boundary line between the region and the outside of the region;
The arrangement order of the connection points between the circuit cell and the wiring is arranged in the same order as the arrangement order of the electrode pads connected to the circuit cell, and the wiring connected to the circuit cell is connected to the connection point with the circuit cell. And a second circuit cell group routed to the electrode pad without passing through the region overlapping the drive voltage output circuit,
The plurality of circuit cells are arranged so that the shift order between the shift registers in the first circuit cell group is opposite to the shift order between the shift registers in the second cell group. A display panel driving device. For a display panel including a plurality of display pixels and a plurality of drive wirings for driving the display pixels, a drive voltage for driving the display pixels is applied to the display pixels via the drive wirings. A display panel driving device which is a source driver or a gate driver for
A substrate having a rectangular or similar shape;
A plurality of electrode pads for outputting the drive voltage, which are arranged on a peripheral portion of the substrate;
A drive voltage output circuit arranged on the inner side of the electrode pad on the substrate for outputting the drive voltage to the display panel;
A plurality of wirings connecting the drive voltage output circuit and the electrode pads ,
The drive voltage output circuit is formed by arranging a plurality of circuit cells corresponding to individual drive wirings of the display panel and each having a shift register in the long side direction of the substrate,
The plurality of circuit cells are:
The wiring connected to the circuit cell passes from the connection point with the circuit cell through the region overlapping the drive voltage output circuit, and extends to the electrode pad across the short side of the substrate on the boundary line between the region and the outside of the region A first group of circuit cells being routed;
A second circuit cell group in which wiring connected to the circuit cell is routed from the connection point with the circuit cell to the electrode pad without passing through a region overlapping with the drive voltage output circuit;
The plurality of circuit cells are arranged so that the shift order between the shift registers in the first circuit cell group is opposite to the shift order between the shift registers in the second cell group. A display panel driving device. 3. The display panel driving device according to claim 1, wherein the wiring passing through the region overlapping with the driving voltage output circuit is formed with a wiring pattern of two or more layers. The drive voltage output circuit is divided into a plurality of blocks,
3. The display panel driving device according to claim 1, wherein a part of the wiring is routed from a connection point with a driving voltage output circuit to the electrode pad through a space between blocks. The wiring connecting the circuit cell belonging to the second circuit cell group and the electrode pad is formed of a wiring pattern of two or more layers,
3. A display panel driving device according to claim 1, wherein the wiring for connecting the circuit cells belonging to the first circuit cell group and the electrode pads is formed with a wiring pattern of three or more layers. Each circuit cell above is
A shift register circuit for sequentially shifting the pulse signal;
A sampling memory circuit for storing the display data signal in a time-sharing manner in synchronization with the pulse signal output from the shift register circuit;
A hold memory circuit for outputting the display data signal output from the shift register circuit after holding it for a predetermined period;
A level shifter circuit for converting the level of the display data signal output from the hold memory circuit;
A DA conversion circuit for selecting and outputting an analog voltage corresponding to a display data signal level-converted by a level shifter circuit from a plurality of types of analog voltages;
The display panel driving device according to claim 1, further comprising: an output circuit for outputting an analog voltage output from the DA conversion circuit to the display panel. The display panel driving apparatus according to claim 1, wherein the display panel is a liquid crystal display panel including a liquid crystal as the display pixel. A display panel comprising a display panel including a plurality of display pixels and a plurality of drive wirings for driving the display pixels, and the display panel driving device according to claim 1. The display device according to claim 8, wherein the display panel is a liquid crystal display panel including a liquid crystal as the display pixel.

Images