JP4228276B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device characterized by a configuration for artificially controlling the band structure in a semiconductor and the electrical conduction of a transistor.
[0002]
[Prior art]
In recent years, according to scaling rules, miniaturization of MOS transistors has progressed, and 0.1 μm node transistors have been developed in the research and development stage.
[0003]
Since this generation of transistors has a gate length of 50 nm or less, the threshold voltage V of the transistor_thThe so-called short channel effect such as a decrease in the flow rate and DIBL (Drain-Induced Barrier Lowering) becomes prominent, and in order to suppress this, a device such as pocket implantation (inclined ion implantation) or increasing the impurity concentration of the Si-based semiconductor substrate is used. Has been done.
[0004]
However, when the gate length is further reduced to increase the speed of the transistor, there is a concern that even if the gate length is reduced due to several factors, high performance can no longer be obtained.
[0005]
One of the causes is that the longitudinal electric field in the channel becomes finer, that is, as the oxide film becomes thinner, the wave function indicating the existence probability of carriers is strongly pressed toward the interface with the gate oxide film. , SiO₂This is because the influence of roughness scattering at the / Si interface becomes stronger, and the effective carrier mobility in the channel is lowered.
[0006]
In addition, as a more fundamental problem, V_thIt becomes technically difficult to advance miniaturization while suppressing variations in transistor characteristics.
Even if it can be technically cleared, there is a direction to draw a scenario in which the bankruptcy occurs due to economic factors such as an increase in the investment cost of the production line necessary to realize mass production.
In any case, it must be said that there has been a limit to the improvement in characteristics by Dennard's simple scaling, which has been pursued as a gold sphere for many years.
[0007]
Under such circumstances, an attempt to improve the characteristics by changing the material or physical properties of the channel of the transistor to improve the carrier mobility, rather than simply shrinking the transistor dimensions, has begun.
[0008]
In particular, when a MOS transistor is formed by a normal process technique by forming an oxide film on a strained Si surface to which a biaxial in-plane tensile stress is applied, it is experimentally shown that the electron mobility is improved by about 70%. It has been confirmed.
[0009]
This improvement in mobility results in the symmetry of the crystal breaking due to strain, and the degeneracy of the energy valley at the Δ point that has undergone 6-fold degeneration splits into a low-energy double-degenerate level and a high-energy 4-fold degeneration, resulting in intersubvalley scattering. And the effect of increasing the occupancy of the double degenerate level and reducing the average effective mass of the conduction band electrons (for example, see Non-Patent Document 1).
[0010]
Specifically, a thin Si channel having a critical thickness of 10 to 20 nm or less on a SiGe (Ge composition 10 to 20%) buffer layer grown to exceed the critical thickness for the purpose of relaxing strain on the Si substrate. A MOSFET transistor is manufactured using a wafer on which layers are epitaxially grown.
[0011]
For n-type MOS transistors, this method has already been used, and a number of research institutions (Stanford University, Toshiba, MIT, IBM) have demonstrated significant improvements in mobility, and p-type MOS transistors are also about 2.7 times higher. Although it does not reach the theoretical prediction, using the same wafer, mobility improvement of several tens of percent has been confirmed.
[0012]
  In addition, an SOI (Silicon on Insulator) substrate is used, and an element formation region is selectively oxidized.soIt has also been proposed to improve the mobility of carriers by applying compressive stress to the element formation region by surrounding (see, for example, Patent Document 1).
[0013]
[Non-Patent Document 1]
Semicond. Sci. Technol. , Vol. 12, pp. 1515-1549, 1997
[Patent Document 1]
JP-A-11-54756
[0014]
[Problems to be solved by the invention]
As described above, the concept of equivalent scaling has finally started to be used outside the conventional simple scaling frame. In particular, in terms of strained Si-MOSFETs, mobility improvement is no longer an experimental fact. It seems that the issue and importance have already shifted to how well this characteristic can be applied to practical technology.
[0015]
Of course, the pursuit of the mechanism seems to be important academically, but it does not necessarily link to technical problems.
Therefore, when analyzing the problems of the strained Si technology described above, the new material SiGe itself is not directly used for the channel, but is only indirectly applied to give strain to Si.
[0016]
In other words, the essence of the technology is to add strain to Si, which is normally 6-fold degenerate on the conduction band side and double-degenerate on the valence band side. By releasing these degeneracy and changing the scattering frequency, There is no need to use SiGe which does not necessarily constitute the element formation region if the strain is applied while being artificially controlled.
[0017]
In consideration of cost and process line contamination, a means for improving the mobility of the Si substrate without using a new material such as SiGe can be achieved except when SiGe is used as an element formation region. If so, it would be extremely desirable.
[0018]
In addition, in the case of an SOI substrate, although a new material is not used, it is difficult to improve the crystallinity of the Si layer formed on the insulating film. It is difficult to apply stress.
[0019]
Therefore, an object of the present invention is to apply a uniaxial compressive stress to an element formation region using a conventional configuration as it is.
[0020]
[Means for Solving the Problems]
  FIG. 1 is a diagram illustrating the basic configuration of the present invention, and FIG. 2 is an explanatory diagram of changes in the band structure due to strain. Means for solving the problems in the present invention with reference to FIGS. Will be explained.
  See FIGS. 1 and 2
  In order to achieve the above object, the present invention provides an element formation region for forming at least a transistor provided on a Si-based semiconductor substrate in a semiconductor device.And a groove having a side defined on the outer periphery of the element formation region and a gate electrode formed in the element formation region via a gate insulating film, and having a side perpendicular to the gate electrode. Is completely filled with a thermal oxide film, and a groove parallel to the gate electrode is filled with a buried insulating film made of a thermal oxide film and a deposited film,Compressive stress in one axial direction in the planeTheAppliedDoIt is characterized by that.
[0021]
In the conventional MOSFET, as shown in FIG. 1A, the carrier conduction direction is the <110> direction using the Si substrate having the (001) plane as the main surface. As shown in FIG. 3, when a uniaxial compressive stress is applied from both sides along the <100> direction, which is the x direction, to the Si substrate having the same (001) plane as the main surface, the Si substrate Try to stretch in the direction.
[0022]
Then, as shown in the left diagrams of FIGS. 2A and 2B, in the case of normal Si, the band structure degenerates six times at the Δ point is as shown in the right diagrams of FIGS. 2A and 2B. When compressive stress is applied, the degeneracy is resolved, the energy of the two valleys on the <100> axis (double degeneration) decreases, and conversely, the energy of the four valleys on the <010> axis and the <001> axis increases. To do.
As a result, the occupancy probability of electrons increases in the double degenerated subvalley, and the scattering frequency to four valleys with higher energy decreases, so that the electron mobility is improved.
[0023]
In addition, as shown in FIG. 1B, when a channel is formed in the <010> direction orthogonal to the direction of application of the uniaxial compressive stress, the spheroid shape on the isoenergetic surface means <010 The effective mass in the> direction is mainly visible, so this effect also contributes to improved mobility.
Note that the energy levels in the y direction and the z direction do not necessarily match because energy changes occur in accordance with the amount of lattice deformation in each direction, but there is no doubt that they are higher than the energy in the x direction.
[0024]
On the other hand, as shown in FIG. 2C, in the valence band, light holes (1h) and heavy holes (hh) at the Γ point (intersection of the vertical axis and the horizontal axis) are also affected by strain. Since degeneracy is solved and scattering due to interband transition is reduced, mobility is improved.
In addition, SO in a figure is spin orbit split-off.
[0025]
In addition, it is generally known that the drain current density of the transistor increases by taking the channel direction in the <010> direction for holes, and this effect can also be expected.
[0026]
Therefore, by embedding a pair of opposed grooves provided on the outer periphery surrounding the element formation region by thermal oxidation, the above-described uniaxial stress can be applied to the element without using a special structure such as an SOI structure or a SiGe stress relaxation layer. This can be applied to the region, and the above-described improvement in mobility can be realized.
[0027]
That is, when thermal oxidation is performed, oxidation proceeds from both side walls of the groove, and when the groove is completely filled with the thermal oxide film, the element formation region is pushed inward by the increased thermal oxide film, A compressive stress is applied.
On the other hand, in the other pair of sides, the groove is not completely filled with the thermal oxide film, so that no compressive stress is applied to this portion, so that it becomes a uniaxial compressive stress.
[0028]
The Si-based semiconductor substrate (body) in the present invention means both a Si-based semiconductor substrate and a Si-based semiconductor layer grown on a growth substrate such as a semiconductor substrate or an insulating substrate. The Si-based semiconductor means both Si and SiGe. However, as the Si-based semiconductor substrate, a Si substrate having a (001) plane as a main surface is typical, and as a transistor, Insulated gate field effect transistors, or MISFETs, are typical.
[0030]
As a transistor, a lateral bipolar transistor is also targeted. However, in the case of an insulated gate field effect transistor, compressive stress is applied to at least one of a source region, a drain region, and a channel region. For example, it may be applied to all of the source region, the drain region, and the channel region, only the source region and the drain region, or only the channel region.
[0031]
Further, by applying a partial change in the width of the groove provided in the Si-based semiconductor substrate, the portion to which the compressive stress is applied and the amount of strain may be arbitrarily controlled.
For example, the width of the groove formed in the Si-based semiconductor substrate along the carrier conduction direction is made narrower than other regions in the vicinity of the channel region, and the in-plane compressive stress is applied in the direction perpendicular to the carrier conduction direction. Alternatively, the width of the groove provided in the Si-based semiconductor substrate along the carrier conduction direction is made wider than the other regions in the vicinity of the channel region, and the in-plane compressive stress is increased in the carrier conduction direction. And may be applied in parallel.
[0032]
When a plurality of element formation regions are provided, the widths of grooves provided on the outer periphery of at least a pair of opposing sides of each element formation region may be different from each other, thereby forming each element formation region. The characteristics of the transistors to be made can be made different from each other.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Here, the manufacturing process of the n-channel MOSFET according to the first embodiment of the present invention will be described with reference to FIGS.
In each of the drawings, a figure without “′” is a schematic plan view, and a figure with “′” is a schematic cross-sectional view along an alternate long and short dash line connecting AA ′ in the plan view.
Refer to FIGS. 3A and 3A.
First, after forming the p-type well region 12 on the surface of the p-type silicon substrate 11 having the (001) plane as the main surface, etching is performed using the SiN film pattern 13 as a mask, so that the horizontal direction in FIG. The element forming region 14 is defined by a groove 15 having a width of a groove extending in the 010> direction and a width of b (>> a) extending in the vertical direction, that is, <100>.
[0034]
See FIGS. 3B and 3B '
Next, by performing thermal oxidation using the SiN film pattern 13 as a selective oxidation mask as it is, the groove 15 having a width a extending in the horizontal direction is completely filled with the thermal oxide film 16.
[0035]
At this time, thermal oxidation proceeds from both side walls of the groove 15, but Si is SiO.₂In this case, the volume expansion more than twice occurs, and SiO₂When they come into contact with each other, a force that pushes both sides of the groove is generated and tries to deform.
However, since the p-type well region 12 opposed to the element forming region 14 with the groove 15 interposed therebetween is a larger region than the element forming region 14, a compressive stress is generated in the <100> direction on the element forming region 14 side.
[0036]
On the other hand, by controlling the width b and the thermal oxidation time so that the thermal oxide film 16 does not collide with the groove 15 having the width b, no compressive stress is generated in the <010> direction. The compressive stress is a uniaxial compressive stress in the <100> direction.
[0037]
See FIG. 4 (c) and (c ′)
Next, SiO₂After the film is deposited, etching back is applied to fill the remaining portion of the groove 15 extending in the <100> direction with the buried insulating film 17 and planarize it, and then selectively remove the SiN film pattern 13 in the peripheral portion. Then, by performing selective oxidation using the SiN film pattern 13 remaining on the element forming region 14 as a mask, an element isolation oxide film 18 is formed on the outer peripheral portion of the groove 15.
[0038]
Refer to FIGS. 4D and 4D
Next, after the SiN film pattern 13 is removed, a gate insulating film 19 and a gate electrode 22 are provided. Then, As ions are implanted in a self-aligned manner using the gate electrode 22 as a mask and heat treatment is performed, whereby the n-type source region 20 and n By forming the type drain region 21, the basic configuration of the n-channel type MOSFET can be obtained.
[0039]
In the first embodiment, uniaxial compression in the <100> direction is performed by setting the width of the groove 15 defining the element forming region 14 to be different between the <010> direction and the <100> direction. Since stress is generated and the mobility of electrons in the <010> direction is improved, the operation speed of the n-channel MOSFET having the <010> direction as the current direction can be improved.
[0040]
Next, the manufacturing process of the n-channel MOSFET according to the second embodiment of the present invention will be described with reference to FIG. 5. In each drawing, the figures without “′” are schematic plan views. The drawing with “′” is a schematic cross-sectional view along the alternate long and short dash line connecting AA ′ in the plan view.
See FIGS. 5 (a) and (a ').
First, after forming the p-type well region 12 on the surface of the p-type silicon substrate 11 having the (001) plane as the main surface, etching is performed using the SiN film pattern 13 as a mask, so that the horizontal direction in FIG. The groove extending in the 010> direction has a width in the vicinity of the central portion serving as the channel region and b (>> a) in the other portion, and the groove extending in the vertical direction, that is, <100>. The element formation region 14 is defined by the groove 15 having a width of b.
[0041]
Next, the central portion of the groove extending in the <010> direction is completely filled with the thermal oxide film 16 by performing thermal oxidation using the SiN film pattern 13 as it is as a selective oxidation mask.
In this case, the uniaxial compressive stress in the <100> direction is generated only in the central portion of the groove extending in the <010> direction.
[0042]
Refer to FIGS. 5B and 5B
Next, SiO₂After the film is deposited, etching back is performed to fill the remaining portion of the trench 15 with the buried insulating film 17 and planarize it. Then, the SiN film pattern 13 in the peripheral portion is selectively removed, and the element formation region 14 is formed. The element isolation oxide film 18 is formed on the outer peripheral portion of the trench 15 by performing selective oxidation using the remaining SiN film pattern 13 as a mask.
[0043]
Next, after the SiN film pattern 13 is removed, a gate insulating film 19 and a gate electrode 22 are provided. Then, As ions are implanted in a self-aligned manner using the gate electrode 22 as a mask and heat treatment is performed, whereby the n-type source region 20 and n By forming the type drain region 21, the basic configuration of the n-channel type MOSFET can be obtained.
[0044]
Also in the second embodiment of the present invention, the uniaxial compressive stress in the <100> direction is applied to the channel region to improve the mobility of electrons in the <010> direction. The operating speed of the MOSFET can be improved.
[0045]
In this case, since the band gap is lowered in the vicinity of the channel region to which the compressive stress is applied, the diffusion potential of the channel region immediately below the n-type source region 20 and the gate electrode 22 is lowered and generated by hot electrons. It can also be expected to suppress floating body effect (operation threshold voltage fluctuation) due to charging.
[0052]
  Next, figure6Referring to FIG.3The CMOS of the embodiment will be described.
  Figure6See (a) and (b)
  Figure6(A) is the first of the present invention.32 is a schematic plan view of the CMOS of the embodiment of FIG.6(B) is a figure6FIG. 6 is a schematic cross-sectional view taken along the alternate long and short dash line connecting BB ′ in FIG. 4A. In this case, the n-channel MOSFET having the structure shown in FIG. The p-channel MOSFETs having the same structure are provided adjacent to each other to constitute a CMOS.
[0053]
That is, a p-type well region 12 and an n-type well region 31 are selectively provided on a p-type silicon substrate 11, and an n-channel MOSFET having the structure shown in FIG. A p-channel MOSFET is provided in the n-type well region 31.
[0054]
  This first3In this embodiment, since a uniaxial compressive stress can be applied to both the p-channel MOSFET and the n-channel MOSFET, the operation speed of the CMOS can be improved.
[0055]
  Next, figure7Referring to FIG.4The CMOS of this embodiment will be described. Since the basic manufacturing process is the same as that of each of the above embodiments, the groove pattern and the final configuration will be described as a plan view.
  Figure7See (a) and (b)
  The first aspect of the present invention4In the embodiment, the width extending in the <010> direction of the groove 15 that partitions the element forming region 14 that forms the n-channel MOSFET is a, and the element forming region 33 that forms the p-channel MOSFET is partitioned. The width of the groove 34 extending in the <010> direction is c (<a), and the region of the width a extending in the <010> direction of the groove 15 defining the element forming region 14 is completely filled. Thermal oxidation is performed.
[0056]
In this case, in the region c of the narrow width of the groove 34, the pressure due to the volume expansion by the thermal oxide film 35 becomes larger than the region of the narrow width a of the groove 15, so that the uniaxial compressive stress on the p-channel MOSFET is more Therefore, the balance between the operation speeds of the n-channel MOSFET and the p-channel MOSFET can be further improved.
[0057]
  Next, figure8Referring to FIG.5The manufacturing process of the npn lateral bipolar transistor of this embodiment will be described. In each figure, the figures without “′” are schematic plan views, and the figures with “′” are AA ′ in the plan views. It is a schematic sectional drawing in alignment with the dashed-dotted line which connects.
  Figure8See (a) and (a ')
  First, after forming the p-type well region 52 on the surface of the p-type silicon substrate 51 having the (001) plane as the main surface, etching is performed using the SiN film pattern 54 as a mask, so that the horizontal direction in the drawing, that is, < The width of the groove extending in the 010> direction is b (>> a) in the vicinity of the central portion that becomes the channel region, and the width in the other region is a, extending in the vertical direction, that is, <100>. The element forming region 54 is defined by the groove 55 having a groove width b.
[0058]
  Next, by performing thermal oxidation using the SiN film pattern 53 as it is as a selective oxidation mask, the portion with the width a excluding the central portion of the groove 55 extending in the <010> direction is completely buried with the thermal oxide film 56. .
  This placeIfAs a result of the occurrence of uniaxial compressive stress in the <100> direction in the region other than the central portion of the groove extending in the <010> direction, the regions on both sides of the element formation region 54 are expanded in the <010> direction. Since it tries to deform, a uniaxial compressive stress in the <010> direction is applied in the central region.
[0059]
  Figure8See (b) and (b ')
  Next, after depositing a SiO2 film on the entire surface, etching back is performed to bury the remaining portion of the groove 55 extending in the <100> direction and the remaining portion of the groove 55 in the center portion in the <010> direction with the buried insulating film 57. Then, the SiN film pattern 53 is removed.
[0060]
Next, a new SiN film pattern (not shown) is provided so as to cover the element formation region 54 and the base lead region 55, and selective isolation is performed using this SiN film pattern as a mask, so that element isolation is performed on the outer periphery of the groove 55. An oxide film 58 is formed.
[0061]
Next, after removing the SiN film pattern, As is selectively implanted and heat-treated on both sides of the element formation region 54 to form an n-type emitter region 59 and an n-type collector region 60, and an unimplanted region is formed as a p-type base. By using the region, the basic configuration of the npn lateral bipolar transistor can be obtained.
[0062]
  This first5Also in this embodiment, by applying a uniaxial compressive stress, the mobility of electrons and holes can be improved, so that the operation speed of the lateral bipolar transistor can be improved.
[0063]
Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made.
For example, in each of the above-described embodiments, the element isolation oxide film is formed by selective oxidation after the formation of the thermal oxide film that generates the compressive stress. A thermal oxide film that generates compressive stress may be formed.
[0064]
Also, as can be easily imagined, if the groove width is designed in the channel direction, the band state can be changed at an arbitrary position, and lateral band gap engineering can be performed.
[0065]
For example, if stress is applied only in the vicinity of the junction between the source region and the channel region, the diffusion potential is lowered, so that injection of electrons and holes from the source region to the channel region is promoted, and a large amount of current can be expected.
Furthermore, the effect of increasing the current is expected by making the speed overshoot phenomenon and ballistic conduction remarkable.
[0067]
  Also, the above3And the second4In the embodiment, the CMOS is described, but this is merely an example, and the width of the groove defining the element formation region can be set to an arbitrary pattern according to the intended effect of the uniaxial stress. To design.
[0068]
  In addition, the firstAnd secondIn this embodiment, one type of MOSFET is described, but when forming the same type of MOSFET on one substrate, the uniaxial compressive stress applied to some MOSFETs is different The groove widths may be different from each other so that the uniaxial compressive stress applied to the MOSFET is different, whereby MOSFETs having different characteristics can be formed simultaneously in the same process. .
[0069]
In each of the above embodiments, the silicon substrate having the (001) plane as the main surface is described as an example in the typical example. However, the present invention is not limited to the silicon substrate having the (001) plane as the main surface. However, the present invention is also applicable to a silicon substrate whose main surface is another crystal plane such as the (111) plane.
[0070]
In each of the above embodiments, the description has been given using the silicon substrate. However, the present invention is not limited to the silicon substrate, and the Si epitaxial layer provided on the silicon substrate or the Si layer provided on the SOI substrate is also described. Applicable.
[0071]
In addition, the element formation region is not limited to Si, and SiGe may be used. Thereby, the operation speed of the p-channel MOSFET can be improved, so that the speed of the CMOS can be improved. it can.
In this case, since the SiGe layer may be thick enough to be used as an active region, a thick SiGe layer exceeding the critical film thickness that does not directly contribute to device operation as described in Non-Patent Document 1 described above is required. Disappear.
[0072]
  Here, the detailed features of the present invention will be described again with reference to FIG.
  Again see Figure 1
  (Additional remark 1) The element formation area which forms the transistor provided in the Si type semiconductor substrate, the groove | channel partitioned off by the edge which mutually opposes on the outer periphery of the said element formation area, and a gate insulating film in the said element formation area And a groove on a side perpendicular to the gate electrode is completely filled with a thermal oxide film, and a groove parallel to the gate electrode is buried with a thermal oxide film and a deposited film. The semiconductor device is characterized in that a compressive stress is applied in one axial direction in the plane by embedding in (1).
  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the Si-based semiconductor substrate is a Si substrate having a (001) plane as a main surface, and the transistor is an insulated gate field effect transistor.
  (Additional remark 3) The semiconductor device of Additional remark 1 or 2 characterized by the conduction direction of a carrier being a direction orthogonal to the direction which receives the distortion by the said compressive stress.
  (Appendix4Note that the transistor is an insulated gate field effect transistor, and the compressive stress is applied to at least one of a source region, a drain region, and a channel region.3The semiconductor device according to any one of the above.
  (Appendix5The additional portion 1 to the compressive stress is applied and the amount of strain is controlled by partially changing the width of the groove provided in the Si-based semiconductor substrate.3The semiconductor device according to any one of the above.
  (Appendix6) The width of the groove formed in the Si-based semiconductor substrate along the carrier conduction direction is made narrower than other regions in the vicinity of the channel region, and the in-plane compressive stress is applied in the direction perpendicular to the carrier conduction direction. Additional notes characterized by5The semiconductor device described.
  (Appendix72) A plurality of the element formation regions are provided, and the widths of the grooves provided on the outer circumferences of at least a pair of opposing sides of the element formation regions are different from each other.6The semiconductor device according to any one of the above.
  (Appendix8) A groove is provided in the Si-based semiconductor substrate so as to partition at least an element formation region for forming a transistor, the width of the groove is at least partly narrower than that of the other part, and at least in the region where the width is narrowed. A method of manufacturing a semiconductor device, comprising performing thermal oxidation to such an extent that compressive stress is applied in a uniaxial direction, and filling a groove in the at least narrow region with a thermal oxide film.
[0073]
【The invention's effect】
According to the present invention, the uniaxial compressive stress whose direction can be freely set can be applied with a simple configuration. Therefore, the operating speed is determined by determining the current direction in accordance with the application direction of the uniaxial compressive stress. Can be improved with good controllability, which greatly contributes to improving the performance of silicon-based semiconductor devices.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a change in band structure due to strain.
FIG. 3 is an explanatory diagram of a manufacturing process to the middle of the n-channel MOSFET according to the first embodiment of the invention.
FIG. 4 is an explanatory diagram of the manufacturing process of the n-channel MOSFET according to the first embodiment of the present invention after FIG. 3;
FIG. 5 is an explanatory diagram of a manufacturing process of the n-channel MOSFET according to the second embodiment of the invention.
FIG. 6 shows a third embodiment of the present invention.It is a configuration explanatory diagram of a CMOS.
FIG. 7 is a configuration explanatory diagram of a CMOS according to a fourth embodiment of the present invention.
FIG. 8 shows the first of the present invention.5It is explanatory drawing of the manufacturing process of the npn lateral bipolar transistor of embodiment.
[Explanation of symbols]
  11 p-type silicon substrate
  12 p-type well region
  13 SiN film pattern
  14 Element formation region
  15 groove
  16 Thermal oxide film
  17 buried insulating film
  18 Device isolation oxide film
  19 Gate insulation film
  20 n-type source region
  21 n-type drain region
  22 Gate electrode
  31 n-type wellregion
  33  Element formation region
  34 groove
  35 Thermal oxide film
  36 ImplantationRim
  38  Gate insulation film
  39 p-type source region
  40 p-type drain region
  41 Gate electrode
  51 p-type silicon substrate
  52 p-type well region
  53 SiN film pattern
  54 Element formation region
  55 groove
  56 Thermal oxide film
  57 buried insulating film
  58 Device isolation oxide film
  59 n-type emitter region
  60 n-type collector region
  61 p-type base region
  62 Base drawer area

Claims (4)

  Formed on the Si-based semiconductor substrate at least an element forming region for forming a transistor, a groove partitioned by edges facing each other on the outer periphery of the element forming region, and a gate insulating film formed in the element forming region A groove on a side perpendicular to the gate electrode is completely filled with a thermal oxide film, and a groove parallel to the gate electrode is buried with a buried insulating film made of a thermal oxide film and a deposited film. A semiconductor device characterized by applying a compressive stress in one axial direction in the plane.   2. The semiconductor device according to claim 1, wherein a carrier conduction direction is a direction orthogonal to a direction of receiving a strain due to the compressive stress. The transistor is the insulated gate field effect transistor, the compressive stress, the source region, the drain region, or, according to claim 1 or 2, characterized in that it is applied to at least one region of the channel region Semiconductor device. By varying the width of the groove formed in the Si-based semiconductor substrate partially according to any one of claims 1 to 3, characterized in that controlling the application portion and a strain amount of the compressive stress Semiconductor device.

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