JP4228275B2 - Information processing device - Google Patents

Description

[0001]
The present invention relates to an information processing apparatus, particularly relates to an information processing apparatus for improving the processing speed performed by the CPU.
[0002]
[Prior art]
In recent years, personal computers have become widespread, and the processing capability (processing speed) of a CPU (Central Processing Unit) which is the brain of the personal computer is being improved. In order to improve the processing capability of the CPU, a coprocessor is provided in addition to the CPU. (For example, see Patent Documents 1 to 5)
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-73314 [Patent Document 2]
JP 9-325759 A [Patent Document 3]
JP-A-9-69047 [Patent Document 4]
Patent No. 2849189 [Patent Document 5]
Japanese Patent No. 2990896 [0004]
[Problems to be solved by the invention]
When the CPU executes an operation, it is necessary to access necessary data and instructions by accessing the storage device. Examples of the storage device include a cache provided in the CPU, a memory and a register provided outside the CPU, and the like. When the CPU accesses the cache in the CPU, the data transfer speed between the CPU and the cache is faster than the data transfer speed between the CPU and the memory. When the CPU accesses a register or memory outside the CPU, the access speed (data transfer speed) is via the bus connecting the CPU and the memory (register). take time.
[0005]
This is because the CPU sends the data request signal and the address where the target data is stored to the memory or register, and sends the next request signal until the data is transferred from the register or memory as a response. This is because it cannot be done.
[0006]
In addition to the CPU, there is a device that uses the bus to transfer data, etc., so that the bus can be used due to the bus becoming busy, etc. Wait time may be required. For this reason, when the amount of computation is very large, the processing speed becomes slow, and when real-time processing is required, it becomes impossible to answer the request, and the current CPU performance is insufficient. there were.
[0007]
As one of countermeasures against this problem, for example, there is DMA (Direct Memory Access). This DMA performs data transfer between memories instead of the CPU, and enables high-speed data transfer without going through the CPU. However, in order to transfer the data transfer to the DMA, the CPU needs to set an address, a transfer size, and the like in the DMA controller, and the above-described problem may occur during the process for the setting. There was sex.
[0008]
The present invention has been made in view of such a situation, and an object thereof is to improve the processing speed of a CPU.
[0009]
[Means for Solving the Problems]
The information processing apparatus of the present invention connects a first storage device accessed only by a CPU, a second storage device accessed by a device different from the CPU and the CPU, and the CPU and the first storage device. And a second bus that connects the CPU and the second storage device, and is used between the CPU and the first storage device via the first bus. The instruction set for the first bus has a fixed length, does not have an Acknowledge as one of response signals, does not have an offset value, and uses an immediate value or a pointer to the first storage device. When accessing the first storage device using the pointer, a predetermined value out of values stored in the pointer of the instruction set for the first bus is used. Masked upper bits are to increase or decrease only the lower bits other than the predetermined upper bits.
[0010]
The instruction set for the first bus may have the same format as the instruction set for the second bus used between the CPU and the second storage device via the second bus. it can.
[0011]
A third bus that connects the first storage device and the second bus may be further provided.
[0012]
The first bus may be connected to a coprocessor port of the CPU.
[0016]
In the information processing apparatus of the present invention, the CPU and the memory dedicated to the CPU are connected by a dedicated bus, and the instruction set in the bus has a fixed latency and does not have an Acknowledge. In executing the processing, it is possible to issue instructions continuously, thereby improving the processing capability of the CPU. In addition, the instruction set has no offset value, and the memory is accessed using an immediate value or a pointer. When accessing using a pointer, a predetermined value out of the values stored in the pointer of the instruction set is used. The upper bits are masked so that only lower bits other than the predetermined upper bits are increased or decreased .
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of an information processing apparatus to which the present invention is applied. The information processing apparatus 10 illustrated in FIG. 1 is incorporated in, for example, a personal computer. The CPU 11 and the local memory 13 are connected by a local bus interface 12 and a local bus 14 so that data can be exchanged. The CPU 11 and the local bus interface 12 are also connected to the register 16 and the memory 17 by a standard memory bus 15.
[0018]
The local bus interface 12 is connected to the coprocessor port 21 of the CPU 21.
[0019]
Here, the coprocessor port 21 will be described. The coprocessor port 21 is originally provided to connect to the coprocessor. The coprocessor is a processor that complements the CPU 11 and enhances the performance. A typical example is a coprocessor that performs floating-point arithmetic.
[0020]
In this embodiment, a local bus interface 12 that is used independently by the CPU 11 is connected to the coprocessor port 21 provided in the CPU 11 for connecting the coprocessor. The CPU 11 is configured to exchange data with the local memory 13 via the local bus interface 12 and the local bus 14.
[0021]
The local memory 13 is used by the CPU 11 alone. Since the local memory 13 is used by the CPU 11 alone, the local bus 14 is also a bus used by the CPU 11 alone. A local bus interface 12 is provided to control data exchange with the local memory 13 that the CPU 11 uses independently.
[0022]
Although the CPU 11 is used for the local memory 13, the registers 16 and the memory 17 are also used as necessary for devices other than the CPU 11. Data required by devices other than the CPU 11 is transmitted / received to / from the standard memory bus 15, but only data required by the CPU 11 is transmitted / received to / from the local bus 14. In the local bus 14, for example, data is exchanged with 32 bits.
[0023]
The operation when data is exchanged between the CPU 11 and the local memory 13 will be described with reference to the flowchart of FIG. In step S11, the CPU 11 issues a command. The issued instruction is received by the local bus interface 12. In step S12, the local bus interface 12 analyzes the received instruction and stores data to be processed or data at an address to be stored, data to be processed, a read signal (read signal) or a write Convert to signal (Write signal).
[0024]
The converted data and signals are transferred from the local bus interface 12 to the local memory 13 in step S13. In step S14, the local memory 13 generates a response signal as a process corresponding to the received data. The response signal is transmitted (output) to the local bus interface 12.
[0025]
In step S15, the local bus interface 12 converts the response signal from the local memory 13 into data that can be processed by the CPU 11, and outputs the data. In step S16, the CPU 11 receives data from the local bus interface 12, and starts processing based on the received data.
[0026]
In this manner, data exchange (issue of an instruction and processing corresponding to the instruction) is performed between the CPU 11 and the local memory 13. When data is exchanged between the CPU 11 and the local memory 13, that is, when data is exchanged via the local bus 14, for example, between the CPU 11 and the memory 17 via the standard memory bus 15. Compare with the case where data is exchanged.
[0027]
The difference between the exchange of data on the local bus 14 and the exchange of data on the standard memory bus 15 is that the exchange of data via the standard memory bus 15 is performed when the CPU 11 issues a request signal (command), and the signal is sent to the register 16 or the memory. After reaching the storage device 17 or the like, the CPU 11 performs an operation of waiting for reception of data output from the storage device as a response signal. Therefore, the CPU 11 cannot perform other operations until the response signal is received after issuing the request signal.
[0028]
On the other hand, the data transmission / reception protocol (described later) in the local bus 14 has a fixed latency with no Acknowledge as one of the response signals, so the CPU 11 needs to wait for the response signal after issuing the command. There is no. Therefore, it is possible to perform other operations after issuing the request signal. For example, request signals can be issued continuously. As described above, in the data exchange on the local bus 14, the CPU 11 can perform another operation immediately after issuing a signal, and can perform an efficient operation.
[0029]
In step S11, the instruction issued by the CPU 11 to the local memory 13 via the local bus interface 12 and the local bus 14 is to extend the instruction set normally provided in the CPU 11 and use the local memory 13 ( This is a coprocessor instruction format prepared uniquely (to use the local bus 14).
[0030]
By using a coprocessor instruction format prepared independently, a standard instruction is used when accessing a storage device such as the register 16 or the memory 17 that is accessed by devices other than the CPU 11, and the local memory 13 dedicated for the CPU 11 is used. When accessing, it is possible to make a distinction according to the bus to be used, such as using an instruction of a coprocessor instruction format prepared independently. However, since the instruction format is the same as that of a normal instruction, a special operation such as setting to the DMA controller is not necessary.
[0031]
An extension command for transferring data using the local bus 14 will be described. FIG. 3 shows the data structure of LDL (Load-Data-Local) and SDL (Store-Data-Local) instructions, which are extended instructions for exchanging data on the local bus 14. LDL is a read command (read command) from the local memory 13 to the CPU 11, and SDL is a write command (write command) from the CPU 11 to the local memory 13.
[0032]
The instruction is, for example, 32 bits long and has the same configuration as other instructions (instructions output to the standard memory bus 15) provided in the CPU 11. 31 to 26 bits are an opcode, and 20 to 16 bits are a target register, and this part is configured in the same manner as other instructions provided in the CPU 11.
[0033]
The extension instruction for the local bus 14 is configured not to have an offset value. By not having an offset value, it is possible to prevent address calculation. The extension instruction for the local bus 14 is configured to access the local memory 13 using an immediate value (Immediate) or a pointer (Pointer) instead of having an offset value.
[0034]
As shown in FIG. 4, the Lmode data of 25 to 21 bits indicates whether to use an immediate value or a pointer. At the same time, when an immediate value is selected (when Lmode is $ 0 to $ 7), whether or not the immediate value is assigned to the pointer, or when a pointer is selected (when Lmode is $ 8 to $ 13) The user can select whether to increase or decrease the value.
[0035]
For example, with an assembler
LDL $ 10,256 ($ 0) is
CPU.Reg [10] = LocalMem [256]; Pointer [0] = 256;
[0036]
If Pointer [2] is assigned to address 0x4002,
SDL $ 12,0x4002 ($ 12) is
LocalMem [Pointer [2]] = CPU.Reg [12]; Pointer [2]-;
[0037]
In addition, a mask corresponding to one-to-one is prepared for each pointer. An example is shown in FIG. By preparing such a mask, when sending an address using a pointer, it is possible to leave the desired lower bits and increase or decrease the addresses without changing the higher bits.
[0038]
Next, the protocol of the local bus 14 will be described with reference to the timing charts of FIGS. 6 to 9, the first line (HCLK) indicates the waveform of the operation clock signal of the CPU 11, the second line (LDL or SDL) indicates the pipeline stage, and the third line (enable) indicates A read (read) or write (write) enable signal is shown, and a fourth line (address) indicates an address to be read or written (a timing at which the address passes on the local bus 14). (H: read, L: write) indicates a signal instructing reading or writing, and the sixth line (read data [31: 0]) indicates data to be read or written (the data is a local bus). 14).
[0039]
6 to 9, IF indicates Instruction Fetch, RF indicates Register Fetch, EX indicates Execution, DF indicates Data Fetch, and WB indicates Write Back. Further, RA in the fourth line in FIG. 7 indicates Read Address, and RD in the sixth line indicates Read Data. Similarly, WA in the fourth line in FIG. 8 indicates Write Address, and WD in the sixth line indicates Write Data.
[0040]
FIG. 6 shows a case where a read instruction is issued from the CPU 11 to the local memory 13, and the pipeline stage of the LDL instruction which is the instruction is shown in the second line. For the standard memory bus 15 (ordinary bus), after reading the contents of the register included in the instruction and performing processing such as adding an offset, a request is issued in the fourth stage DF.
[0041]
On the other hand, since only the immediate value of the address is included in the instruction to the local bus 14, a request (address of data to be read, etc.) can be issued by the second stage RF. Therefore, even if the LDL instruction is issued after the LDL instruction, no interlock occurs, and continuous data transfer without delay is possible. FIG. 7 shows a state when such an LDL instruction is issued continuously.
[0042]
FIG. 8 shows a case where a write instruction is issued from the CPU 11 to the local memory 13, and the pipeline stage of the SDL instruction as the instruction is shown on the second line. Unlike SDL, SDL issues a request at WB, which is the fifth stage, and writing is completed at that stage. The reason why the request is not issued at an earlier stage is that an interrupt may occur in the fourth stage DF. In such a case, similarly to LDL, even if SDL instructions are issued continuously, data can be transferred without causing an interlock. FIG. 9 shows a state when such SDL instructions are issued continuously.
[0043]
By using such a local bus 14, the CPU 11 can operate with high efficiency. However, data or the like passing through the local bus 14 cannot be detected by a normal debugger. This is because a general debugger accesses a storage device such as the memory 17 through the standard memory bus 15 and the debug signal does not use the coprocessor port 21.
[0044]
In order to solve such a problem, a bypass connecting the standard memory bus 15 and the local bus interface 12 is prepared. Via this debugging bypass, data transfer with the storage device such as the local memory 12 or a local register (not shown) can be performed, and as a result, debugging is also possible.
[0045]
Conventionally, data transfer between the CPU 11 and a storage device such as a memory cannot issue the next signal (it cannot move to the next operation) without waiting for a response signal to the request signal. Several cycles of waiting time were required to access and transfer data.
[0046]
However, by applying the above-described embodiment, by using the local bus 14 instead of the coprocessor, the CPU 11 can transfer data at the same speed as accessing the cache in the CPU. Data can be transferred with high efficiency, and the CPU 11 can operate with high efficiency. For this reason, for example, if an apparatus including the information processing apparatus 10 as shown in FIG. 1 is used as a real-time encoder of an audio signal or a video signal, it has a great influence, without preparing a special processing apparatus separately. High speed operation is possible.
[0047]
In this specification, the steps for describing the program provided by the medium are performed in parallel or individually in accordance with the described order, as well as the processing performed in time series, not necessarily in time series. The process to be executed is also included.
[0048]
【The invention's effect】
According to the information processing apparatus of the present invention, data can be transferred between the CPU and the storage device.
[0049]
Further , according to the information processing apparatus of the present invention, data transfer between the CPU and the storage device can be performed with higher efficiency, and the data processing speed can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of an information processing apparatus to which the present invention is applied.
FIG. 2 is a flowchart for explaining the operation of the information processing apparatus.
FIG. 3 is a diagram for explaining an extension instruction;
FIG. 4 is a diagram for explaining an extension instruction;
FIG. 5 is a diagram for explaining a mask.
FIG. 6 is a diagram for explaining a local bus protocol;
FIG. 7 is a diagram for explaining a local bus protocol;
FIG. 8 is a diagram for explaining a local bus protocol;
FIG. 9 is a diagram for explaining a local bus protocol;
[Explanation of symbols]
10 information processing device, 11 CPU, 12 local bus interface, 13 local memory, 14 local bus, 15 standard memory bus, 16 registers, 17 memory

Claims (4)

A first storage device accessed only by the CPU;
A second storage device accessed by a device different from the CPU and the CPU;
A first bus connecting the CPU and the first storage device;
A second bus for connecting the CPU and the second storage device;
The instruction set for the first bus used between the CPU and the first storage device via the first bus is:
Latency is fixed length, does not have Acknowledge as one of the response signals ,
Having no offset value and accessing the first storage device using an immediate value or a pointer;
When accessing the first storage device using the pointer, a mask is applied to a predetermined upper bit of the value stored in the pointer of the instruction set for the first bus, and the predetermined storage An information processing apparatus configured to increase or decrease only lower bits other than upper bits . The instruction set for the first bus has the same format as the instruction set for the second bus used between the CPU and the second storage device via the second bus. The information processing apparatus according to 1. The information processing apparatus according to claim 1, further comprising a third bus that connects the first storage device and the second bus. The information processing apparatus according to claim 1, wherein the first bus is connected to a coprocessor port of the CPU.

Images