JP4227971B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and a semiconductor module.

  Semiconductor devices are used in various information devices such as large computers, personal computers, and portable devices, and required functions and capacities are increasing year by year. Along with these higher performance and larger capacity, the mounting area of the semiconductor element on the base substrate increases, which is a factor that hinders downsizing. Therefore, as a technique for mounting many semiconductor elements on a limited base substrate area, a technique for stacking and mounting a plurality of semiconductor elements on a base substrate has been developed. As a technique for laminating the semiconductor elements, a plurality of individual semiconductor packages each composed of a semiconductor element and a wiring member are laminated to form a laminated semiconductor package, and the laminated semiconductor package is mounted on a base substrate. A technique for forming a semiconductor device by extending to both sides of a semiconductor element and connecting to a base substrate has been developed. As patent documents related to this, Japanese Patent Application Laid-Open No. 2002-176135 (Patent Document 1), Japanese Patent Application Laid-Open No. 8-236694 (Patent Document 2), Japanese Patent Application Laid-Open No. 2000-286380 (Patent Document 3), and Japanese Patent Application Laid-Open Publication No. 2004. -335624 (patent document 4).

JP 2002-176135 A JP-A-8-236694 JP 2000-286380 A JP 2004-335624 A JP 2001-110978 A

  The linear expansion coefficient of the semiconductor element is smaller than the linear expansion coefficient of the resin or metal used for the base substrate or the wiring member. Therefore, when a heat load such as heat generation or environmental temperature change due to the operation of the semiconductor element is applied to the semiconductor device, a thermal deformation amount difference occurs between the semiconductor element and the wiring member or between the individual semiconductor package and the base substrate.

  In a conventional semiconductor device in which the planar dimension of a semiconductor element is small with respect to the entire mounting area, a connection portion extending from the semiconductor element can be made sufficiently long, thereby absorbing a thermal deformation amount difference by deformation of the connection portion. It was possible to do. However, if the high-dimensional mounting is attempted by increasing the planar dimensions of the semiconductor element with respect to the mounting area of the base substrate, the dimensional tolerance of the connection portion must be reduced, and the difference in the amount of thermal deformation is reduced. The deformation of the connection portion makes it difficult to sufficiently absorb, and there is a possibility that the connection portion is broken due to a thermal load. In particular, in a semiconductor device provided with a stacked semiconductor package, a heat generation load due to the operation of a plurality of stacked semiconductor elements increases, and thus there is a limit in preventing connection portion breakage due to deformation of the connection portion.

  Further, in a semiconductor device provided with a stacked semiconductor package, the semiconductor elements constituting the individual semiconductor package are being thinned so as not to increase the total thickness of the stacked individual semiconductor packages. However, in the conventional semiconductor device in which the wiring member of the individual semiconductor package is extended to both sides of the semiconductor element and connected to the base substrate, it is found that if the semiconductor element is made too thin, the semiconductor element is greatly warped and deformed by a thermal load. It was. For this reason, this large bending deformation must be absorbed by the connecting portions on both sides of the semiconductor element, and the bending stress increases due to warping deformation and the relative stress with other members decreases, resulting in compressive stress and tension. There is a concern that an increase in stress or the like may cause a malfunction or breakage of the semiconductor element, and a new problem has arisen that reliability must be ensured.

  An object of the present invention is to provide a semiconductor device, a method of manufacturing the same, and a semiconductor module that can increase the mounting density while ensuring high reliability.

  In order to achieve the above object, a first aspect of the present invention includes: a stacked semiconductor package configured by stacking a plurality of individual semiconductor packages each having a semiconductor element fixed to a wiring member made of a flexible substrate and wiring; and the stacked semiconductor In a semiconductor device comprising a base substrate mounted with an interface chip that functions as an interface between the package and the outside of the device, at least the wiring of the wiring member fixed to the semiconductor element extends from only one side of the semiconductor element, and Connected to the base substrate.

A more preferable specific configuration example in the first aspect of the present invention is as follows.
(1) The wiring member fixed to the semiconductor element is extended from only one side of the semiconductor element and connected to the base substrate.
(2) As the semiconductor element, a thin semiconductor element having a planar rectangular shape and a side parallel to the extending direction of the wiring member being 30 times or more than the thickness is used, and a wiring member thinner than the semiconductor element is used as the wiring member. thing.
(3) A low-elasticity connecting member is interposed between the stacked semiconductor package and the base substrate.
(4) The laminated semiconductor package is configured by interposing a low-elasticity connecting member between each of the individual semiconductor packages.
(5) In the above (1), the extension dimension of the wiring extending to the same side from the individual semiconductor package is increased as the wiring extending from the individual semiconductor package far from the base substrate.
(6) In the above (1), the wiring member is extended from different sides of the plurality of semiconductor elements and connected to the base substrate.
(7) In the above (1), the semiconductor element and the wiring member constituting the individual semiconductor package are resin-molded.
(8) In the above (1), an upper surface and a lower surface of the stacked semiconductor package are connected to the same fixing member, and the stacked semiconductor package is formed by the fixing member in at least a part of a temperature range where the stacked semiconductor package is used. Compressive load is applied to the upper and lower surfaces of
(9) The flexible substrate is bent into a U shape and connected to the base substrate.
(10) In the above (9), the surface of the base substrate on which the connection portion between each flexible substrate and the base substrate is provided is the surface opposite to the side on which the stacked semiconductor package is installed. .
(11) The semiconductor element constituting the stacked semiconductor package is a DRAM chip.
(12) The interface chip is interposed between the stacked semiconductor package and the base substrate.

  According to a second aspect of the present invention, a step of configuring an individual semiconductor package by fixing a wiring member composed of a flexible substrate and wiring to the semiconductor element such that at least wiring is extended from only one side of the semiconductor element; A method of manufacturing a semiconductor device, comprising: stacking a plurality of the individual semiconductor packages on a base substrate to form a stacked semiconductor package; and connecting the wiring extended from the individual semiconductor package to the base substrate. .

A more preferable specific configuration example in the second aspect of the present invention is as follows.
(1) After extending each wiring member constituting the laminated semiconductor package from only one side of the semiconductor element and joining the base substrate, the wiring member is bent into a U-shape to form the laminated semiconductor package. Mount on the base board.

  According to a third aspect of the present invention, there is provided a stacked semiconductor package configured by stacking a plurality of individual semiconductor packages each having a semiconductor element fixed to a wiring member made of a flexible substrate and wiring, and a base substrate on which the stacked semiconductor package is mounted. In a semiconductor module in which a plurality of semiconductor devices provided with a plurality of semiconductor devices are arranged on a module substrate, the semiconductor device extends at least the wiring of the wiring member fixed to the semiconductor element from only one side of the semiconductor element. Connected to the base substrate.

  According to the present invention, it is possible to provide a semiconductor device, a manufacturing method thereof, and a semiconductor module capable of increasing the mounting density while ensuring high reliability.

  Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. The same reference numerals in the drawings of the respective embodiments indicate the same or equivalent. In addition, it can be made more effective by combining each Example suitably as needed.

  First, a first embodiment of the present invention will be described with reference to FIGS.

  First, the entire semiconductor device of this embodiment will be described with reference to FIG. 1A and 1B are diagrams showing a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a top view thereof, and FIG. 1B is a front view thereof. In FIG. 1A, the resin 2 is not shown.

  In the present embodiment, a semiconductor package is constituted by one semiconductor element 1, a wiring member 4, and a resin 2, and a semiconductor package having a plurality of semiconductor elements 1 is constituted by stacking the constituted semiconductor packages. Yes. In order to distinguish the names of these semiconductor packages, in the following description, a semiconductor package composed of one semiconductor element 1, a wiring member 4, and a resin 2 is referred to as an individual semiconductor package 13, and is composed of a plurality of individual semiconductor packages 13. This semiconductor package is referred to as a laminated semiconductor package 12.

  The semiconductor device 70 includes a laminated semiconductor package 12 formed by laminating a plurality of individual semiconductor packages 13 in which the semiconductor element 1 is fixed to the wiring member 4 including the flexible substrate 4a and the wiring 4b, and a base substrate on which the laminated semiconductor package 12 is mounted. 5.

  In the individual semiconductor package 13, one semiconductor element 1 is bonded on one wiring member 4, and the resin 2 is formed on the entire periphery of the semiconductor element 1 and on the surface of the wiring member 4 on the side opposite to the semiconductor element. It is constituted by.

  The semiconductor element 1 is a flat rectangular shape, and a thin semiconductor element in which a side (short side in the illustrated example) parallel to the direction in which the wiring member extends from the semiconductor element 1 is 30 times or more than the thickness is used. A DRAM having a long side dimension of about 20 mm, a short side dimension of about 10 mm, and a thickness dimension of about 0.15 mm is used. The circuit surface side of the semiconductor element 1 is bonded to the wiring member 4. The wiring member 4 includes a flexible substrate 4a that can be bent and has flexibility, and a wiring 4b disposed on the surface thereof. As the wiring member 4, a wiring member thinner than the semiconductor element 1 is used. Specifically, a polyimide tape having a thickness of about 0.03 mm is used as the flexible substrate 4a, and a Cu tape having a thickness of about 0.02 mm is used as the wiring 4b. Is used.

  As described above, since the thickness of the individual semiconductor package 13 can be reduced by using the thin semiconductor element 1, the thin flexible substrate 4a, and the thin wiring 4b, the individual semiconductor package 13 suitable for stacking can be obtained. it can. Moreover, since the thickness of the wiring member 4 is reduced by using the thin flexible substrate 4a and the thin wiring 4b, and the bending rigidity of the wiring member 4 is lowered, it is possible to easily perform bonding when the individual semiconductor packages 13 are stacked. it can. By using polyimide for the flexible substrate 4a, it is possible to withstand a temperature history such as a solder reflow process while having flexibility in bending the flexible substrate 4a. Further, the Cu surface used for the wiring 4b is plated with Ni and Au, thereby preventing defects due to oxidation or corrosion of the Cu wiring and facilitating bonding with the base substrate.

  The wiring member 4 fixed to the semiconductor element 1 has a portion extending from only one side of the semiconductor element 1, and the tip portion is connected to the base substrate 5. In this embodiment, the wiring member 4 extends only from one long side of the semiconductor element 1. As a result, the length of the individual semiconductor package 13 in the longitudinal direction can be suppressed, and the wiring member 4 can be extended with the same width. If necessary, the wiring member 4 may extend from only one side of the semiconductor element 1 including the half side of the short side of the semiconductor element 1. The outer shape of the wiring member 4 is formed larger than the outer shape of the semiconductor element 1, and the length of the flexible substrate 4 a is larger than that of the semiconductor element 1, particularly in the short direction of the semiconductor element 1 (direction parallel to the short side). By ensuring that the semiconductor element 1 is sufficiently large and arranged in one direction instead of the center of the flexible substrate 4a, a place for drawing the wiring 4b from only one long side of the semiconductor element 1 on the flexible substrate 4a is secured. The wiring 4b is pulled out together with the flexible substrate 4a. In this way, the wiring 4b is drawn out from only one direction of the semiconductor element 1. Further, by providing a resin 2 around the semiconductor element 1, the adhesion between the wiring member 4 and the semiconductor element 1 is improved, and peeling of the semiconductor element 1 and the wiring member 4 and peeling of the surface thin film of the semiconductor element 1 are prevented. ing.

  The semiconductor device 70 mainly includes a single base substrate 5, an interface chip 8 disposed on the surface of the base substrate 5, a laminated semiconductor package 12, and solder balls 6.

  The base substrate 5 is a glass epoxy substrate having a thickness of about 0.3 mm, and has a total of four Cu wiring layers, two layers on the surface and two layers inside. Similar to the wiring 4 b of the individual semiconductor package 13, the surface of the wiring exposed on the surface of the base substrate 5 is plated with Ni or Au.

  The interface chip 8 is equivalent in thickness to the semiconductor element 1 mounted on the individual semiconductor package 13 and has a smaller planar dimension than the semiconductor element 1 mounted on the individual semiconductor package 13. This difference in planar dimension is due to a difference in function between the interface chip 8 and the semiconductor element 1 mounted on the individual semiconductor package 13. The interface chip 8 is a chip that functions as an interface between the outside of the semiconductor device 70 and the semiconductor element 1 that is a DRAM. Therefore, the semiconductor element 1 mounted on the individual semiconductor package 13 does not have an interface function, and may function as an aggregate of memory cells. By consolidating the interface functions in the interface chip 8 in this way, it is possible to reduce the power consumed for the interface function as compared with the case where each semiconductor element 1 has the interface function individually. As a result, heat generated in the entire stacked semiconductor package 12 can be reduced, so that damage or malfunction due to temperature rise of the semiconductor element 1 or the interface chip 8 during operation can be prevented. The interface chip 8 is electrically connected to the base substrate 5 by flip-chip bonding with the circuit surface side facing the base substrate 5. In addition, the connection reliability between the interface chip 8 and the base substrate 5 is improved by underfill sealing the interface chip 8 and the base substrate 5 with the resin 9.

  A plurality of individual semiconductor packages 13 are mounted on the upper portion of the base substrate 5 on which the interface chip 8 is mounted. Each individual semiconductor package 13 has substantially the same size except for the length of the wiring 4b to be drawn out and the length of the flexible substrate 4a for drawing out the wiring 4b. The length of the extracted wiring 4b is longer as the individual semiconductor package 13 is farther from the base substrate 5. In this way, by changing the dimensions of the flexible substrate 4a in each individual semiconductor package 13, it is possible to prevent the flexible substrates 4a from interfering with each other after mounting, and each flexible substrate 4a has an appropriate deflection. The deformation absorbability can be improved. The wiring 4b drawn from each individual semiconductor package 13 is ultrasonically bonded to the wiring on the surface of the base substrate 5 so that the individual semiconductor package 13 and the base substrate 5 are electrically connected. In this case, the end of the base substrate 5 is closer to the joint between the wiring 4b of the individual semiconductor package 13 and the base substrate 5 that are stacked at a position farther from the base substrate 5 so that the wiring members 4 of the individual semiconductor packages 13 do not intersect with each other. It is provided in the position near.

  Connection members 7 are arranged between the individual semiconductor packages 13 and between the individual semiconductor packages 13 and the interface chip 8. In this embodiment, a low-elastic elastomer is used for the connection member 7. By disposing a low-elasticity member between the individual semiconductor packages 13 and between the individual semiconductor package 13 and the interface chip 8, it is possible to absorb the horizontal displacement of the individual semiconductor packages 13, respectively. The warp deformation of the individual semiconductor package 13 can be reduced.

  Solder balls 6 are disposed on the lower surface of the base substrate 5. With this solder ball, it is possible to establish electrical continuity between the semiconductor device 70 and the external substrate. Thus, in the laminated semiconductor package 12 configured by laminating the individual semiconductor packages 13, the wiring 4 b drawn from each individual semiconductor package 13 is only in one direction, and the individual semiconductor package 13 and the base substrate 5 A major feature of the present embodiment is that the junction is also provided in only one direction with respect to each semiconductor element 1.

  In this way, at least the wiring 4b of the wiring member 4 fixed to the semiconductor element 1 is extended from only one side of the semiconductor element 1, and a connection portion 3 between the extended portion and the base substrate 5 is provided, thereby enabling a temperature cycle test or Even when thermal deformation occurs in each member due to a change in environmental temperature, heat generation during operation, or the like, it is possible to prevent a large thermal stress from being generated in the joint portion, and to obtain a highly reliable semiconductor device.

  Next, a mechanism for improving the reliability of the semiconductor device against thermal deformation will be described with reference to FIGS.

  FIG. 2 is a diagram for explaining thermal deformation of the semiconductor device of Comparative Example 1 and this example.

  FIG. 2A shows the heat generated in each member when a temperature change ΔT is applied to the semiconductor device (Comparative Example 1) having a connection member between the individual semiconductor packages 13 and having the connection portions 3 on both sides of the individual semiconductor package 13. It is a figure which shows the representative value of a deformation | transformation.

  When the length of the individual semiconductor package 13 is L1 and the horizontal linear expansion coefficient of the entire individual semiconductor package is α1, the thermal deformation amount of the entire individual semiconductor package 13 is represented by α1 × L1 × ΔT. Since the structure in which the connection portions 3 are provided on both sides of the individual semiconductor package 13 is a left-right symmetric structure, the movement amount of the end portion of the individual semiconductor package 13 is α1 × (L1 / 2) × ΔT, respectively.

  On the other hand, if the length between the connecting portions 3 provided on both sides of the base substrate 5 is L2, and the horizontal linear expansion coefficient of the base substrate 5 is α2, the amount of thermal deformation of the entire base substrate 5 is α2 × L2 ×. It is represented by ΔT. Here, L2 is defined by using the dimension of the individual semiconductor package 13 stacked closest to the base substrate 5 in which the dimension of the connecting portion is the shortest and reliability is an issue. Since the left and right sides of the base substrate 5 are also symmetrical, the amounts of movement of the connecting portions at both ends of the base substrate 5 are α2 × (L2 / 2) × ΔT, respectively.

  As a result, a difference of (α1 × (L1 / 2) × ΔT) − (α2 × (L2 / 2) × ΔT) occurs in the end portion thermal deformation amount between the individual semiconductor package 13 and the base substrate 5. The individual semiconductor package 13 is mainly composed of silicon which is the semiconductor element 1, polyimide or Cu of the wiring member 4, and the base substrate 5 is composed of glass epoxy composite material or Cu. Among these members, silicon has a linear expansion coefficient of about 3 ppm / K, and polyimide, Cu, or a glass epoxy composite has a linear expansion coefficient of 10 ppm / K or more. Further, the semiconductor element 1 has a longitudinal elastic modulus larger than that of the wiring member 4 and a thickness equal to or greater than that. Under these conditions, the overall linear expansion coefficient α1 of the individual semiconductor package 13 becomes smaller than the linear expansion coefficient α2 of the base substrate 5 in order to approach the linear expansion coefficient of silicon, and the linear expansion coefficient α1 of the individual semiconductor package 13 and the base There is a large difference in the linear expansion coefficient α2 of the substrate 5. Therefore, the end thermal deformation amount is large.

  By the way, when the capacity and function of the semiconductor element 1 are increased, the dimension L1 of the individual semiconductor package 13 increases. In addition, since the heat generation amount increases in the semiconductor element 1 having a large capacity and high functionality, the temperature rise amount ΔT during operation increases. Since these increases in L1 and ΔT also lead to an increase in the end portion thermal deformation amount, the deformation amount to be absorbed by the connecting portion is increased. On the other hand, in order to increase the mounting density, it is necessary to reduce the difference between the length L1 of the individual semiconductor package 13 and the length L2 of the base substrate 5. Since the difference between L2 and L1 is the length of the connecting portion itself, it is necessary to reduce the length of the connecting portion. Therefore, when a large-capacity, high-performance semiconductor element is mounted at a high density, the amount of absorption to be deformed increases, but the length of the connecting portion itself that absorbs deformation decreases, resulting in large stress at the joint. There is a concern to do. For this reason, in the semiconductor device of Comparative Example 1 shown in FIG.

  FIG. 2B is a diagram showing a representative value of thermal deformation occurring in each member when a temperature change ΔT is applied to the semiconductor device 70 (this embodiment) in which the connection portion 3 is provided only on one side of the individual semiconductor package 13. is there.

  The amount of thermal deformation of the entire individual semiconductor package 13 and the amount of thermal deformation of the entire base substrate 5 of this embodiment are the same as those in the comparative example, and are α1 × L1 × ΔT and α2 × L2 × ΔT, respectively. However, in this embodiment, unlike the comparative example, the connection portion 3 is provided only on one side, so the difference between the amount of thermal deformation of the entire individual semiconductor package 13 and the amount of thermal deformation of the entire base substrate 5 is on the side without the connection portion 3. It can be absorbed by the movement of the end of the individual semiconductor package 13. Therefore, it is not necessary for the connection part 3 of the present embodiment to absorb the difference between the thermal deformation amount of the entire individual semiconductor package 13 and the thermal deformation amount of the entire base substrate 5. As a result, in this embodiment, a large stress is not generated in the connection portion 3, the reliability of the joint portion can be improved, and even when a large-capacity and high-performance semiconductor element is mounted at a high density. The reliability of the joint can be ensured.

  FIG. 3 shows the deformation of the semiconductor device (Comparative Example 2) in which the connection portions 3 are provided on both sides of the individual semiconductor package 13 without having a connection member between the individual semiconductor packages 13, using the finite element method. The analysis result is shown. In FIG. 3, the deformation is shown in an enlarged manner.

  As shown in FIG. 3B, each individual semiconductor package 13 is warped upwardly. This is a phenomenon that occurs because the linear expansion coefficient of the semiconductor element 1 is smaller than that of the wiring member 4 and the resin 2. Due to this warpage deformation, bending deformation occurs in the connection portions 3 on both sides of the individual semiconductor package 13. Therefore, not only the horizontal deformation described above but also the bending deformation may cause a decrease in the reliability of the joint. In particular, when the individual semiconductor package 13 is thinned, the warpage of the individual semiconductor package 13 increases even if the planar dimensions and the temperature change amount of the semiconductor element 1 are the same. Become prominent. Furthermore, when the warpage deformation of the individual semiconductor package 13 is large, a large bending stress is generated in the semiconductor element 1. If a large stress acts on the circuit surface of the semiconductor element 1, it may cause malfunction or circuit breakage, so that countermeasures are also an issue.

On the other hand, in the present embodiment, each individual semiconductor package 13 is planarly connected by the connection member 7 that is a low-elasticity material, so that warping deformation of the individual semiconductor package 13 can be restrained. Therefore, the bending deformation that the connecting portion 3 must absorb is very small. At this time, since the connection member 7 has low elasticity and very low shear rigidity, the effect of absorbing deformation in the horizontal direction described with reference to FIG. 2 is not hindered. Further, since the connection part 3 is provided only on one side of the individual semiconductor package 13, slight warping deformation of the individual semiconductor package 13 can be absorbed by movement on the side where the connection part 3 is not provided. By the way, the process of joining the semiconductor element 1 of the individual semiconductor package and the flexible substrate 4 is performed at a temperature higher than the environment in which the semiconductor device is used. For this reason, in an environment where the temperature is lower than the bonding temperature, the individual semiconductor package is warped and deformed upward (the semiconductor element 1 side is convex) due to the difference in linear expansion coefficient between the semiconductor element 1 and the flexible substrate 4. In this embodiment, since the interface chip 8 to be placed between the individual semiconductor package 13 and the base substrate 5 is smaller than the individual semiconductor package 1, between air is provided in the neighborhood of the interface chip 8. It is also one of the features of the present invention that this space can absorb convex warpage deformation on the individual semiconductor package 13. Because of these effects, warp deformation of the individual semiconductor package can be absorbed, and thus the reliability of the connection portion 3 can be sufficiently ensured. Moreover, since the bending stress generated inside the semiconductor element 1 can be reduced by reducing the warp deformation of the semiconductor element 1, it is possible to prevent malfunction caused by stress and damage to the circuit surface.

  As is apparent from the description with reference to FIGS. 2 and 3, the semiconductor device of this embodiment can ensure high reliability.

  Next, the joining structure and joining method of the connecting portion 3 of this embodiment will be described with reference to FIG. FIG. 4 is an enlarged view of a portion A in FIG.

  The wiring member 4 and the base substrate 5 are bonded by an ordinary temperature ultrasonic bonding method. Specifically, the base substrate surface wiring 21 provided on the surface of the base substrate 5 and the wiring 4b provided on the surface of the flexible substrate 4a on the base substrate 5 side are bonded by an ultrasonic bonding method at room temperature. . Since the joining locations are provided in a straight line parallel to the long side direction of each individual semiconductor package 13, one individual piece can be obtained by using a linear joining tool having a length equivalent to the width of the flexible substrate 4a. The semiconductor package 13 and the base substrate 5 can be bonded in one step. Therefore, when the four individual semiconductor packages 13 are stacked, the number of bonding steps required for assembling the semiconductor device 70 may be four. In this bonding method, since the bonding can be performed at room temperature, a positional shift due to thermal deformation does not occur. Therefore, since the wiring 4b can be arranged at a gorgeous pitch, it is possible to draw out the wiring 4b only on one side even when the number of wiring is large as in the case of stacking a large capacity DRAM.

  In this embodiment, room temperature ultrasonic bonding is used for bonding the wiring member 4 and the base substrate 5, but other bonding methods such as soldering may be used depending on the number of wirings that need to be bonded and the condition of the pitch width. it can. When using solder bonding, the area required for bonding is larger than that of room temperature ultrasonic bonding. Moreover, since heating up to the solder melting point or more is required, there is a concern about displacement due to thermal deformation. For this reason, since it is necessary to increase the connection pitch width compared to room temperature ultrasonic bonding, the number of wires that can be bonded in the same area is reduced. On the other hand, by performing reflow after all the individual semiconductor packages 13 are arranged on the base substrate 5, there is an advantage that all the individual semiconductor packages 13 can be bonded to the base substrate 5 in one step. Therefore, this connection method is suitable for a semiconductor device having a small number of connection wires between the base substrate 5 and the individual semiconductor package 13.

  Next, a semiconductor module 80 using the semiconductor device 70 of this embodiment will be described with reference to FIGS.

  FIG. 5 is a view showing a semiconductor module (memory module) 80 using the semiconductor device 70 of the present embodiment, FIG. 5 (a) is a top view thereof, and FIG. 5 (b) is a front view thereof.

  The module substrate 31 is a glass epoxy substrate having eight wiring layers, and has a terminal 32 on one side. Nine semiconductor devices 70 are arranged side by side on one surface of the module substrate 31 and are arranged on both surfaces, so that a total of 18 semiconductor devices 70 are arranged on one module substrate 31. In this case, since the area occupied by one stacked semiconductor package 12 on the module substrate 31 is substantially the same as that when no lamination is performed, the same number of stacked semiconductors as when no lamination is performed on one module substrate 31. The package 12 can be mounted. Therefore, the number of semiconductor elements 1 that can be mounted on one module substrate 31 is double the number of stacked layers when stacking is not performed, and the capacity can be increased. In the case of this embodiment, since four semiconductor elements 1 are stacked in one stacked semiconductor package, the capacity can be increased to four times that in the case where stacking is not performed.

  In general, when the laminated semiconductor package 12 is mounted on the module substrate 31, the connection reliability of the solder balls 6 that are the connecting portions between the module substrate 31 and the laminated semiconductor package 12 becomes a problem. This is because the amount of thermal deformation of the base substrate 5 located above the solder balls 6 is reduced by the influence of the semiconductor element 1 mounted on the laminated semiconductor package 12, so that the module substrate located below the solder balls 6. This is because the amount of thermal deformation with 31 increases. However, in the semiconductor device 70 of the present embodiment, the semiconductor directly bonded to the base substrate 5 connected to the module substrate 31 is only the interface chip 8, and the four semiconductor elements 1 stacked thereon are the base substrate. 5 is connected only at one end. Therefore, the four semiconductor elements 1 stacked on the upper side do not affect the thermal deformation of the base substrate 5, and only the interface chip 8 having a small planar dimension has an influence, so that the influence is small. As a result, the difference in thermal deformation between the base substrate 5 and the module substrate 31 becomes small, and the connection reliability of the solder balls 6 connecting between them can be ensured. Note that the connection member 7 is disposed between the interface chip 8 and the individual semiconductor package 13, but since this is a low-elasticity material, the individual semiconductor package 13 passes through the connection member 7 and the heat of the base substrate 5. The effect on deformation is small.

  By configuring the semiconductor module (memory module) in this way, the individual semiconductor package stage, the semiconductor device stage in which the stacked semiconductor package is connected to the base substrate 5 and the semiconductor module stage can be inspected at each stage. Become. Therefore, this configuration is also suitable for the case where a semiconductor element having a low yield during manufacturing, such as a semiconductor element for a high-end product, or a semiconductor element in which a defect is likely to occur in the assembly process is used. In particular, in a memory module, since it is necessary to mount a large number of semiconductor elements 1 on the module substrate 31, the individual semiconductor package is not directly connected to the module substrate 31 but connected to the module substrate 31 via the base substrate 5. It is desirable to do.

  FIG. 6 is a view showing a semiconductor module (memory module) 80 using the semiconductor device and the heat sink of the present embodiment. FIG. 6A is a top view thereof, and FIG. 6B is a front view thereof.

  As described above, each of the semiconductor elements 1 does not have an interface function, and the functions are concentrated on the interface chip 8 to reduce the total amount of heat generation and prevent the temperature increase during the operation of the semiconductor element 1. However, in the memory module in which the semiconductor devices 70 are arranged in one direction as shown in FIG. 6, since the heat generated by each semiconductor device 70 affects the adjacent semiconductor device 70, the semiconductor arranged at the end of the module substrate 31. There is a concern that the temperature of the semiconductor device 70 disposed near the center of the module substrate 31 is higher than that of the device 70. Therefore, as shown in FIG. 6, by disposing the heat radiating plate 41 having good thermal conductivity so as to cover both surfaces of the module substrate 31, the temperature of the semiconductor device 70 at the end of the module substrate 31 and the temperature of the semiconductor device 70 near the center. The difference can be reduced. In this embodiment, a Cu alloy is used for the heat radiating plate 41, and the surface is painted black to improve radiation.

  Further, in order to reduce the thermal resistance between the heat radiating plate 41 and each semiconductor device 70, a heat conducting member 42 having a high thermal conductivity is disposed between the heat radiating plate 41 and the semiconductor device 70. In this embodiment, a low-elasticity resin is used for the heat conducting member 42. By using a low-elasticity material for the heat conducting member 42, it is possible to absorb the height variation of each stacked semiconductor package, so even if the stacked semiconductor packages 12 have different heights, the stacked semiconductor package The temperature rise of 12 can be reduced.

  In addition, since the metal heat sink 41 and the low-elasticity heat conductive member 42 are arranged on the upper portion of the semiconductor device 70, even when a load or an impact is applied from the outside, the heat sink 41 Since the force applied to the laminated semiconductor package 12 and the module substrate 31 can be reduced by the rigidity and the shock absorption property of the heat conducting member 42, a semiconductor device that is resistant to external force and impact can be obtained.

  Next, a method for manufacturing the individual semiconductor package 13 of this embodiment will be described with reference to FIG. FIG. 7 is a process diagram showing a method of manufacturing the individual semiconductor package 13 constituting the semiconductor device 70 of this embodiment. In each process drawing, the upper figure is a plan view and the lower figure is a cross-sectional view.

  First, as shown in FIG. 7A, a wiring member 4 is prepared which is configured by providing Cu wiring 4b on the surface of a polyimide flexible substrate 4a provided with holes 61. The wiring 4b is subjected to wiring processing by etching and then plated with Ni or Au. At this time, the wiring 4b is provided in the hole 61 provided in the flexible substrate 4a so as to straddle the hole 61.

  Next, the semiconductor element 1 is bonded to the wiring member 4 as shown in FIG. At this time, the semiconductor element 1 is bonded so that the circuit surface of the wiring element 4 does not have the wiring 4b. Further, the external input / output terminals 62 of the semiconductor element 1 are aligned so as to be arranged at the positions of the holes 61 provided in the flexible substrate 4a.

  Next, as shown in FIG. 7C, the external input / output terminal 62 of the semiconductor element 1 and the wiring 4b are bonded together by bonding. At this time, the wiring 4b arranged so as to straddle the hole 61 of the flexible substrate 4a is cut by the bonding tool and then joined to the terminal 62 of the semiconductor element 1.

  Finally, as shown in FIG. 7D, the bonding portion and the connection portion between the semiconductor element 1 and the wiring member 4 are sealed with a resin. In this embodiment, the resin 2 is cured by raising the temperature after applying a liquid epoxy potting resin. By using the above steps, the individual semiconductor package 13 of this embodiment can be manufactured.

  Next, a method for manufacturing the semiconductor device 70 of this embodiment will be described with reference to FIG. FIG. 8 is a process diagram showing a method for manufacturing the semiconductor device 70 of this embodiment.

  First, as shown in FIG. 8A, the interface chip 8 is mounted on the surface of the base substrate 5. In this embodiment, the circuit surface of the interface chip 8 is arranged so as to face the base substrate 5 and the flip chip connection is made. Further, the connection portion is sealed with the resin 9 to ensure reliability. Since the interface chip 8 is flip-chip bonded to the base substrate 5 as in this embodiment, the height required for mounting can be reduced compared to a method of mounting using wire bonding or the like. The thickness of the device 70 can be reduced.

  Next, as illustrated in FIG. 8B, the individual semiconductor package 13 is disposed on the interface chip 8. A connection member 7 is sandwiched between the interface chip 8 and the individual semiconductor package 13.

  Next, as shown in FIG. 8C, the wiring member 4 of the individual semiconductor package 13 and the base substrate 5 are ultrasonically bonded. Thereafter, by repeating the steps of FIGS. 8B and 8C as many as the number of individual semiconductor packages 13 to be stacked, the stacked semiconductor package 12 is configured as shown in FIG. 8D. At this time, the wiring member 4 of each individual semiconductor package 13 intersects by making the joint portion between the individual semiconductor package 13 and the base substrate 5 closer to the end portion of the base substrate 5 in later steps. Is preventing.

  Finally, as shown in FIG. 8E, by providing the solder balls 6 on the lower surface of the base substrate 5, the semiconductor device 70 is completed. In addition, a temperature history is required in each bonding process, resin sealing process, and solder mounting process. These temperature control steps can be performed independently for each step, or the steps can be shortened by performing the steps simultaneously.

  As is apparent from the above description, according to the present embodiment, it is possible to absorb the difference in thermal deformation of each member that occurs when a thermal load is applied to the semiconductor device 70 without generating a large stress on each member. In addition, the semiconductor device 70 with high reliability against the heat load can be provided. Since the individual semiconductor package 13 is connected to the base substrate 5 in only one direction, the thermal deformation amount difference between the individual semiconductor package 13 and the base substrate 5 can be absorbed by the expansion / contraction on the unconnected side. Therefore, no great stress is generated in the connection portion between the semiconductor package and the base substrate. In addition, since the individual semiconductor package 13 is connected to the base substrate only in one direction, it is possible to prevent a large stress from being generated in the connection portion 3 due to the warp deformation of the individual semiconductor package 13. Therefore, the thin semiconductor element 1 can be used, and more semiconductor elements can be stacked in the same thickness. Further, since the semiconductor element 1 itself is not subjected to a load such as compression, tension, or bending from the connection portion 3, the stress generated in the semiconductor element 1 can be reduced. Furthermore, since the warping deformation itself of the semiconductor element 1 is reduced, the bending stress generated in the semiconductor element 1 can also be reduced. Furthermore, since the connection location between each individual semiconductor package 13 and the base substrate 5 is only on one side with respect to each semiconductor element 1, the area of the connection location can be reduced, and the mounting density of the semiconductor elements 1 is improved. can do. As a result, it is possible to provide a semiconductor device with higher functionality, larger capacity, and smaller space than conventional ones.

  Next, a second embodiment of the present invention will be described with reference to FIG. FIGS. 9A and 9B are diagrams showing a semiconductor device 70 according to the second embodiment of the present invention. FIG. 9A is a front view thereof, and FIG. 9B is an enlarged view of a portion B in FIG. The second to tenth embodiments are different from the first embodiment in that they are described in the following description of each embodiment, and are otherwise basically the same as the first embodiment. It is.

  The second embodiment is different from the first embodiment in that the wiring member 4 has two layers of wiring 4b. That is, the wiring member 4 is configured by having the wiring 4b on both surfaces of the flexible substrate 4a. Thus, by providing two layers of the wiring 4b, the electrical characteristics of the wiring portion can be improved, and a semiconductor device capable of operating at higher speed can be obtained. On the other hand, since the wiring 4b is provided on both surfaces of the flexible substrate 4a, the bending rigidity of the wiring member 4 is increased, so that the load necessary for bending the wiring member 4 and the repulsive force against the bending increase. As a method for reducing the bending rigidity, it is possible to reduce the thickness of the flexible substrate 4a and the wiring 4b to be used, provide a hole in a part of the wiring member 4, and improve the pattern shape of the wiring 4b.

  Next, a third embodiment of the present invention will be described with reference to FIG. 10A and 10B are views showing a semiconductor device 70 according to a third embodiment of the present invention. FIG. 10A is a front view thereof, and FIG. 10B is a view showing a modification thereof.

  The third embodiment is different from the first embodiment in that connection portions between the wiring member 4 and the base substrate 5 are provided on both sides of the base substrate. In FIG. 10A, the wiring member 4 of the individual semiconductor package 13 closest to the base substrate and the third individual semiconductor package 13 closest to the base substrate are connected on the left side in the drawing of the base substrate 5. The wiring members 4 of the individual semiconductor package 13 close to and the fourth individual semiconductor package 13 are connected on the right side in the drawing of the base substrate 5. Even in the case where the connection portions 3 are arranged in this way, in each individual semiconductor package 13, the wiring member 4 is drawn from only one side of the individual semiconductor package 13 and is connected to the base substrate 5 only on one side. Is the same as in the first embodiment. Therefore, the reliability improvement mechanism described using the first embodiment is also valid in the third embodiment. Further, when this embodiment is used, the number of wiring members 4 on one side is halved, so that it becomes easy to prevent interference and contact of each wiring member.

  FIG. 10B shows an embodiment in which the connection parts between the wiring member 4 and the base substrate 5 are provided on both sides of the base substrate, as in FIG. 10A. The difference from FIG. The wiring member 4 of the individual semiconductor package 13 that is closest to the base substrate 5 and the individual semiconductor package 13 that is closest to the second are connected on the right side in the drawing of the base substrate 5. The wiring member 4 of the individual semiconductor package 13 close to is connected on the left side in the drawing of the base substrate 5. By arranging the connection portions in this manner, the base substrate 5 is not moved or rotated when the first individual semiconductor package 13 and the second individual semiconductor package 13 are ultrasonically bonded to the base substrate 5. Therefore, equipment and process time required for joining can be shortened. The same applies to the case where the third individual semiconductor package 13 and the fourth individual semiconductor package 13 are joined.

  10 (a) and 10 (b), an example in which the wiring member 4 is disposed on both the left and right sides of the base substrate 5 is shown because the embodiment has been described using the front view of the semiconductor device 70. It is also possible to pull out the wiring member 4 to each of the four sides of the base substrate 5.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a front view of a semiconductor device 70 according to the fourth embodiment of the present invention.

  The fourth embodiment is different from the first embodiment in that the laminated semiconductor package 12 is sealed with a mold resin 101. When the laminated semiconductor package 12 is sealed with the mold resin 101 as in the fourth embodiment, the effect of absorbing the thermal deformation difference described in the first embodiment by the movement on the side without the connecting portion is reduced. Instead, reliability can be ensured by sealing and strengthening the joint portion between the wiring member 4 and the base substrate 5 and the like where securing reliability is an issue with the mold resin 101. Since warping deformation of the individual semiconductor package 13 can also be reduced by sealing with the mold resin 101, it is possible to prevent malfunction and damage of the element due to warping. Further, since the dimensions of the base substrate 5 are the same as those in the first embodiment, the mounting density is high as in the first embodiment.

  Next, a fifth embodiment of the present invention will be described with reference to FIG. 12A and 12B show a semiconductor device 70 according to a fifth embodiment of the present invention. FIG. 12A is a front view thereof, and FIG. 12B is a package fixing member 111 used in the semiconductor device 70 of FIG. FIG.

  The fifth embodiment is different from the first embodiment in that the upper surface of the stacked uppermost individual semiconductor package 13 and the lower surface of the base substrate 5 are fixed by being compressed by the package fixing member 111. . At this time, the individual semiconductor package 13 is pressed by the repulsive force of the bent wiring member 4 by holding the individual semiconductor package 13 in the direction of the base substrate 5 using a material having a large elastic range such as a spring material for the fixing member 111. Can cancel out the force to move away from the base substrate 5. At this time, it is desirable to hold the individual semiconductor package 13 in the direction of the base substrate 5 in all temperature ranges in which the semiconductor device 70 is used. However, if the individual semiconductor package 13 can be pressed in a part of the temperature range, the effect is at least in that temperature range. Obtainable.

  Further, the surface of the package fixing member 111 that comes into contact with the base substrate 5 is formed in a U shape so that the contact between the solder ball 6 and the package fixing member 111 can be prevented. By fixing the individual semiconductor package 13 using the package fixing member 111 as in the fifth embodiment, the connection member 7 does not need to have an adhesive force. For this reason, the width | variety of the material which can be used for the connection member 7 can be expanded. Further, by using a material having good thermal conductivity for the package fixing member 111, the temperature difference between the upper surface of the individual semiconductor package 13 and the lower surface of the base substrate 5 can be reduced. As a result, the temperature difference between the stacked semiconductor elements 1 and interface chips 8 is reduced, and the maximum temperature of the semiconductor elements 1 and interface chips 8 can be lowered. In the fifth embodiment, the above feature is effectively utilized by using a Cu alloy for the package fixing member 111.

  Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a front view of a semiconductor device 70 according to the sixth embodiment of the present invention.

  In the sixth embodiment, the wiring member 4 is bent into a U-shape on the base substrate 5, and the surface opposite to the base substrate 5 (upper side in the drawing) at the position where the semiconductor element 1 is stacked is the base substrate. The difference from the first embodiment is that it is the same surface as the surface connected to 5. By selectively using the sixth embodiment and the first embodiment, connection to the base substrate 5 is possible regardless of the surface of the wiring member 4 where the wiring 4b is provided. Further, in the case of the sixth embodiment, the connection portion between the individual semiconductor package 13 and the base substrate 5 can be disposed below the stacked semiconductor elements 1, that is, in the vicinity of the interface chip 8, so that the size of the base substrate can be reduced. it can. As a result, the planar dimension of the semiconductor device 70 can be reduced, and the mounting density can be further increased.

  Next, a seventh embodiment of the present invention will be described with reference to FIG. FIG. 14 is a front view of a semiconductor device 70 according to a seventh embodiment of the present invention.

  The seventh embodiment is different from the sixth embodiment in that the wiring member 4 is arranged above the semiconductor element 1 (position far from the base substrate 5) in each individual semiconductor package to be stacked. . In this case, the circuit surface of the semiconductor element 1 is arranged on the upper side (position far from the base substrate 5). By selecting the sixth embodiment and the seventh embodiment, the connection to the base substrate 5 becomes possible regardless of which surface of the wiring member 4 is provided with the wiring 4b.

  Next, an eighth embodiment of the present invention will be described with reference to FIGS. 15A and 15B are diagrams showing a semiconductor device 70 according to an eighth embodiment of the present invention. FIG. 15A is a front view thereof, and FIG. 15B is a diagram showing a modification of the semiconductor device 70 of FIG. FIG. 16 is a process diagram showing a method for manufacturing the semiconductor device 70 of FIG.

  The eighth embodiment is different from the first embodiment in that the connection member 3 between the wiring member 4 and the base substrate 5 of each individual semiconductor package 13 is provided on the lower surface of the base substrate 5. By disposing the connection portion 3 in this manner, the connection portion 3 can be provided on the lower side of the semiconductor element 1, that is, in the vicinity of the solder ball 6, so that the planar dimension of the stacked semiconductor package 12 can be reduced and further mounted. The density can be increased. In addition, the radius of curvature of the wiring member 4 can be increased by the thickness of the base substrate 5 as compared with the case where the connection portion 3 is disposed on the upper surface of the base substrate 5. As a result, since the bending stress generated in the wiring member 4 can be reduced, the reliability of the wiring 4 can be improved. Further, since the radius of curvature is increased, the wiring member 4 having a large bending rigidity can be used.

  In the modification shown in FIG. 15B, the height of the semiconductor device 70 can be further reduced by providing the interface chip 8 on the lower surface of the base substrate 5. As a result, the semiconductor device 70 can be mounted in a thinner space.

  A method for manufacturing the semiconductor device shown in FIG. 15A will be described with reference to FIG. Since the manufacturing method of the individual semiconductor package 13 is the same as that of the first embodiment, the description thereof is omitted.

  First, as shown in FIG. 16A, the interface chip 8 is mounted on the surface of the base substrate 5. This step is the same as the manufacturing method of the first embodiment.

  Next, as shown in FIG. 16B, the wiring member 4 of the individual semiconductor package 13 is bonded to the lower end portion of the base substrate 5. As in the first embodiment, room temperature ultrasonic bonding is used for the bonding method of the eighth embodiment.

  Next, as shown in FIG. 16C, the bonding process is repeated by the number of individual semiconductor packages 13 to be stacked. At this time, the wiring member 4 and the base substrate 5 are joined after the already joined individual semiconductor package 13 and the newly joined individual semiconductor package 13 are connected, thereby facilitating the alignment of the joining portion.

  Next, as shown in FIG. 16D, the wiring member 4 is bent 180 degrees to connect the stacked individual semiconductor packages 13 to the upper surface of the interface chip 8. At this time, by using the end portion of the base substrate 5 as a guide for bending the wiring member 4, the wiring member 4 can be easily bent. At this time, it is possible to prevent the wiring member 4 from being scratched at the end of the base substrate 5 by rounding the end corners of the base substrate 5.

  Finally, the semiconductor device 70 is completed by providing the solder balls 6 on the bottom surface of the base substrate as shown in FIG. In addition, a temperature history is required in each bonding process, resin sealing process, and solder mounting process. These temperature control steps can be performed independently for each step, and the steps can be shortened by performing the steps simultaneously, as in the manufacturing method of the first embodiment.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Of course, it is also possible to carry out the embodiments in combination.

It is a figure which shows the semiconductor device of 1st Example of this invention. It is a figure explaining the typical value of the thermal deformation of the semiconductor device of the comparative example 1 and 1st Example. 6 is a diagram illustrating thermal deformation of a semiconductor device of Comparative Example 1. FIG. It is the A section enlarged view of FIG.1 (b). It is a figure which shows the semiconductor module using the semiconductor device of 1st Example. It is a figure which shows the semiconductor module using the semiconductor device and heat sink of 1st Example. It is process drawing which shows the manufacturing method of the separate semiconductor package which comprises the semiconductor device of 1st Example. It is process drawing which shows the manufacturing method of the semiconductor device of 1st Example. It is a figure which shows the semiconductor device of 2nd Example of this invention. It is a figure which shows the semiconductor device of 3rd Example of this invention. It is a front view which shows the semiconductor device of 4th Example of this invention. It is a figure which shows the semiconductor device of 5th Example of this invention. It is a front view of the semiconductor device of 6th Example of this invention. It is a front view of the semiconductor device of 7th Example of this invention. It is a figure which shows the semiconductor device of 8th Example of this invention. FIG. 16 is a process diagram illustrating a method of manufacturing the semiconductor device of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Resin, 3 ... Connection part, 4 ... Wiring member, 4a ... Flexible substrate, 4b ... Wiring, 5 ... Base substrate, 6 ... Solder ball, 7 ... Connection member, 8 ... Interface chip, 9 ... Resin, 10 ... Interface chip outline, 11 ... Solder ball, 12 ... Multilayer semiconductor package, 13 ... Individual semiconductor package, 21 ... Base substrate surface wiring, 22 ... Joining tool trace, 31 ... Module substrate, 32 ... Terminal, 41 ... Heat dissipation Reference numeral 42... Heat conduction member 61... Hole 62. Terminal 70. Semiconductor device 80. Semiconductor module 101. Mold resin 111.

Claims (14)

A laminated semiconductor package configured by laminating a plurality of individual semiconductor packages each having a semiconductor element fixed to a wiring member made of a flexible substrate and wiring; and
A base substrate mounted with an interface chip that functions as an interface between the stacked semiconductor package and the outside of the device;
In the semiconductor device in which at least the wiring of the wiring member fixed to the semiconductor element extends from only one side of the semiconductor element and is connected to the base substrate.
The planar dimension of the interface chip is smaller than the planar dimension of the semiconductor element mounted on the individual semiconductor package, and the interface chip surrounds a space for absorbing convex warpage deformation on the individual semiconductor package. The semiconductor device is disposed between the stacked semiconductor package and the base substrate.   2. The semiconductor device according to claim 1, wherein the wiring member fixed to the semiconductor element extends from only one side of the semiconductor element and is connected to the base substrate.   3. The semiconductor device according to claim 2, wherein the semiconductor element is a thin semiconductor element having a planar rectangular shape and a side parallel to the direction in which the wiring member extends is 30 times or more than the thickness, and the wiring member is thinner than the semiconductor element. A semiconductor device using a wiring member.   2. The semiconductor device according to claim 1, wherein a low-elasticity connecting member is interposed between the stacked semiconductor package and the base substrate.   2. The semiconductor device according to claim 1, wherein the stacked semiconductor package is configured by interposing a low-elasticity connecting member between each of the individual semiconductor packages.   3. The semiconductor device according to claim 2, wherein an extension dimension of the wiring extending to the same side from the individual semiconductor package is increased as a wiring extending from the individual semiconductor package far from the base substrate.   3. The semiconductor device according to claim 2, wherein the wiring member is extended from different sides of the plurality of semiconductor elements and connected to the base substrate.   3. The semiconductor device according to claim 2, wherein the semiconductor element and the wiring member constituting the individual semiconductor package are resin-molded.   3. The semiconductor device according to claim 2, wherein an upper surface and a lower surface of the stacked semiconductor package are connected to the same fixing member, and the fixed semiconductor package is configured to be at least partially in a temperature range where the stacked semiconductor package is used by the fixing member. A semiconductor device, wherein a compressive load is applied to an upper surface and a lower surface.   2. The semiconductor device according to claim 1, wherein the flexible substrate is bent into a U shape and connected to the base substrate. The semiconductor device according to claim 10, that surface of the base substrate connecting portion between the flexible substrate before the SL each said base substrate is provided is a surface opposite to the side where the stacked semiconductor package is installed A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, wherein the semiconductor element constituting the stacked semiconductor package is a DRAM chip. A step of configuring an individual semiconductor package by fixing a wiring member composed of a flexible substrate and wiring to the semiconductor element so that the wiring is extended at least from only one side of the semiconductor element;
A step of mounting a smaller interface chip than the planar dimension of the semiconductor device in which the mounted into individual semiconductor package base over scan substrate,
Forming a plurality of the individual semiconductor packages on the interface chip, and forming a laminated semiconductor package having a space around the interface chip to absorb convex warpage deformation on the individual semiconductor package ;
And a step of connecting the wiring extended from the individual semiconductor package to the base substrate. 14. The method of manufacturing a semiconductor device according to claim 13 , wherein each wiring member constituting the stacked semiconductor package is extended from only one side of the semiconductor element and joined to the base substrate, and then the wiring member is formed into a U-shape. A method of manufacturing a semiconductor device, comprising bending and mounting the stacked semiconductor package on the base substrate.

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