JP4226514B2 - amplifier - Google Patents

Description

  The present invention relates to an amplifier using a multilayer wiring technique used in a microwave and millimeter wave band used for wireless communication.

  Field effect transistors (FETs) used in microwave and millimeter wave amplifiers need to increase the gate width in order to obtain a large output power, but the increase in the gate width leads to an increase in parasitic capacitance, and at high frequencies. This leads to a decrease in gain.

  Therefore, in order to obtain a desired high output and a certain level of gain, a method of combining the outputs of a plurality of FETs is employed. Therefore, there is a need for a distributor that distributes the RF signal to the individual FETs and a combiner that combines the outputs.

  In order to synthesize the outputs of a plurality of FETs with high power efficiency, the phases of the respective signals must be aligned at the time of synthesis. For this reason, conventionally, as shown in FIG. 5, a planar tournament distribution circuit and a synthesis circuit are used. However, in the tournament distribution circuit and the synthesis circuit, in order to avoid coupling between the lines, an interval is required between the lines, the path length of the tournament distribution circuit and the synthesis circuit becomes long, and the tournament distribution circuit and the synthesis circuit There is a problem that the area occupied by increases.

  In the conventional analog integrated circuit for microwave and millimeter wave bands, the wiring layer is about two layers, and one of the two layers is used when the metal is thin and the current capacity is small, or for cross connection. It was an air bridge. For this reason, the area of a passive circuit such as an inductor or a stub is formed by a single main wiring layer, leading to an increase in chip area, which is an area occupied by a tournament distribution and synthesis circuit [Non-Patent Document 1].

  A three-dimensional MMIC technique using a multilayer wiring technique has been proposed [Non-Patent Document 2]. The three-dimensional MMIC technology increases the number of wiring layers, and a passive circuit such as an inductor and a stub can be formed using a plurality of wiring layers, so that the chip area can be reduced.

Yasuyuki Ito, Nao Takagi, “Basics and Applications of MMIC Technology” p1-2 and p200-201, Realize, 1996 Aikawa Masayoshi, Tokuman Tsuneo, Yamazaki K., Toyoda Kazuhiko, “Technology Development of 3D MMIC”, NTTR & D, VoL45, No. 12, pp. 1261-1268, 1996

  In order to synthesize the outputs of a plurality of FETs with high power efficiency, the phases of the respective signals must be aligned at the time of synthesis. For this reason, a planar tournament distribution circuit and a synthesis circuit are used. However, in the planar tournament distribution circuit and the synthesis circuit, in order to avoid coupling between the lines, an interval is required between the lines, and the length of the tournament distribution circuit and the synthesis circuit becomes longer, and the tournament distribution circuit In addition, there is a problem that the area occupied by the synthesis circuit increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an amplifier that can reduce the loss of the output section of the amplifier in the microwave band and the millimeter wave band and achieve high efficiency.

In order to achieve this object, in the present invention, N (N is an integer of 2 or more) transistors are formed using a multilayer substrate or a monolithic integrated circuit having M wiring layers (M is an integer of 2 or more) . In an amplifier that operates simultaneously and obtains a combined output of the N transistors, a distribution circuit that distributes an input signal is configured in a vertical tournament shape having N output terminals using via holes between multilayer wirings, wherein the N output terminals of the dividing circuit, are respectively connected to input terminals of each of the N transistors, the output terminals of the N respective transistors are respectively connected to the N input terminals of the combining circuit, by arranging the output terminals of the N respective transistors of the opposite or radially, from the N input terminals of the combining circuit, the length of the path to the one output terminal of said combining circuit But wherein the one input terminal of the distribution circuit, and constitutes the said N short Kunar so than the length of the path to the output terminal of the distribution circuit.

  In the amplifier circuit according to the present invention, the multilayer circuit technique is used, the distribution circuit and the synthesis circuit are downsized by using the vertical tournament wiring, and the output portions of the transistors are arranged oppositely or radially. The path length of the synthesis circuit on the output side of each transistor is shortened, the loss of the output part of the amplifier in the microwave band and the millimeter wave band is reduced, and high efficiency is achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a circuit configuration of an amplifier circuit according to an embodiment of the present invention. First, the configuration of FIG. 1 will be described.

A tournament distribution circuit D that distributes an input signal inputted from a distribution input terminal (one input terminal) A using a multilayer substrate or a monolithic integrated circuit having M wiring layers (M is an integer of 2 or more) is a multilayer wiring. It is formed in a vertical tournament shape having N (N is an integer of 2 or more) output terminals o1 to oN using via holes (Via Hole) between the N output terminals o1 to oN. is connected to the input terminal _T i1 _{through T iN} the number of transistors 1 to N, at the same time to operate the transistors 1 to N, arranged output terminal _T o1 _{through T oN} transistors 1 to N to the counter or radial, the output terminal T the _o1 through T _oN connected to the input terminal i1~iN tournament combining circuit G, synthesized output terminal a synthesized output obtained by combining the output of the transistor 1 to N (1 one output terminal) The circuit configuration of the amplifier obtained from B is shown. Note that the transistors 1 to N in FIG. 1 show only the input and output terminals of the transistors 1 to N, and the remaining one terminal is not shown.

  Next, a method for connecting to a transistor in a vertical tournament shape using multilayer wiring will be described with reference to FIG. The vertical tournament shape is branched in a tournament shape in a vertical direction from a transmission line of a plurality of wiring layers (I-th layer, J-th layer, K-th layer, etc.) via via holes such as through holes. The end of the branched tournament (the input side of the transistor in the distribution circuit and the output side of the transistor in the synthesis circuit) is connected to the transistor via the transmission line or directly from the via hole. FIG. 4 shows a state in which the transistor is connected via a transmission line of the Kth layer, which is the end of the tournament. As described above, the vertical tournament shape can suppress an increase in the circuit area of the tournament distribution and synthesis circuit. In the multilayer wiring technique in MMIC, since the via length is as short as several microns, an increase in the line length can be suppressed.

  Note that FIG. 4 is not a cross-sectional view of FIG. 2 to be described next, but is a diagram for explaining the vertical tournament shape of this embodiment and connection of transistors.

  Next, for an amplifier that synthesizes an output using four transistors (N = 4), FIGS. 2A and 2B are perspective views in which a vertical tournament shape and an output terminal of the transistor are arranged to face each other. The operation will be described with reference to FIG.

First, in FIG. 2A, if an input signal is input to the distribution input terminal A of the I-th layer among the M wiring layers, the input signal constitutes a distribution circuit having a tournament shape in the vertical direction. The transmission lines I1, I2, and I3 in the second layer are distributed to the transmission lines K1, K2, K7, and K8 in the Kth layer via the via holes V _I2 and V _I3 , and are respectively connected to the via holes V _K1 , V _K2 , and V _K7 , V _K8 , input terminals T _{i1 of} transistors 1 to 4 mounted on the L-th layer from the output terminals o1, o2, o3, o4 ahead of the via holes V _K1 , V _K2 , V _K7 , V _K8 , It is distributed to T _i2 , T _i3 , and T _i4 . Input terminal _{T i1,} T _i2 of the transistor _{1~4, T} i3, T _i4 is arranged transistors 1-4 to the output terminals of the transistors _{1~4 T o1, T o2, T} o3, T o4 faces So it is placed outside in the horizontal direction.

On the other hand, the respective output signals from the transistors 1 to 4 are via holes V _K3 that form a tournament-shaped synthesis circuit in the vertical direction from the output terminals T _o1 , T _o2 , T _o3 , and T _o4 arranged so as to face each other. , V _K4 , V _K5 , V _K6 via input terminals i1, i2, i3, i4 and via holes V _K3 , V _K4 , V _K5 , V _K6 and via transmission lines K3, K4, K5, K6 and via holes V _J1 Is synthesized at the synthesis terminal S at the tip of the signal, and is outputted as a synthesis signal from the synthesis output terminal B via the via hole V _J1 and the transmission line J1.

As is apparent from the above description, the length of the path from the four input terminals i1, i2, i3, i4 of the tournament synthesis circuit to one synthesis output terminal B of the tournament synthesis circuit, that is, the four via holes V _K3 , V _K4, the length of the _{V K5, V K6,} the length of the four transmission lines K3, K4, K5, K6, the total length and the length of the transmission line J1 of one via hole _{V J1} is, the tournament distribution circuit 1 The length of the path from one distribution input terminal A to the four output terminals o1, o2, o3, o4, that is, the length of the transmission lines I1, I2, I3, the length of the two via holes V _I2 , V _I3 , and 4 one of the length of the transmission line K1, K2, K7, K8, compared to the sum of the lengths of the four via holes _{V K1, V K2, V K7} , V K8, the shorter is clear.

In FIG. 2B, the input terminals T _i1 , T _i2 , T _i3 and T _i4 of the transistors 1 to 4 are directly connected to the transmission lines K1, K2, K7 and K8 of the Kth layer, and the outputs of the transistors 1 to 4 Terminals T _o1 , T _o2 , T _o3 , T _o4 are directly attached to the transmission lines K3, K4, K5, K6 of the Kth layer, and the length of the route of the tournament-shaped distribution circuit and the synthesis circuit in the vertical direction 2 is shorter than that in FIG. 2A, but the length of the path from the four input terminals i1, i2, i3, i4 of the tournament synthesis circuit to one synthesis output terminal B of the tournament synthesis circuit is It is clear that the length of the path from one distribution input terminal A of the tournament distribution circuit to the four output terminals o1, o2, o3, o4 is shorter.

  Also, as shown in FIG. 3, FIG. 2 (b) is modified so that the composite circuit does not have a vertical tournament shape, and the output terminals of the transistors 1 to 4 are connected to a wide transmission line of the Kth layer to produce a composite output. Since the combined output can be output from the terminal B, the length of the path of the combining circuit becomes shorter.

  As described above, by arranging the output terminals of the four transistors to face each other, the path length of the tournament synthesizing circuit that synthesizes the outputs of the four transistors is shorter than the path length of the tournament distribution circuit that distributes the input signal. can do. It is clear that this is the same even when N transistors are used. Also, for example, when an amplifier is configured using more transistors, the output terminals of the transistors are arranged radially so that the path length of the synthesis circuit is shorter than the path length of the tournament distribution circuit that distributes the input signal. Obviously we can do it.

  As described above, in this embodiment, the distribution circuit and the synthesis circuit are miniaturized by using the multi-layer wiring technique, using the vertical tournament wiring, and the output portions of the transistors are arranged oppositely or radially. Accordingly, the path length of the tournament synthesis circuit on the output side of each transistor can be shortened, the loss of the output part of the amplifier in the microwave band and the millimeter wave band can be reduced, and high efficiency can be achieved. In addition, the tournament distribution circuit on the input side can also achieve uniformity in pass characteristics, the relative phase difference during synthesis is reduced, and the efficiency during synthesis is increased.

1 is a diagram illustrating a circuit configuration of an amplifier circuit according to an embodiment. The perspective view of the amplifier which has arrange | positioned the tournament shape of the orthogonal | vertical direction of embodiment, and the output terminal of a transistor facing. The perspective view at the time of connecting the output terminal of the transistor of an embodiment with a wide transmission line Sectional drawing which shows the connection method to the transistor by the vertical tournament shape using the multilayer wiring of embodiment. A conventional tournament distribution circuit and synthesis circuit and an amplifier using a plurality of transistors.

Explanation of symbols

A distribution input terminal B synthesis output terminal D tournament distribution circuit G synthesis circuit T _i1 , T _i2 , T _i3 , T _i4 transistor input terminals T _o1 , T _o2 , T _o3 , T _o4 transistor output terminals i1, i2, i3 , I4 Tournament synthesis circuit input terminals o1, o2, o3, o4 Tournament distribution circuit output terminals

Claims (1)

Using a multilayer substrate or a monolithic integrated circuit having M (M is an integer of 2 or more) wiring layers, N (N is an integer of 2 or more) transistors are operated simultaneously, and the combined output of the N transistors In the amplifier to obtain
A distribution circuit for distributing an input signal is configured in a vertical tournament shape having N output terminals using via holes between multilayer wirings,
Wherein the N output terminals of the dividing circuit, are respectively connected to input terminals of each of the N transistors,
The output terminal of each of the N transistors are respectively connected to the N input terminals of the combining circuit,
By arranging the output terminals of the N respective transistors of the opposite or radially, from the N input terminals of the combining circuit, the length of the path to the one output terminal of said combining circuit, the distribution An amplifier characterized by being shorter than a length of a path from one input terminal of the circuit to the N output terminals of the distribution circuit.

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