JP4219507B2 - コンピュータ動作方法 - Google Patents

コンピュータ動作方法 Download PDF

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Publication number
JP4219507B2
JP4219507B2 JP27847299A JP27847299A JP4219507B2 JP 4219507 B2 JP4219507 B2 JP 4219507B2 JP 27847299 A JP27847299 A JP 27847299A JP 27847299 A JP27847299 A JP 27847299A JP 4219507 B2 JP4219507 B2 JP 4219507B2
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JP
Japan
Prior art keywords
floating point
status field
status
register
flag information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27847299A
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English (en)
Japanese (ja)
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JP2000122848A5 (https=
JP2000122848A (ja
Inventor
ジェローム・シー・ハック
ピーター・マークスタイン
グレン・ティー・コロン−ボネット
アラン・エイチ・カープ
ロジャー・ゴリヴァー
マイケル・モリソン
ゴータム・ビー・ドシ
ギラルモ・フアン・ロサス
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HP Inc
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Hewlett Packard Co
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Publication date
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Publication of JP2000122848A5 publication Critical patent/JP2000122848A5/ja
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Publication of JP4219507B2 publication Critical patent/JP4219507B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
JP27847299A 1998-10-10 1999-09-30 コンピュータ動作方法 Expired - Fee Related JP4219507B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US169482 1998-10-10
US09/169,482 US6370639B1 (en) 1998-10-10 1998-10-10 Processor architecture having two or more floating-point status fields

Publications (3)

Publication Number Publication Date
JP2000122848A JP2000122848A (ja) 2000-04-28
JP2000122848A5 JP2000122848A5 (https=) 2006-11-09
JP4219507B2 true JP4219507B2 (ja) 2009-02-04

Family

ID=22615891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27847299A Expired - Fee Related JP4219507B2 (ja) 1998-10-10 1999-09-30 コンピュータ動作方法

Country Status (2)

Country Link
US (1) US6370639B1 (https=)
JP (1) JP4219507B2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6604188B1 (en) 1999-10-20 2003-08-05 Transmeta Corporation Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction
US6728865B1 (en) 1999-10-20 2004-04-27 Transmeta Corporation Pipeline replay support for unaligned memory operations
US6804769B1 (en) * 2000-02-18 2004-10-12 Hewlett-Packard Development Company, L.P. Unified buffer for tracking disparate long-latency operations in a microprocessor
US6826682B1 (en) * 2000-06-26 2004-11-30 Transmeta Corporation Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state
US6941449B2 (en) * 2002-03-04 2005-09-06 Hewlett-Packard Development Company, L.P. Method and apparatus for performing critical tasks using speculative operations
US20040143821A1 (en) * 2003-01-21 2004-07-22 Sun Microsystems, Inc. Method and structure for converting data speculation to control speculation
US20040221274A1 (en) * 2003-05-02 2004-11-04 Bross Kevin W. Source-transparent endian translation
US7711928B2 (en) * 2004-03-31 2010-05-04 Oracle America, Inc. Method and structure for explicit software control using scoreboard status information
US20070006195A1 (en) * 2004-03-31 2007-01-04 Christof Braun Method and structure for explicit software control of data speculation
US20170212763A1 (en) * 2014-07-25 2017-07-27 Hewlettt Packard Enterprise Development Lp Exception handling predicate register
US9971604B2 (en) * 2015-02-26 2018-05-15 International Business Machines Corporation History buffer for multiple-field registers
US10067766B2 (en) 2015-02-26 2018-09-04 International Business Machines Corporation History buffer with hybrid entry support for multiple-field registers
US9996353B2 (en) 2015-02-26 2018-06-12 International Business Machines Corporation Universal history buffer to support multiple register types
US10108423B2 (en) * 2015-03-25 2018-10-23 International Business Machines Corporation History buffer with single snoop tag for multiple-field registers
EP4127937A1 (en) 2020-03-27 2023-02-08 Sysdig, Inc. Dynamic instrumentation via user-level mechanisms
US12493543B2 (en) 2021-10-29 2025-12-09 Sysdig, Inc. Dynamic instrumentation to capture cleartext from transformed communications

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5125092A (en) * 1989-01-09 1992-06-23 International Business Machines Corporation Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes
US5574872A (en) * 1991-12-10 1996-11-12 Intel Corporation Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling
US5826069A (en) * 1993-09-27 1998-10-20 Intel Corporation Having write merge and data override capability for a superscalar processing device
US5574942A (en) * 1994-02-28 1996-11-12 Intel Corporation Hybrid execution unit for complex microprocessor
US5701508A (en) * 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
US5835748A (en) * 1995-12-19 1998-11-10 Intel Corporation Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file
US6151669A (en) * 1998-10-10 2000-11-21 Institute For The Development Of Emerging Architectures, L.L.C. Methods and apparatus for efficient control of floating-point status register

Also Published As

Publication number Publication date
US6370639B1 (en) 2002-04-09
JP2000122848A (ja) 2000-04-28

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