JP4219106B2 - 動的優先順位外部トランザクション・システム - Google Patents
動的優先順位外部トランザクション・システム Download PDFInfo
- Publication number
- JP4219106B2 JP4219106B2 JP2001549203A JP2001549203A JP4219106B2 JP 4219106 B2 JP4219106 B2 JP 4219106B2 JP 2001549203 A JP2001549203 A JP 2001549203A JP 2001549203 A JP2001549203 A JP 2001549203A JP 4219106 B2 JP4219106 B2 JP 4219106B2
- Authority
- JP
- Japan
- Prior art keywords
- transaction
- request
- prefetch
- queue
- requests
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
- Cash Registers Or Receiving Machines (AREA)
- Developing Agents For Electrophotography (AREA)
- Measuring Volume Flow (AREA)
- Exchange Systems With Centralized Control (AREA)
- Computer And Data Communications (AREA)
- Memory System (AREA)
- Transmitters (AREA)
- Preparation Of Compounds By Using Micro-Organisms (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/474,011 | 1999-12-28 | ||
| US09/474,011 US6654837B1 (en) | 1999-12-28 | 1999-12-28 | Dynamic priority external transaction system |
| PCT/US2000/032154 WO2001048618A2 (en) | 1999-12-28 | 2000-11-28 | Dynamic priority external transaction system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003521029A JP2003521029A (ja) | 2003-07-08 |
| JP2003521029A5 JP2003521029A5 (enExample) | 2005-11-17 |
| JP4219106B2 true JP4219106B2 (ja) | 2009-02-04 |
Family
ID=23881859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001549203A Expired - Fee Related JP4219106B2 (ja) | 1999-12-28 | 2000-11-28 | 動的優先順位外部トランザクション・システム |
Country Status (10)
| Country | Link |
|---|---|
| US (2) | US6654837B1 (enExample) |
| EP (2) | EP1624379B1 (enExample) |
| JP (1) | JP4219106B2 (enExample) |
| CN (3) | CN100492332C (enExample) |
| AT (1) | ATE317991T1 (enExample) |
| AU (1) | AU1793701A (enExample) |
| DE (2) | DE60039375D1 (enExample) |
| MX (1) | MXPA02005822A (enExample) |
| TW (1) | TW484065B (enExample) |
| WO (1) | WO2001048618A2 (enExample) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3908482B2 (ja) * | 2001-06-22 | 2007-04-25 | 富士通株式会社 | 入出力制御装置及び入出力制御方法並びに情報記憶システム |
| US6732242B2 (en) | 2002-03-28 | 2004-05-04 | Intel Corporation | External bus transaction scheduling system |
| US7315912B2 (en) * | 2004-04-01 | 2008-01-01 | Nvidia Corporation | Deadlock avoidance in a bus fabric |
| US20060123003A1 (en) * | 2004-12-08 | 2006-06-08 | International Business Machines Corporation | Method, system and program for enabling non-self actuated database transactions to lock onto a database component |
| US8032711B2 (en) * | 2006-12-22 | 2011-10-04 | Intel Corporation | Prefetching from dynamic random access memory to a static random access memory |
| US8984198B2 (en) * | 2009-07-21 | 2015-03-17 | Microchip Technology Incorporated | Data space arbiter |
| CN101908000B (zh) * | 2010-07-08 | 2012-10-10 | 北京航空航天大学 | 一种硬件型事务存储系统中事务线程的阻塞唤醒方法 |
| CN101930371A (zh) * | 2010-09-16 | 2010-12-29 | 复旦大学 | 一种基于控制论和目标推理的软件质量运行时优化方法 |
| US9009414B2 (en) * | 2010-09-21 | 2015-04-14 | Texas Instruments Incorporated | Prefetch address hit prediction to reduce memory access latency |
| US8769175B2 (en) * | 2011-03-09 | 2014-07-01 | International Business Machines Corporation | Adjustment of post and non-post packet transmissions in a communication interconnect |
| CN102183923B (zh) * | 2011-04-26 | 2013-06-05 | 中国工商银行股份有限公司 | 一种计算机关联事件执行控制方法及系统 |
| US9251108B2 (en) * | 2012-11-05 | 2016-02-02 | International Business Machines Corporation | Managing access to shared buffer resources |
| KR101641847B1 (ko) * | 2012-12-04 | 2016-07-21 | 도요타지도샤가부시키가이샤 | 충전 제어 장치, 충전 제어 방법, 컴퓨터 프로그램을 기록한 기록 매체 |
| US20180081749A1 (en) * | 2013-12-04 | 2018-03-22 | International Business Machines Corporation | Performance ranking of read requests in a distributed storage network |
| JP6295700B2 (ja) | 2014-02-12 | 2018-03-20 | 株式会社ソシオネクスト | 調停回路及び調停回路の処理方法 |
| CN103984652B (zh) * | 2014-05-28 | 2017-12-19 | 山东超越数控电子有限公司 | 一种基于龙芯平台的北斗通信方法 |
| KR20160018204A (ko) * | 2014-08-08 | 2016-02-17 | 삼성전자주식회사 | 전자 장치, 온 칩 메모리 장치 및 온 칩 메모리의 운영 방법 |
| US10496577B2 (en) * | 2017-02-09 | 2019-12-03 | Hewlett Packard Enterprise Development Lp | Distribution of master device tasks among bus queues |
| US10387320B2 (en) | 2017-05-12 | 2019-08-20 | Samsung Electronics Co., Ltd. | Integrated confirmation queues |
| US11874782B1 (en) * | 2018-07-20 | 2024-01-16 | Robert Gezelter | Fast mass storage access for digital computers |
| US10983836B2 (en) | 2018-08-13 | 2021-04-20 | International Business Machines Corporation | Transaction optimization during periods of peak activity |
| US11470004B2 (en) * | 2020-09-22 | 2022-10-11 | Advanced Micro Devices, Inc. | Graded throttling for network-on-chip traffic |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE414087B (sv) | 1977-02-28 | 1980-07-07 | Ellemtel Utvecklings Ab | Anordning i ett datorsystem vid utsendning av signaler fran en processor till en eller flera andra processorer varvid prioriterade signaler sends direkt utan tidsfordrojning och oprioriterade signalers ordningsfoljd ... |
| US5056041A (en) * | 1986-12-31 | 1991-10-08 | Texas Instruments Incorporated | Data processing apparatus with improved bit masking capability |
| JPH0664567B2 (ja) * | 1989-12-25 | 1994-08-22 | 株式会社日立製作所 | 多重プロセッサシステム |
| US5230078A (en) * | 1991-08-05 | 1993-07-20 | Motorola Inc. | Method for a console to quickly monitor a group |
| US5666494A (en) * | 1995-03-31 | 1997-09-09 | Samsung Electronics Co., Ltd. | Queue management mechanism which allows entries to be processed in any order |
| US5937205A (en) | 1995-12-06 | 1999-08-10 | International Business Machines Corporation | Dynamic queue prioritization by modifying priority value based on queue's level and serving less than a maximum number of requests per queue |
| US5673413A (en) * | 1995-12-15 | 1997-09-30 | International Business Machines Corporation | Method and apparatus for coherency reporting in a multiprocessing system |
| US5761452A (en) | 1996-03-18 | 1998-06-02 | Advanced Micro Devices, Inc. | Bus arbiter method and system |
| US5724613A (en) | 1996-05-06 | 1998-03-03 | Vlsi Technology, Inc. | System and method for automatically enabling and disabling a prefetching capability |
| US6401212B1 (en) * | 1997-08-21 | 2002-06-04 | Texas Instruments Incorporated | Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden |
| US6341335B1 (en) * | 1997-10-29 | 2002-01-22 | Hitachi, Ltd. | Information processing system for read ahead buffer memory equipped with register and memory controller |
| US6484239B1 (en) * | 1997-12-29 | 2002-11-19 | Intel Corporation | Prefetch queue |
| US6148372A (en) * | 1998-01-21 | 2000-11-14 | Sun Microsystems, Inc. | Apparatus and method for detection and recovery from structural stalls in a multi-level non-blocking cache system |
| US6076130A (en) * | 1998-03-19 | 2000-06-13 | Hewlett-Packard Company | System and method for efficient communication between buses |
| US6446143B1 (en) * | 1998-11-25 | 2002-09-03 | Compaq Information Technologies Group, L.P. | Methods and apparatus for minimizing the impact of excessive instruction retrieval |
| US6286074B1 (en) * | 1999-03-24 | 2001-09-04 | International Business Machines Corporation | Method and system for reading prefetched data across a bridge system |
| US6330647B1 (en) * | 1999-08-31 | 2001-12-11 | Micron Technology, Inc. | Memory bandwidth allocation based on access count priority scheme |
| US6553446B1 (en) * | 1999-09-29 | 2003-04-22 | Silicon Graphics Inc. | Modular input/output controller capable of routing packets over busses operating at different speeds |
| US6470427B1 (en) * | 1999-11-09 | 2002-10-22 | International Business Machines Corporation | Programmable agent and method for managing prefetch queues |
| US6704817B1 (en) * | 2000-08-31 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Computer architecture and system for efficient management of bi-directional bus |
-
1999
- 1999-12-28 US US09/474,011 patent/US6654837B1/en not_active Expired - Lifetime
-
2000
- 2000-11-28 DE DE60039375T patent/DE60039375D1/de not_active Expired - Lifetime
- 2000-11-28 CN CNB008177910A patent/CN100492332C/zh not_active Expired - Fee Related
- 2000-11-28 AU AU17937/01A patent/AU1793701A/en not_active Abandoned
- 2000-11-28 EP EP05023715A patent/EP1624379B1/en not_active Expired - Lifetime
- 2000-11-28 WO PCT/US2000/032154 patent/WO2001048618A2/en not_active Ceased
- 2000-11-28 AT AT00980710T patent/ATE317991T1/de not_active IP Right Cessation
- 2000-11-28 EP EP00980710A patent/EP1323045B1/en not_active Expired - Lifetime
- 2000-11-28 MX MXPA02005822A patent/MXPA02005822A/es active IP Right Grant
- 2000-11-28 DE DE60026068T patent/DE60026068T2/de not_active Expired - Lifetime
- 2000-11-28 CN CNA200910130408XA patent/CN101539896A/zh active Pending
- 2000-11-28 CN CN2009101348374A patent/CN101520759B/zh not_active Expired - Fee Related
- 2000-11-28 JP JP2001549203A patent/JP4219106B2/ja not_active Expired - Fee Related
- 2000-12-19 TW TW089127214A patent/TW484065B/zh not_active IP Right Cessation
-
2003
- 2003-09-23 US US10/667,457 patent/US7143242B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101539896A (zh) | 2009-09-23 |
| AU1793701A (en) | 2001-07-09 |
| CN101520759B (zh) | 2011-12-28 |
| CN1503947A (zh) | 2004-06-09 |
| DE60026068T2 (de) | 2006-11-02 |
| WO2001048618A2 (en) | 2001-07-05 |
| US7143242B2 (en) | 2006-11-28 |
| CN100492332C (zh) | 2009-05-27 |
| US6654837B1 (en) | 2003-11-25 |
| WO2001048618A3 (en) | 2002-03-07 |
| ATE317991T1 (de) | 2006-03-15 |
| CN101520759A (zh) | 2009-09-02 |
| MXPA02005822A (es) | 2003-12-11 |
| EP1624379A2 (en) | 2006-02-08 |
| JP2003521029A (ja) | 2003-07-08 |
| EP1323045B1 (en) | 2006-02-15 |
| DE60039375D1 (de) | 2008-08-14 |
| EP1323045A2 (en) | 2003-07-02 |
| DE60026068D1 (de) | 2006-04-20 |
| TW484065B (en) | 2002-04-21 |
| US20040059854A1 (en) | 2004-03-25 |
| HK1066610A1 (zh) | 2005-03-24 |
| EP1624379A3 (en) | 2006-04-26 |
| EP1624379B1 (en) | 2008-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4219106B2 (ja) | 動的優先順位外部トランザクション・システム | |
| US7487305B2 (en) | Prioritized bus request scheduling mechanism for processing devices | |
| US9727469B2 (en) | Performance-driven cache line memory access | |
| US8131948B2 (en) | Snoop request arbitration in a data processing system | |
| US8255591B2 (en) | Method and system for managing cache injection in a multiprocessor system | |
| US20100057998A1 (en) | Snoop request arbitration in a data processing system | |
| US7058767B2 (en) | Adaptive memory access speculation | |
| US6928525B1 (en) | Per cache line semaphore for cache access arbitration | |
| US6553473B1 (en) | Byte-wise tracking on write allocate | |
| US6467032B1 (en) | Controlled reissue delay of memory requests to reduce shared memory address contention | |
| US20030105929A1 (en) | Cache status data structure | |
| US7330940B2 (en) | Method and system for cache utilization by limiting prefetch requests | |
| US7340542B2 (en) | Data processing system with bus access retraction | |
| EP1622029A2 (en) | Memory control device, move-in buffer control method | |
| US7130943B2 (en) | Data processing system with bus access retraction | |
| HK1066610B (en) | Dynamic priority external transaction system | |
| US20060174062A1 (en) | Method and system for cache utilization by limiting number of pending cache line requests | |
| JPH0773035A (ja) | 複数プロセツサ・システム |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040401 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040401 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080129 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20080430 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20080509 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20080529 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20080605 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080630 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20081104 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081111 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111121 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111121 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121121 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121121 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131121 Year of fee payment: 5 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |