JP4218073B2

JP4218073B2 - Semiconductor resistance element

Info

Publication number: JP4218073B2
Application number: JP00903598A
Authority: JP
Inventors: 努井本; 信一斉木
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1998-01-20
Filing date: 1998-01-20
Publication date: 2009-02-04
Anticipated expiration: 2018-01-20
Also published as: JPH11214616A

Description

【０００１】
【発明の属する技術分野】
本発明は、例えばＧａＡｓ基板等の半絶縁性基板の電位変動の影響を受けにくい構成の半導体抵抗素子に関する。
【０００２】
【従来の技術】
従来、半導体基板内の表面側に不純物を導入して形成される抵抗素子は、半導体集積回路の構成要素として、広く利用されている抵抗素子の一形態である。
【０００３】
図４には、従来から用いられている抵抗素子の一例として、ＧａＡｓ半絶縁性基板に形成された抵抗素子の断面構造を示す。
図４において、符号１０２はＧａＡｓ基板、１０４は基板内の表面側に例えばＳｉ等のｎ型不純物を導入して形成された抵抗素子の不純物領域（以下、抵抗不純物領域）、１０５は抵抗不純物領域と基板領域界面に形成された空乏層、１０６は基板及び抵抗不純物領域上に成膜された例えばＳｉＮ等の絶縁膜、１０８は抵抗不純物領域に対し低抵抗で接触するオーミック電極、１１０はオーミック電極上に接触する抵抗素子の金属配線である。
【０００４】
このような構造の抵抗素子を形成するには、まず、用意した半絶縁性のＧａＡｓ基板に、所定の条件でｎ型不純物（Ｓｉ）を例えばイオン注入法，熱拡散法に等により導入し、抵抗不純物領域１０４を形成する。全面にＳｉＮ等の絶縁膜１０６をＣＶＤ法等で成膜した後、オーミック電極の形成部分で開孔するレジストパターンを形成し、これをマスクにオーミック電極の形成部分に絶縁膜１０６の開口部を形成する。続いて、形成したレジストパターン上に例えばＡｕＧｅ／Ｎｉ等の積層金属を蒸着し、これをレジストパターンごと除去（リフトオフ）した後、加熱して合金化することにより、オーミック電極１０８を絶縁膜１０６の開口部に埋め込んで形成する。その後、全面に例えばＴｉ／Ｐｔ／Ａｕ等の配線材料を蒸着し、例えばイオンミリング法でパターンニングして、金属配線１１０を形成する。
【０００５】
本製造方法では、抵抗不純物領域１０４を形成する際の濃度プロファイル（濃度分布及び深さ等）を制御することにより、所望の抵抗値の抵抗素子を得る。
【０００６】
【発明が解決しようとする課題】
しかしながら、この従来の素子構造では、高抵抗を小面積で実現しようとして抵抗不純物領域１０４の形成時にＳｉ等のｎ型不純物濃度を低くすると、抵抗不純物領域１０４の電気抵抗が、基板電位によって大きく変化してしまうという不都合が生じる。この現象は、いわゆるバックゲート効果によるものとされ、この効果は、例えば『H.Goronkin,et.al, “Backgating and light sensitivity in ion-implantated GaAs integratedcircuits ”,IEEE Tran.ED-29(5),pp.845-850(1982)』、或いは『“GaAs DEVICES AND CIRCUITS (p.324) ”,Michael SHUR, PLENUM PRESS 』等に記載されている。
【０００７】
図５は、抵抗不純物領域に対するバックゲート効果の影響を調べた測定例であり、図５（ａ）が試料構成、測定方法を示すバイアス設定時の試料断面図である。
この測定用試料１２０の作製にあたっては、ＧａＡｓ基板１２２内の表面側に、イオン注入によりＳｉ不純物を所定濃度で導入して、抵抗不純物領域１２４と、基板電圧を変化させるための不純物領域１２６とを離間して同時に形成した。その上に絶縁膜１２８を成膜し、これに開口部を設け、抵抗不純物領域１２４上で測定端子をなす２つのオーミック電極１３０，１３２と不純物領域１２６上に基板電圧の印加端子をなすオーミック電極１３６とを、リフトオフ法で一括形成した。
【０００８】
図５（ｂ）に、測定結果（抵抗素子のＩ−Ｖ特性）を示す。
この測定では、まず、基板１２２を接地した状態で、電極１３０をプラス、電極１３２をマイナスにして抵抗素子の印加電圧ＶＨを徐々に大きくしていったときに、端子間に流れる素子電流ＩＨをパラメータアナライザを用いて測定した。また、基板に負の電圧（−Ｖ_SUB）を印加し、その電圧値Ｖ_SUBを２Ｖ，４Ｖ，６Ｖと大きくしていったときに、それぞれの基板電圧において上記と同様な測定を繰り返し行った。
この結果、基板電位を負側に振ると、抵抗不純物領域１２４の電気抵抗が増大し、飽和電流が次第に減少して殆ど流れなくなり、あたかも基板１２２がゲートとして作用するＦＥＴのドレイン電圧電流特性の如き特性が得られた。これは、基板１２２が半絶縁性とはいえ若干の電位変動があり、その電位変動による抵抗不純物領域への影響（抵抗値変動）が意外に大きいことを示すものである。かかる抵抗変動は、基板１２２の印加電圧が負に大きくなるにしたがって、空間電荷領域（先の図４に示す空乏層）が抵抗不純物領域内に拡がり、その電流チャネルを狭めて電流に寄与するシートシャリア濃度を減少させるために起こると解される。
【０００９】
この実験から容易に推測できるように、実際のＧａＡｓ集積回路における抵抗素子は、その抵抗値が基板電位に応じて数桁のオーダで変動する。したがって、この基板電位による抵抗値変化は、例えばＤＣＦＬ型ロジックゲートのプルアップ抵抗値を変動させ、ノイズマージンを減少させることによって、回路の誤動作を招く要因ともなっていた。
この従来の抵抗素子を有する集積回路の誤動作を防止するには、基板電位を制御して所望の抵抗値を維持しなければならない。しかし、抵抗素子の抵抗値に大きく影響する基板電位は、同じ基板内に近接して作られた周辺素子の影響、例えば近接するＦＥＴのソース・ドレイン電圧や、ＦＥＴから基板に注入された正孔の量等の種々の要因が総合して決まり、回路の動作状態に応じて複雑に変動していることから、この基板電位を予測し制御することは困難である。
【００１０】
本発明は、このような実情に鑑みてなされ、半絶縁性基板に作られ基板電位の影響を受けにくい構成とした半導体抵抗素子を提供することを目的とする。
【００１１】
【課題を解決するための手段】
上述した従来技術の問題点を解決し、上記目的を達成するために、本発明の半導体抵抗素子は、半絶縁性の半導体基板と、当該半導体基板内の表面側に形成され、２つの第１コンタクトを有し、当該２つの第１コンタクト間で抵抗素子の抵抗値を決める第１導電型の抵抗不純物領域と、を有する半導体抵抗素子であって、前記半導体基板の基板領域と前記抵抗不純物領域との間に、第２導電型を有し、第２コンタクトを介して所定電位に保持された抵抗素子専用の埋め込み不純物領域が設けられ、前記２つの第１コンタクトのうち、前記埋め込み不純物領域に前記所定電位を与える前記第２コンタクトに近い方の第１コンタクトが、前記所定電位で保持されている。
この埋め込み不純物領域は、好ましくは、前記所定電位を印加していない状態で全て空乏化しない基板深さ方向の幅を有する。
また、抵抗不純物領域上には、好ましくは、所定間隔で２つのオーミック電極と、当該２つのオーミック電極上のそれぞれに接触する配線層とが設けられ、埋め込み不純物領域の一方端には、オーミック電極を介して前記所定電位を付与する電位供給配線層が設けられている。
【００１２】
この半導体抵抗素子では、抵抗不純物領域と基板領域との間には、固定電位の埋め込み不純物領域が設けられ、しかも好適には、この埋め込み不純物領域が厚さ方向全てが空乏化しないことから、抵抗不純物領域は、半導体基板の電位変動の影響を殆ど受けない。このため、抵抗不純物領域の濃度を低くして高抵抗化した場合であっても、抵抗値が変動するようなことがない。
【００１３】
【発明の実施の形態】
以下、本発明に係る半導体抵抗素子の実施形態を、ＧａＡｓＪＦＥＴを基本素子とする場合を例に図面を参照しながら詳細に説明する。
【００１４】
図１（ａ）は本発明の実施形態に係る半導体抵抗素子の概略平面図である。また、図１（ｂ）は図１（ａ）のＡ−Ａ’線に沿った断面図である。
図１において、符号１は半導体抵抗素子、２は半絶縁性基板、例えばＧａＡｓ基板を示す。
半絶縁性ＧａＡｓ基板２内の表面側に、本実施形態では、例えばマグネシウム（Ｍｇ）が導入されたｐ型の埋め込み不純物領域４が形成され、その埋め込み不純物領域４内の表面側に抵抗素子１のｎ型不純物領域（抵抗不純物領域６）が形成されている。埋め込み不純物領域４は、当該抵抗不純物領域６の基板変調を防ぐために設けたものである。埋め込み不純物領域４は、望ましくは、少なくとも埋め込み不純物領域４に電圧を印加しないときに基板深さ方向が全て空乏化しない程度に、ある程度大きな厚みを有する。埋め込み不純物領域４は、抵抗不純物領域６と逆導電型であればよく、逆に埋め込み不純物領域４がｎ型、抵抗不純物領域６がｐ型でもよい。
【００１５】
この各種不純物領域が形成された基板上には、絶縁膜８が成膜されている。この絶縁膜８には、抵抗不純物領域６上で所定間隔で開口する２つの開孔部８ａと８ｂと、埋め込み不純物領域４の一方端部上で開口する開孔部８ｃとが設けられている。抵抗不純物領域６上の２つの開孔部８ａ，８ｂ内に、それぞれオーミック電極１０，１２が埋め込まれ、また埋め込み不純物領域４上の開孔部８ｃには、オーミック電極１４が埋め込まれている。これらのオーミック電極１０，１２，１４は、例えばＡｕＧｅ／Ｎｉの積層金属を下地のＧａＡｓと合金化したもの等、コンタクト抵抗が低い材料から構成されている。
【００１６】
抵抗不純物領域６上の２つのオーミック電極１０，１２上にそれぞれ接する配線層１６，１８が、絶縁膜８上を抵抗不純物領域６上から、その外側に向けて配線されている。また、埋め込み不純物領域４上のオーミック電極１４上に接する電位供給配線層２０が、絶縁膜８上に配線されている。これらの配線層１６，１８，２０は、Ｔｉ／Ａｕ，Ｔｉ／Ｐｔ／ＡｕのＡｕ系の積層金属或いはＡｌ等からなる。
【００１７】
このような構成の半導体抵抗素子１では、抵抗不純物領域６と基板領域との間には、固定電位の埋め込み不純物領域４が設けられ、しかも好適には、この埋め込み不純物領域が厚さ方向全てが空乏化しないことから、抵抗不純物領域６は、半導体基板の電位変動の影響を殆ど受けない。このため、本実施形態の半導体抵抗素子１は、抵抗不純物領域６の濃度を低くして高抵抗化した場合であっても、抵抗値が変動するようなことがないという利点がある。
半導体集積回路内で他の素子とともに単一の基板に集積化された抵抗素子において、その誤動作防止に上記利点が特に有効である。なぜなら、半導体集積回路ではＦＥＴ等を含む抵抗素子周囲の素子の影響、例えばＦＥＴのソースまたはドレイン不純物領域への印加電圧値、或いは当該電圧印加による基板への正孔注入等の影響で基板電位が変化することがあるが、本実施形態では上記理由により素子抵抗値が殆ど変動しないからである。
【００１８】
つぎに、この図１に示す半導体抵抗素子の製造方法を説明する。
【００１９】
図２及び図３は、図１に示す半導体抵抗素子の各製造過程を示す断面図である。
図２（ａ）では、まず、半絶縁性の半導体基板２として、例えば半絶縁性ＬＥＣ−ＧａＡｓ基板（主面方位（１００））を用意し、この半絶縁性の半導体基板２の主面に、例えばプラズマＣＶＤ法によりキャップ層３を形成する。このキャップ層３は、例えば窒化シリコン（ＳｉＮ）或いは酸化シリコン（ＳｉＯ₂）から構成され、膜厚が例えば５０ｎｍ程度で形成される。次いで、抵抗を形成する部分で開口するレジストパターン５を、光学リソグラフィ技術を用いて形成する。このレジストパターン５をマスクに、キャップ層３をスルー膜として例えばＳｉ等のｎ型不純物を基板内表面側にイオン注入する。これにより、レジストパターン５の開口部５ａに応じた基板領域に、所定の濃度プロファイルで抵抗不純物領域６が形成される。イオン注入条件は、注入エネルギーを例えば１２０ＫｅＶとし、ドーズ量を例えば１×１０¹³／ｃｍ²とする。
【００２０】
レジストパターン５を除去した後、続く図２（ｂ）では、抵抗不純物領域６より広い開口部７ａを有するレジストパターン７を、光学リソグラフィ技術を用いてキャップ層３上に形成する。このレジストパターン７をマスクに、キャップ層３をスルー膜として例えばＭｇ等のｐ型不純物を基板内表面側にイオン注入する。このときのイオン注入は、ｐ型不純物領域が抵抗不純物領域６より深くに、また周囲を囲んで基板領域との間に介在し、かつ抵抗不純物領域６のｎ型不純物濃度が所定値となるような条件で行う。例えば、注入エネルギーを先程より高い２４０ＫｅＶとし、ドース量を先程より低い５×１０¹²／ｃｍ²程度とする。これにより、レジストパターン７の開口部７ａに応じた面積で抵抗不純物領域６周囲の基板領域との間に、所定の濃度プロファイルの埋め込み不純物領域４が形成される。
【００２１】
図２（ｃ）では、キャップ層３が酸化シリコン系の膜である場合は例えばフッ酸（ＨＦ）を含む所定のエッチング溶液等を用いて、キャップ層３を除去する。このキャップレスの状態で、基板全体を例えば所定圧の水素化砒素（ＡｓＨ₃）中で８５０℃でアニールし、導入不純物を活性化させる。
【００２２】
図２（ｄ）に示すように、プラズマＣＶＤ法等を用いて、例えばＳｉＮからなる絶縁膜８を全面に３００ｎｍほど堆積する。
続いて、図３（ｅ）に示すように、絶縁膜８上に、所定のオーミック電極形成部分で開口するレジストパターン９を、通常のフォトリソグラフィ技術を用いて形成する。このレジストパターン９をマスクに、下地の絶縁膜８をエッチングし、抵抗不純物領域６の両端部を表出させる開孔部８ａと８ｂ、埋め込み不純物領域４の一方端を表出させる開孔部８ｃを同時形成する。ここで、この絶縁膜のエッチングは、例えば、ＣＦ₄／Ｈ₂を反応ガスとするＲＩＥ等で行う。
【００２３】
レジストパターン９をつけたまま、図３（ｆ）に示すように、全面にオーミック電極材料となる金属薄膜１１を成膜する。この金属薄膜１１の成膜では、抵抗加熱蒸着法等により、例えばＡｕＧｅ合金とＮｉの２層膜を連続蒸着する。これにより、絶縁膜８の開孔部８ａ，８ｂ，８ｃが、それぞれ孤立した金属薄膜１０ａ，１２ａ，１４ａによって埋め込まれる。
【００２４】
金属薄膜１０ａ，１２ａ，１４ａ以外の殆どの金属薄膜１１はレジストパターン９の上に残るが、図３（ｇ）においては、まず、この不要な部分をリフトオフ法によって除去する。すなわち、蒸着後の基板を、例えばアセトン等のレジスト溶解液に浸すと、レジストの溶解とともにレジストパターン９上の不要な金属薄膜１１は剥離される。その後、所定の合金化加熱処理を行うことによって、残された金属薄膜１０ａ，１２ａ，１４ａがＧａＡｓ基板と合金化し、低抵抗なオーミック電極１０，１２，１４が形成される。続いて、このオーミック電極及び絶縁膜８上の全面に、配線材料として金属膜１５を成膜し、その上にフォトリソグラフィ法によってレジストパターン１７を形成する。金属膜１５は、例えば、Ｔｉ／Ｐｔ／Ａｕの３層膜とし、膜厚は、ＴｉおよびＰｔが５０ｎｍでＡｕが１２０ｎｍ程度とする。
【００２５】
図３（ｈ）では、このレジストパターン１７で被膜されていない金属膜部分をエッチング除去して、金属配線のパターンニングを行う。金属膜１５がＡｕ系の場合、このパターンニングはイオンミリング法が用いられる。これにより、抵抗素子の２つのオーミック電極１０，１２にそれぞれ接続された抵抗素子用の配線層１６，１８と、埋め込み不純物領域４上のオーミック電極１４に接続された電位供給配線層２０とが形成される。エッチング後は、レジストパターン１７を除去して、図１に示す本実施形態の抵抗素子を完成させる。
【００２６】
本実施形態の半導体抵抗素子では、埋め込み不純物領域４を抵抗不純物領域６の周囲に設けこれを所定電位で保持するが、その電位供給手段として、オーミック電極１４と電位供給配線層２０が用いられる。これらの固定電位供給用の電極と配線層は、抵抗素子の電極１０，１２または配線層１６，１８と同時形成されることから、従来の製造方法に比べ、埋め込み不純物領域４の形成のためのレジストパターン７の形成とイオン注入（図２（ｂ））の工程増加で済み、比較的に製造工程が簡素である。
【００２７】
最後に、本実施形態の半導体抵抗素子１の集積回路等における使用方法について簡単に述べる。
第１の使用例は、埋め込み不純物領域４の電位を接地電位（０Ｖ）に固定することである。本実施形態の抵抗素子を集積回路用として用いた場合、基板電位は抵抗素子周囲の状況、例えば、図示しないトランジスタのソース又はドレイン不純物領域の電位、このような不純物領域からの正孔の注入等によって、０Ｖから電源電圧Ｖ_DDの範囲で種々変化し得る。埋め込み不純物領域４を接地電位に固定すると、抵抗不純物領域６について、その両端に印加される電位に対して、常に、同じ抵抗値が再現され、当該抵抗素子１を基本構成素子として用いる半導体集積回路の誤動作を有効に防止することができる。
【００２８】
第２の使用例は、埋め込み不純物領域６を電源電圧Ｖ_DDに固定することである。この場合、抵抗の端子電圧が電源電圧Ｖ_DDよりある程度下がると、埋め込み不純物領域６と抵抗不純物領域４によるｐｎ接合が順方向にバイアスされ、抵抗値が若干下がることがある。これは、前述とは逆向きのバックゲート効果によるものである。ｐｎ接合が順方向にバイアスされると、抵抗不純物領域４と埋め込み不純物領域６との間で空乏化していた領域が導電層になる過程で小さくなる或いは空乏化領域がなくなり、抵抗素子を流れる電流に寄与できるキャリア数が増えるために、抵抗値が下がることがある。ところが、埋め込み不純物領域４の電位は固定されているため、この抵抗値の低下の程度は予測できて再現性がある。また、このときの抵抗値の変動（低下）は、従来の基板電位の変動による抵抗値変動に比べ桁違いに小さい。従って、従来のような予測不可能な抵抗値の変動を防止することに対し、埋め込み不純物領域４を電源電圧Ｖ_DDに固定する本第２の使用例は有効である。
なお、抵抗の端子電圧が電源電圧Ｖ_DDより更に低下すると、両不純物領域４，６によるｐｎ接合で順方向電流が流れることが原理的には予想できるが、通常、抵抗不純物領域６の濃度は埋め込み不純物領域４の濃度より高いため、抵抗不純物領域６にのみ電流が流れる。ただし、抵抗に急激に大きな電流が流れると、このｐｎ接合に順方向電流が流れることも否定できないので、電源電圧Ｖ_DDで保持されている電位供給配線層２０に近い抵抗端子（配線層１６）は高い電圧（例えば、同じ電源電圧Ｖ_DD）で保持し、電位供給配線層２０に遠い抵抗端子（配線層１８）を、例えば０Ｖから電源電圧Ｖ_DDまで変化させる使用方法が望ましい。配線層１６を電源電圧Ｖ_DDで保持するとすれば、一般には、この配線層１６と固定電位供給層２０を短絡して使用する。
【００２９】
【発明の効果】
本発明に係る半導体抵抗素子によれば、抵抗不純物領域周囲の基板領域との間に逆導電型の埋め込み不純物領域が介在し、これが所定の電位で保持されているので、基板電位変動の影響を受けて抵抗不純物領域の電流チャネル抵抗（又はシート抵抗）が変動することがないので、当該抵抗素子の抵抗値を一定にできる。とくに、本発明の半導体抵抗素子は、周囲にトランジスタ等が集積されて基板変動が発生しやすい半導体集積回路の基本抵抗素子として好適である。この意味では、本発明によって、抵抗値変動による回路誤動作をひき起こし難い動作信頼性が高い集積回路用の半導体抵抗素子を実現することが可能となる。
【図面の簡単な説明】
【図１】本発明の実施形態に係る半導体抵抗素子の概略平面図と、平面図のＡ−Ａ’線に沿った各断面図である。
【図２】図１に示す半導体抵抗素子の各製造過程を示す断面図であり、各不純物領域形成後の絶縁膜形成までを示す。
【図３】図２に続く同断面図であり、最終工程の配線層形成までを示す。
【図４】従来から用いられている半導体抵抗素子の構造例を示す断面図である。
【図５】解決課題で述べた抵抗不純物領域に対するバックゲート効果の影響を調べた測定試料の断面図と、測定結果（抵抗素子のＩ−Ｖ特性）を示すグラフである。
【符号の説明】
１…半導体抵抗素子、２…絶縁性半導体基板、４…埋め込み不純物領域、５，７，９，１７…レジストパターン、６…抵抗不純物領域、８…絶縁膜、８ａ〜８ｃ…開孔部、１０，１２，１４…オーミック電極、１０ａ，１２ａ，１４ａ，１１…オーミック電極合金化前の金属薄膜、１５…金属膜、１６，１８…抵抗素子の配線層、２０…電位供給配線層。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor resistance element having a configuration that is not easily affected by potential fluctuations of a semi-insulating substrate such as a GaAs substrate.
[0002]
[Prior art]
Conventionally, a resistance element formed by introducing impurities into the surface side in a semiconductor substrate is one form of a resistance element that is widely used as a component of a semiconductor integrated circuit.
[0003]
FIG. 4 shows a cross-sectional structure of a resistance element formed on a GaAs semi-insulating substrate as an example of a resistance element conventionally used.
In FIG. 4, reference numeral 102 denotes a GaAs substrate, 104 denotes an impurity region (hereinafter referred to as a resistance impurity region) of a resistance element formed by introducing an n-type impurity such as Si on the surface side in the substrate, and 105 denotes a resistance impurity region. , A depletion layer formed at the substrate region interface, 106 an insulating film such as SiN formed on the substrate and the resistive impurity region, 108 an ohmic electrode that contacts the resistive impurity region with low resistance, and 110 an ohmic electrode It is the metal wiring of the resistance element that contacts the top.
[0004]
In order to form a resistance element having such a structure, first, an n-type impurity (Si) is introduced into a prepared semi-insulating GaAs substrate under predetermined conditions by, for example, an ion implantation method or a thermal diffusion method, Resistive impurity region 104 is formed. After an insulating film 106 such as SiN is formed on the entire surface by a CVD method or the like, a resist pattern is formed that opens at the ohmic electrode forming portion. Using this as a mask, the opening of the insulating film 106 is formed at the ohmic electrode forming portion. Form. Subsequently, a laminated metal such as AuGe / Ni is vapor-deposited on the formed resist pattern, and the resist pattern is removed (lifted off) together with the resist pattern. Then, the ohmic electrode 108 is formed on the insulating film 106 by heating and alloying. It is formed by being embedded in the opening. Thereafter, a wiring material such as Ti / Pt / Au is vapor-deposited on the entire surface and patterned by, for example, an ion milling method to form the metal wiring 110.
[0005]
In this manufacturing method, a resistance element having a desired resistance value is obtained by controlling a concentration profile (concentration distribution, depth, etc.) when the resistance impurity region 104 is formed.
[0006]
[Problems to be solved by the invention]
However, in this conventional element structure, if the n-type impurity concentration of Si or the like is reduced when forming the resistive impurity region 104 in order to achieve high resistance in a small area, the electrical resistance of the resistive impurity region 104 varies greatly depending on the substrate potential. Inconvenience occurs. This phenomenon is considered to be due to the so-called back gate effect, which is described in, for example, “H. Goronkin, et.al,“ Backgating and light sensitivity in ion-implantated GaAs integrated circuits ””, IEEE Tran. ED-29 (5), pp.845-850 (1982) ”or“ “GaAs DEVICES AND CIRCUITS (p.324)”, Michael SHUR, PLENUM PRESS ”.
[0007]
FIG. 5 is a measurement example in which the influence of the back gate effect on the resistance impurity region is examined, and FIG. 5A is a sample cross-sectional view at the time of bias setting showing a sample configuration and a measurement method.
In producing the measurement sample 120, a Si impurity is introduced at a predetermined concentration into the surface side of the GaAs substrate 122 by ion implantation to form a resistance impurity region 124 and an impurity region 126 for changing the substrate voltage. Separated and formed simultaneously. An insulating film 128 is formed thereon, an opening is provided in the insulating film 128, and two ohmic electrodes 130 and 132 that form measurement terminals on the resistive impurity region 124 and an ohmic electrode that forms a substrate voltage application terminal on the impurity region 126. 136 were formed together by a lift-off method.
[0008]
FIG. 5B shows measurement results (IV characteristics of the resistance element).
In this measurement, first, with the substrate 122 grounded, when the electrode 130 is positive and the electrode 132 is negative and the applied voltage VH of the resistance element is gradually increased, the element current IH flowing between the terminals is obtained. Measurement was performed using a parameter analyzer. Further, when a negative voltage (−V _SUB ) was applied to the substrate and the voltage value V _SUB was increased to 2V, 4V, and 6V, the same measurement as described above was repeatedly performed at each substrate voltage. .
As a result, when the substrate potential is shifted to the negative side, the electric resistance of the resistive impurity region 124 increases, the saturation current gradually decreases, and hardly flows, as if the drain voltage current characteristics of the FET in which the substrate 122 acts as a gate. Characteristics were obtained. This shows that although the substrate 122 is semi-insulating, there is a slight potential fluctuation, and the influence (resistance value fluctuation) on the resistance impurity region due to the potential fluctuation is surprisingly large. Such resistance fluctuation is caused by the fact that the space charge region (depletion layer shown in FIG. 4) spreads in the resistance impurity region as the applied voltage of the substrate 122 becomes negative, and the current channel is narrowed to contribute to the current. It is understood that this occurs to reduce the sharia concentration.
[0009]
As can be easily inferred from this experiment, the resistance value of the resistance element in an actual GaAs integrated circuit varies on the order of several digits according to the substrate potential. Therefore, the change in the resistance value due to the substrate potential causes a malfunction of the circuit by, for example, changing the pull-up resistance value of the DCFL type logic gate and reducing the noise margin.
In order to prevent the malfunction of the integrated circuit having the conventional resistance element, the substrate resistance must be controlled to maintain a desired resistance value. However, the substrate potential that greatly affects the resistance value of the resistance element is influenced by the peripheral elements that are formed in the same substrate, for example, the source / drain voltage of the adjacent FET, or the holes injected from the FET to the substrate. It is difficult to predict and control the substrate potential because various factors such as the amount of the substrate are determined comprehensively and fluctuate in a complicated manner depending on the operation state of the circuit.
[0010]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor resistance element that is formed on a semi-insulating substrate and has a configuration that is hardly affected by the substrate potential.
[0011]
[Means for Solving the Problems]
To solve the problems of the prior art described above, in order to achieve the above object, a semiconductor resistance element of the present invention includes a semi-insulating semiconductor substrate, is formed on the surface side in the semiconductor substrate, two first It has a contact, a semiconductor resistor having a resistance impurity region of the first conductivity type which determines the resistance value of the resistance element between the two first contact, the resistance impurity region and the substrate region of said semiconductor substrate Between them, a buried impurity region dedicated to a resistance element having a second conductivity type and held at a predetermined potential via a second contact is provided, and the buried impurity region of the two first contacts is provided in the buried impurity region. The first contact closer to the second contact for applying the predetermined potential is held at the predetermined potential .
This buried impurity region preferably has a width in the substrate depth direction that is not fully depleted when the predetermined potential is not applied.
Preferably, two ohmic electrodes and a wiring layer in contact with each of the two ohmic electrodes are provided on the resistive impurity region at a predetermined interval, and an ohmic electrode is provided at one end of the buried impurity region. A potential supply wiring layer for applying the predetermined potential is provided through the wiring.
[0012]
In this semiconductor resistance element, a buried impurity region having a fixed potential is provided between the resistive impurity region and the substrate region, and preferably, the buried impurity region is not depleted in the entire thickness direction. The impurity region is hardly affected by the potential fluctuation of the semiconductor substrate. For this reason, even when the resistance impurity region is reduced in concentration and increased in resistance, the resistance value does not fluctuate.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a semiconductor resistance element according to the present invention will be described in detail with reference to the drawings, taking as an example a case where a GaAs JFET is a basic element.
[0014]
FIG. 1A is a schematic plan view of a semiconductor resistance element according to an embodiment of the present invention. FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG.
In FIG. 1, reference numeral 1 denotes a semiconductor resistance element, and 2 denotes a semi-insulating substrate, for example, a GaAs substrate.
In this embodiment, a p-type buried impurity region 4 into which, for example, magnesium (Mg) is introduced is formed on the surface side in the semi-insulating GaAs substrate 2, and the resistance element 1 is formed on the surface side in the buried impurity region 4. N-type impurity region (resistive impurity region 6) is formed. The buried impurity region 4 is provided to prevent substrate modulation of the resistive impurity region 6. The buried impurity region 4 desirably has a certain thickness so that at least the substrate depth direction is not depleted when no voltage is applied to the buried impurity region 4. The buried impurity region 4 only needs to have a conductivity type opposite to that of the resistive impurity region 6. Conversely, the buried impurity region 4 may be n-type and the resistive impurity region 6 may be p-type.
[0015]
An insulating film 8 is formed on the substrate on which the various impurity regions are formed. The insulating film 8 is provided with two openings 8 a and 8 b that open at a predetermined interval on the resistive impurity region 6 and an opening 8 c that opens on one end of the buried impurity region 4. . The ohmic electrodes 10 and 12 are embedded in the two opening portions 8 a and 8 b on the resistive impurity region 6, respectively, and the ohmic electrode 14 is embedded in the opening portion 8 c on the embedded impurity region 4. These ohmic electrodes 10, 12, and 14 are made of a material having a low contact resistance, such as an alloy of AuGe / Ni laminated metal and an underlying GaAs.
[0016]
Wiring layers 16 and 18 in contact with the two ohmic electrodes 10 and 12 on the resistive impurity region 6 are wired on the insulating film 8 from the resistive impurity region 6 to the outside . A potential supply wiring layer 20 in contact with the ohmic electrode 14 on the buried impurity region 4 is wired on the insulating film 8. These wiring layers 16, 18, and 20 are made of an Au-based laminated metal of Ti / Au, Ti / Pt / Au, Al, or the like.
[0017]
In the semiconductor resistance element 1 having such a configuration, the buried impurity region 4 having a fixed potential is provided between the resistive impurity region 6 and the substrate region, and preferably, the buried impurity region is entirely in the thickness direction. Since it is not depleted, the resistive impurity region 6 is hardly affected by the potential fluctuation of the semiconductor substrate. For this reason, the semiconductor resistance element 1 of the present embodiment has an advantage that the resistance value does not fluctuate even when the resistance impurity region 6 is reduced in concentration and increased in resistance.
In the resistance element integrated on a single substrate together with other elements in the semiconductor integrated circuit, the above advantages are particularly effective for preventing malfunction. This is because, in a semiconductor integrated circuit, the substrate potential is affected by the influence of an element around a resistance element including an FET, for example, the applied voltage value to the source or drain impurity region of the FET or the influence of hole injection to the substrate due to the voltage application. This is because the element resistance value hardly fluctuates in the present embodiment for the above reason.
[0018]
Next, a method for manufacturing the semiconductor resistance element shown in FIG. 1 will be described.
[0019]
2 and 3 are cross-sectional views showing respective manufacturing processes of the semiconductor resistance element shown in FIG.
In FIG. 2A, first, as a semi-insulating semiconductor substrate 2, for example, a semi-insulating LEC-GaAs substrate (main surface orientation (100)) is prepared, and the semi-insulating semiconductor substrate 2 is formed on the main surface. For example, the cap layer 3 is formed by a plasma CVD method. The cap layer 3 is made of, for example, silicon nitride (SiN) or silicon oxide (SiO ₂ ) and has a film thickness of, for example, about 50 nm. Next, a resist pattern 5 having an opening at a portion where a resistor is to be formed is formed using an optical lithography technique. With this resist pattern 5 as a mask, an n-type impurity such as Si is ion-implanted into the substrate inner surface side using the cap layer 3 as a through film. Thereby, the resistance impurity region 6 is formed in the substrate region corresponding to the opening 5a of the resist pattern 5 with a predetermined concentration profile. The ion implantation conditions are, for example, an implantation energy of 120 KeV and a dose of 1 × 10 ¹³ / cm ² , for example.
[0020]
After removing the resist pattern 5, in FIG. 2B, a resist pattern 7 having an opening 7a wider than the resistive impurity region 6 is formed on the cap layer 3 using an optical lithography technique. Using this resist pattern 7 as a mask, p-type impurities such as Mg are ion-implanted into the substrate inner surface side using the cap layer 3 as a through film. The ion implantation at this time is such that the p-type impurity region is deeper than the resistive impurity region 6 and is surrounded by the substrate region and the n-type impurity concentration of the resistive impurity region 6 becomes a predetermined value. Perform under appropriate conditions. For example, the implantation energy is 240 KeV, which is higher than the previous one, and the dose amount is about 5 × 10 ¹² / cm ² which is lower than the previous one. As a result, a buried impurity region 4 having a predetermined concentration profile is formed between the resist pattern 7 and the substrate region around the resistive impurity region 6 in an area corresponding to the opening 7a.
[0021]
In FIG. 2C, when the cap layer 3 is a silicon oxide film, the cap layer 3 is removed using, for example, a predetermined etching solution containing hydrofluoric acid (HF). In this capless state, the entire substrate is annealed at, for example, 850 ° C. in arsenic hydride (AsH ₃ ) at a predetermined pressure to activate the introduced impurities.
[0022]
As shown in FIG. 2D, an insulating film 8 made of, for example, SiN is deposited on the entire surface by about 300 nm using a plasma CVD method or the like.
Subsequently, as shown in FIG. 3E, a resist pattern 9 having an opening at a predetermined ohmic electrode formation portion is formed on the insulating film 8 by using a normal photolithography technique. Using this resist pattern 9 as a mask, the underlying insulating film 8 is etched to open the openings 8 a and 8 b that expose both ends of the resistive impurity region 6, and the opening 8 c that exposes one end of the buried impurity region 4. Are formed simultaneously. Here, the etching of the insulating film is performed by, for example, RIE using CF ₄ / H ₂ as a reaction gas.
[0023]
With the resist pattern 9 attached, a metal thin film 11 serving as an ohmic electrode material is formed on the entire surface as shown in FIG. In forming the metal thin film 11, for example, a two-layer film of AuGe alloy and Ni is continuously vapor-deposited by a resistance heating vapor deposition method or the like. Thereby, the opening portions 8a, 8b, and 8c of the insulating film 8 are filled with the isolated metal thin films 10a, 12a, and 14a, respectively.
[0024]
Although most of the metal thin film 11 other than the metal thin films 10a, 12a, and 14a remains on the resist pattern 9, in FIG. 3G, this unnecessary portion is first removed by a lift-off method. That is, when the deposited substrate is immersed in a resist solution such as acetone, unnecessary metal thin film 11 on resist pattern 9 is peeled off with the dissolution of the resist. Thereafter, by performing a predetermined alloying heat treatment, the remaining metal thin films 10a, 12a, and 14a are alloyed with a GaAs substrate, and low-resistance ohmic electrodes 10, 12, and 14 are formed. Subsequently, a metal film 15 is formed as a wiring material on the entire surface of the ohmic electrode and the insulating film 8, and a resist pattern 17 is formed thereon by photolithography. The metal film 15 is, for example, a three-layer film of Ti / Pt / Au, and the film thickness is about 50 nm for Ti and Pt and about 120 nm for Au.
[0025]
In FIG. 3H, the metal film portion not covered with the resist pattern 17 is removed by etching, and the metal wiring is patterned. When the metal film 15 is Au-based, ion milling is used for this patterning. As a result, the resistance element wiring layers 16 and 18 connected to the two ohmic electrodes 10 and 12 of the resistance element, respectively, and the potential supply wiring layer 20 connected to the ohmic electrode 14 on the embedded impurity region 4 are formed. Is done. After etching, the resist pattern 17 is removed to complete the resistance element of this embodiment shown in FIG.
[0026]
In the semiconductor resistance element of the present embodiment, the buried impurity region 4 is provided around the resistive impurity region 6 and held at a predetermined potential. The ohmic electrode 14 and the potential supply wiring layer 20 are used as the potential supply means. These fixed potential supply electrodes and wiring layers are formed at the same time as the electrodes 10 and 12 of the resistance elements or the wiring layers 16 and 18, so that compared to the conventional manufacturing method, the electrodes for forming the buried impurity region 4 are formed. The formation of the resist pattern 7 and ion implantation (FIG. 2B) need only be increased, and the manufacturing process is relatively simple.
[0027]
Finally, a method of using the semiconductor resistance element 1 of this embodiment in an integrated circuit or the like will be briefly described.
The first use example is to fix the potential of the buried impurity region 4 to the ground potential (0 V). When the resistance element of this embodiment is used for an integrated circuit, the substrate potential is the situation around the resistance element, for example, the potential of a source or drain impurity region of a transistor (not shown), injection of holes from such an impurity region, etc. Can vary in a range from 0 V to the power supply voltage V _DD . When the buried impurity region 4 is fixed to the ground potential, the same resistance value is always reproduced for the potential applied to both ends of the resistive impurity region 6, and the semiconductor integrated circuit using the resistive element 1 as a basic constituent element. Can be effectively prevented.
[0028]
A second use example is to fix the buried impurity region 6 to the power supply voltage V _DD . In this case, when the terminal voltage of the resistor is lowered to some extent from the power supply voltage V _DD , the pn junction by the buried impurity region 6 and the resistive impurity region 4 is biased in the forward direction, and the resistance value may be slightly lowered. This is due to the back gate effect opposite to that described above. When the pn junction is biased in the forward direction, the current that flows through the resistance element becomes smaller or disappears in the process where the region depleted between the resistive impurity region 4 and the buried impurity region 6 becomes a conductive layer. As the number of carriers that can contribute to the increase increases, the resistance value may decrease. However, since the potential of the buried impurity region 4 is fixed, the degree of decrease in the resistance value can be predicted and is reproducible. Further, the resistance value variation (decrease) at this time is orders of magnitude smaller than the conventional resistance value variation due to the substrate potential variation. Therefore, the second usage example in which the buried impurity region 4 is fixed to the power supply voltage V _DD is effective for preventing the unpredictable fluctuation of the resistance value as in the prior art.
In principle, it can be predicted that when the terminal voltage of the resistor is lower than the power supply voltage V _DD , a forward current flows through the pn junction between the two impurity regions 4 and 6. Since the concentration is higher than that of the buried impurity region 4, a current flows only through the resistive impurity region 6. However, if a large current suddenly flows through the resistor, it cannot be denied that a forward current flows through the pn junction. Therefore, the resistance terminal (wiring layer 16) close to the potential supply wiring layer 20 held at the power supply voltage V _DD is used. Is preferably held at a high voltage (for example, the same power supply voltage V _DD ) and the resistance terminal (wiring layer 18) far from the potential supply wiring layer 20 is changed from, for example, 0 V to the power supply voltage V _DD . If the wiring layer 16 is held at the power supply voltage V _DD , the wiring layer 16 and the fixed potential supply layer 20 are generally used by short-circuiting.
[0029]
【The invention's effect】
According to the semiconductor resistance element of the present invention, the reverse conductivity type buried impurity region is interposed between the substrate region around the resistance impurity region, and this is held at a predetermined potential. As a result, the current channel resistance (or sheet resistance) of the resistive impurity region does not fluctuate, so that the resistance value of the resistance element can be made constant. In particular, the semiconductor resistance element of the present invention is suitable as a basic resistance element of a semiconductor integrated circuit in which transistors and the like are integrated around and the substrate is likely to change. In this sense, according to the present invention, it is possible to realize a semiconductor resistance element for an integrated circuit having high operation reliability that hardly causes a circuit malfunction due to a resistance value variation.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a semiconductor resistance element according to an embodiment of the present invention, and cross-sectional views taken along line AA ′ of the plan view.
2 is a cross-sectional view showing each manufacturing process of the semiconductor resistance element shown in FIG. 1, and shows the process up to formation of an insulating film after formation of each impurity region.
FIG. 3 is a cross-sectional view subsequent to FIG. 2, showing the final process until formation of a wiring layer;
FIG. 4 is a cross-sectional view showing an example of the structure of a semiconductor resistance element conventionally used.
FIGS. 5A and 5B are a cross-sectional view of a measurement sample in which the influence of the back gate effect on the resistive impurity region described in the problem to be solved and a graph showing a measurement result (IV characteristic of the resistance element). FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor resistance element, 2 ... Insulating semiconductor substrate, 4 ... Embedded impurity area | region, 5, 7, 9, 17 ... Resist pattern, 6 ... Resistance impurity area | region, 8 ... Insulating film, 8a-8c ... Opening part, 10 , 12, 14... Ohmic electrode, 10a, 12a, 14a, 11... Metal thin film before ohmic electrode alloying, 15... Metal film, 16, 18.

Claims

A semi-insulating semiconductor substrate;
A resistance impurity region of a first conductivity type formed on a surface side in the semiconductor substrate, having two first contacts, and determining a resistance value of a resistance element between the two first contacts ;
A semiconductor resistance element having
Between the substrate region of the semiconductor substrate and the resistive impurity region, there is provided a buried impurity region dedicated to a resistive element having a second conductivity type and held at a predetermined potential via a second contact ,
The semiconductor resistance element in which the first contact closer to the second contact that applies the predetermined potential to the buried impurity region among the two first contacts is held at the predetermined potential .

The semiconductor resistance element according to claim 1, wherein the buried impurity region has a width in a substrate depth direction that is not fully depleted in a state where the predetermined potential is not applied.

On the resistive impurity region , two ohmic electrodes at a predetermined interval and a wiring layer in contact with each of the two ohmic electrodes are provided,
The semiconductor resistance element according to claim 1, wherein a potential supply wiring layer for applying the predetermined potential is provided at one end of the buried impurity region through an ohmic electrode.

The semiconductor resistance element according to claim 1, wherein the predetermined potential is a ground potential.

The semiconductor resistance element according to claim 1, wherein the predetermined potential is a power supply potential.

The semiconductor resistance element according to claim 1, wherein the semiconductor substrate is a GaAs semi-insulating substrate.