JP4213999B2 - Digital transmission equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital transmission apparatus that visualizes a transmission state in a digital transmission apparatus.
[0002]
[Prior art]
In recent years, QAM (Quadrature Amplitude Modulation) and OFDM (Orthogonal Frequency Division Multiplexing) have begun to be used as modulation schemes for digital transmission.
[0003]
The data is a transport stream (hereinafter referred to as TS) in which video and audio signals are compressed by MPEG processing.
[0004]
Several years ago, video and audio were transmitted by analog FM. In analog FM, the SN of video and audio changes depending on the received electric field level. In mobile transmission such as a marathon relay where the received electric field level changes drastically, the relayed video signal tends to be a low-quality signal with a lot of noise and disturbance.
[0005]
In digital transmission, information is digitized and error correction processing is used together. Therefore, even when the received electric field level changes, the same quality video can be relayed and transmitted as long as error correction is possible. If the electric field level falls below the limit value, error correction becomes impossible and image transmission becomes impossible. This limit can be grasped to some extent by the signal state after demodulation.
[0006]
For example, in the 64QAM mode with a large transmission amount of 60 Mbps, the limit CN is about 27 dB, and the limit of the reception electric field needs to be about -70 dBm or more. In the 16QAM2 mode with a small transmission amount of 35 Mbps, the limit CN is about 18 dB, and the limit of the reception electric field is about −80 dBm or more so that video can be transmitted.
[0007]
FIG. 14 is an overall configuration diagram of a conventional digital transmission apparatus. In FIG. 14, a video signal is input to the MPEG encoder 1 and becomes compressed data TS. The compressed data TS becomes two-dimensional data Dm by the mapping circuit 2 that determines the modulation mode.
[0008]
The data Dm is modulated by the modulation unit (MOD) 3 and becomes, for example, Dmod, which is an intermediate frequency signal in the 130 MHz band, and is sent to the transmission high frequency unit (Th) 4-1.
[0009]
The transmission high frequency unit (Th) 4-1 converts the frequency of the intermediate frequency signal Dmod into a signal in the microwave band, amplifies the power, and transmits the signal from the antenna 4-2.
[0010]
The radio wave that reaches the receiving antenna 6-1 via the transmission path 5 is input to the receiving high-frequency unit (Rh) 6-2. The reception high-frequency unit (Rh) 6-2 amplifies a weak signal and converts it to an intermediate frequency signal Ddem in the 130 MHz band.
[0011]
This Ddem signal is subjected to time timing reproduction and frequency reproduction by a demodulator (DEM) 7 and becomes two-dimensional data Dd. The data Dd is sent to the discrimination / determination unit 8 and returned to the reproduction compressed data TSr. The reproduction compressed data TSr is input to the MPEG decoder 9 and expanded into a video signal.
[0012]
Here, in order to grasp the quality of the transmission state and the synchronous reproduction state, the output I and Q data of the demodulator (DEM) 7 is normally connected to the XY input of the oscilloscope 10 and observed. If the transmission state is good, each mapping point (signal point) of the received signal is gathered small as shown in FIG. However, if the transmission state is poor, each mapping point becomes large and scattered as shown in FIG.
[0013]
For example, Patent Document 1 discloses that each data is observed by receiving and demodulating a modulated (transmission) signal modulated by the OFDM method and displaying the modulated signal on an oscilloscope.
[0014]
[Patent Document 1]
JP 2002-340937 A (page 2-3)
[0015]
[Problems to be solved by the invention]
However, since the frequency response of the oscilloscope 10 on the X axis is usually less than 1 MHz and cannot follow high-speed signal point changes, it is usually necessary to prepare a dedicated thinned signal for observation.
[0016]
Further, the state of the transmission line 5 is not always constant, and changes every moment depending on the level of a river, sea, or paddy field in the middle of the transmission line. Therefore, it is difficult to record and store changes in the line conditions of digital transmission that change from moment to moment.
[0017]
Further, when receiving a modulation (transmission) signal modulated by a multi-carrier digital modulation method as in the OFDM method, it is difficult to grasp the deterioration state of a specific carrier.
[0018]
SUMMARY OF THE INVENTION An object of the present invention is a digital transmission apparatus for transmitting and receiving a transmission signal modulated by a digital modulation method, and capable of grasping a deterioration state of a specific carrier and converting it into a video signal that can be easily recorded and stored. Is to provide.
[0019]
[Means for Solving the Problems]
The present invention relates to a digital transmission device that transmits a transmission signal modulated by a digital modulation method and mapped in two dimensions, and reproduces the transmission signal by identifying the received two-dimensional data. And a two-dimensional display output device for outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction, connected to a demodulator that demodulates the transmission signal.
[0020]
The present invention also relates to a digital transmission apparatus that transmits a transmission signal modulated by a digital modulation method and mapped in two dimensions, and reproduces the transmission signal by identifying the received two-dimensional data. A hold signal that is connected to a demodulator that demodulates the received transmission signal, holds the demodulated data according to the timing of the demodulating process that demodulates the transmission signal at the demodulator, and has a constant level according to the timing An output unit that outputs an increasing level increase signal, and a video unit that is connected to the output unit and that outputs a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction from the hold signal and the level increase signal A processor is provided.
[0021]
The present invention also relates to a digital transmission apparatus that transmits a transmission signal modulated by a digital modulation method and mapped in two dimensions, and reproduces the transmission signal by identifying the received two-dimensional data. A level increasing signal that is connected to a demodulating unit that demodulates the received transmission signal, and that increases from the data demodulated by the demodulating unit at a constant level according to the timing of the demodulating process that demodulates the transmission signal by the demodulating unit And a video processor for outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction from the demodulated data and the level increase signal.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the present invention. FIG. 1 is a diagram showing the overall configuration of the conventional digital transmission apparatus of FIG. 14, in which an oscilloscope 10 is removed, a timing controller (hereinafter referred to as CNT) 11 and a sampling and holding device (hereinafter referred to as SH) 12 are added, and further a video. The chemical processor 13 was added.
[0023]
As a result, an image 9a is displayed on the monitor screen (not shown) connected to the output of the MPEG decoder 9 in FIG. 1, for example, as shown in FIG. For example, as shown in FIG. 2 (b), the monitor screen (not shown) connected to the output of 2 is composed of the image 9a having frequency components in the X-axis direction and signal components demodulated in the Y-axis direction. A superimposed image on which the dimension display image 13a is superimposed is displayed.
[0024]
In FIG. 1, an FST (frame start pulse) signal from the demodulator (DEM) 7 is input to the CNT 11.
[0025]
The CNT 11 outputs an sp signal (sampling pulse) to the SH 12 and also outputs a Ys signal (Y component sawtooth wave), and the Ys signal is input to the video processing unit 13.
[0026]
The SH 12 receives the output I data of the demodulator (DEM) 7 as an input. The output Xh (I) signal (X component sample hold of I data) of the SH 12 is input to the other terminal of the video processor 13.
[0027]
FIG. 3 is a timing chart showing operations of the timing controller CNT11 and the sampling and holding device SH12 in FIG.
[0028]
In response to the FST (frame start pulse) signal from the demodulator (DEM) 7, the CNT 11 outputs an sp signal whose phase is shifted by FFT processing period × N for each symbol period (cycle). As a result, the SH 12 outputs an Xh (I) signal obtained by sequentially sampling the level of each carrier arranged every 1 FFT period of the I signal from the data of the low frequency component every 1 symbol period.
[0029]
In addition, the CNT 11 creates and outputs a Ys signal whose level is constantly increased every symbol period. The number of increases N of the Ys signal may be the same value as the number of carriers. Alternatively, the maximum number of FFT processes (for example, 1024) may be used.
[0030]
FIG. 4 is a block diagram of the video processing unit 13 in FIG. The video processor 13 receives the Xh (I) signal, which is the output of SH12 in FIG. 1, and the Ys signal, which is the output of CNT11, as input signals.
[0031]
Input signals Xh (I) and Ys are input to A / D converters 14i and 14q, respectively. The outputs of the A / D converters 14i and 14q are input to the change point detectors 15i and 15q, respectively, and also input to the writing unit 16. The outputs of the change point detectors 15 i and 15 q are input to the writing unit 16.
[0032]
The address output, data output, and write enable (WE) output of the writing unit 16 are input to the control unit 19. The address output, data output, and WE output of the initialization unit 17 are input to the control unit 19. The address output and read enable (RE) output of the read display unit 18 are input to the control unit 19.
[0033]
The control unit 19 outputs an enable (EN) signal for permitting operation to the writing unit 16, the initialization unit 17, and the reading display unit 18 based on the video signal output from the MPEG decoder 9 of FIG. In addition, the address output, data output, and control signals WE and RE of the writing unit 16, the initialization unit 17, and the reading display unit 18 are switched and selected between the memory 20a and the memory 20b and output. Further, the data read from the memories 20 a and 20 b is output to the adder 21.
[0034]
The adder 21 superimposes the data read from the memories 20a and 20b on the video signal which is the output of the MPEG decoder 9 in FIG.
[0035]
FIG. 5 is a configuration diagram of the change point detectors 15i and 15q in FIG. 4 (change point detectors 15i and 15q have the same configuration). FIG. 6 is a diagram for explaining the operation of the change point detection and the writing process described below.
[0036]
It is assumed that the I and Q data that are the output of the demodulator (DEM) 7 in FIG. In this case, the Xh (I) signal and the Ys signal, which are input signals to the video processor 13, are input to the latch 15-1 and sampled at 14.3 MHz ((1) in FIG. 6). The output signal of the latch 15-1 is input to the latch 15-2 and the subtracter 15-3. The output signal of the latch 15-2 is input to the other side of the subtractor 15-3. The output signal of the subtractor 15-3, that is, the input differential signal is input to the absolute value converter 15-4, and the positive and negative components are converted into absolute values. The output signal of the absolute value generator 15-4 is input to the determiner 15-5 and is compared with the reference value Th by the determiner 15-5 to indicate “henka” in which a component equal to or higher than the reference value Th is regarded as a change. A change point pulse ((2) in FIG. 6) is output.
[0037]
FIG. 7 is a configuration diagram of the writing unit 16 in FIG. The Xh (I) signal and the Ys signal are converted into a two-dimensional address in the display space by the synthesizer 16-1. The conversion result is held by the S1 pulse from the WE generator 16-2 (which operates or stops according to the EN input), and outputs an address. The gate 16-3 outputs a pulse h1 obtained by ORing the change point pulses ((2) in FIG. 6) indicating "henka" of the Xh (I) signal and the Ys signal.
[0038]
This pulse h1 is input to the gates 16-4 and 16-5.
[0039]
Gate 16-4 is the source of the WE pulse. The gate 16-4 receives the W1 pulse from the WE generator 16-2 (a sampling pulse W1 (1) in FIG. 6 generated by dividing 14.3 MHz by 10) to generate the sampling pulse W1. It is checked whether the timing coincides with the pulse h1 obtained by ORing the change point pulses ((2) in FIG. 6). If they do not match ((4) in FIG. 6), they are sampled as they are (write “1” to the SRAM address), and a WE pulse is output. If they match ((5) in FIG. 6), the sample is canceled. , WE is turned off. In this case, since it is highly probable that the next sample will be a change point, the sample phase is shifted ((6) in FIG. 6). The writing unit 16 always outputs data H. As a result, data of level “H” is written in the memory space corresponding to the values of the I and Q data.
[0040]
Here, the operation of the writing unit 16 will be described again with reference to FIG. It is assumed that the I and Q data that are the output of the demodulator (DEM) 7 in FIG. In this case, the Xh (I) signal and Ys signal which are the input signals of the video processor 13 and the values of the I and Q data are the 4, 10, 16, ..., (6n + 4) th sample pulses, It is assumed that the writing unit 16 takes in the data at a timing of 6 sample periods.
[0041]
In such a case, at the 16th sample pulse timing, “henka” and the sample pulse timing coincide ((5) in FIG. 6). Therefore, when the I and Q values are taken in at the 16th sample point, the locus that is moving transiently from the normal signal point A in FIG. 15A to another normal signal point B. The midpoint value of is taken in. If a large number of such intermediate points of the trajectory are captured, the signal points appear to be scattered as shown in FIG.
[0042]
Therefore, in the embodiment of the present invention, the capturing of the Xh (I) signal and the Ys signal value at the sample point where “henka” and the timing of the sample pulse coincide with each other is paused. Further, since there is a high probability that the next sample timing will also be a change point, the sample pulse generation timing is changed ((6) in FIG. 6). Then, the Xh (I) signal and the Ys signal value at the sample points whose timings do not match are taken into the writing unit 16 as they are.
[0043]
FIG. 8 is a block diagram of the initialization unit 17 in FIG. The address generator 17-1 and the WE generator 17-2 operate or stop according to the EN input. The address generator 17-1 outputs an address corresponding to the EN input. The WE generator 17-2 outputs WE corresponding to the EN input. Also, “L” is output as data. As an overall operation, data “L” is written in the memory address space corresponding to the address generator 17-1 in accordance with the EN input. Specifically, the display space in which the constellation is accumulated is initialized to black.
[0044]
FIG. 9 is a diagram illustrating the operation of the control unit 19 in FIG. First, an F pulse is generated internally as the timing of the frame period from the input video signal. Then, display (reading), erasing (initializing), and constellation writing (writing) are performed on the two memories 20a and 20b in accordance with the F pulse.
[0045]
Specifically, when the memory 20a is displaying (reading) and erasing (initializing), the memory 20b performs constellation writing (writing). Also, when the memory 20a is (1) constellation writing (writing), the memory 20b displays (2) display (read) in field 1, (3) erase (initialization), and (4) display (read) in field 2. (5) Erase (initialize).
[0046]
Here, in (1) constellation writing, “1” is written to the SRAM address corresponding to the sampled Xh (I) and Ys values (performed for one frame period (cycle)). In the above (2) display (field 1), the SRAM address data corresponding to the scanning line is read out for each pixel. If the corresponding Xh (I), Ys value exists, the read value becomes “1”, and one pixel of the NTSC screen is displayed in white. In (3) erasure (field 1), “0” is written to the address read in (2) above (the memory is initialized and the memory contents of the displayed pixel area are returned to black). In the display (4) (field 2), the same operation as the display (2) (field 1) is performed. In (5) erasure (field 2), the same operation as in (3) erasure (field 1) is performed.
[0047]
When the memory 20a displays (reads) and erases (initializes) and the memory 20b performs constellation writing (writing), the following is repeated.
First half of field 1 of frame 1: Reading of an even address in the memory 20a.
Second half of field 1 of frame 1: erasure of even address in memory 20a.
First half of field 2 of frame 1: Reading of odd address of memory 20a
Second half of field 2 of frame 1: Erasing odd addresses in memory 20a.
Frame 1 field 1: Write to Xh (I), Ys signal corresponding address in memory 20a.
Frame 2 field 2: Write to the memory 20a at the address corresponding to the Xh (I) and Ys signals.
First half of field 1 of frame 3: read even address of memory 20a
Second half of field 1 of frame 3: Erasing even addresses in memory 20a.
Thereafter, the above operation is repeated.
[0048]
On the other hand, when the memory 20b displays (reads) and erases (initializes) and the memory 20b performs the constant write (write), the following is repeated.
Frame 1 field 1: Write to Xh (I), Ys signal corresponding address to memory 20b.
Frame 1 field 2: Write to the memory 20b at the address corresponding to the Xh (I) and Ys signals.
First half of field 1 of frame 2: Reading of even address of memory 20b
Second half of field 1 of frame 2: erasure of even address in memory 20b.
First half of field 2 of frame 2: Reading of odd address of memory 20b.
Second half of field 2 of frame 2: Erasing odd addresses in memory 20b.
Thereafter, the above operation is repeated.
[0049]
As a result, the value of the I data from the demodulator (DEM) 7 is converted into the corresponding memory address space, and the level “H” is written into the memory 20a or 20b. In each of the memories 20a and 20b, the level “H” is read from the corresponding memory address in the reading period. The contents of the non-corresponding memory address remain “L”. In the erasure (initialization) performed after the reading is completed, the accumulated contents of the mapping points are initialized by writing “L” in the address space corresponding to the reading.
[0050]
FIG. 10 is a configuration diagram of the readout display unit 18 in FIG. The operations of the address generator 18-1 and the RE generator 18-2 operate or stop according to the EN input. The address generator 18-1 outputs an address corresponding to the display screen. The RE generator 18-2 outputs an RE. As an overall operation, the memory address space data corresponding to the display address generator 18-1 is read in accordance with the EN input. That is, the display space in which the constellation is accumulated is output according to the scanning line timing for display.
[0051]
The read constellation space is superimposed on the video signal which is the output of the MPEG decoder 9 of FIG. 1 by the adder 21 and output as a video XY signal.
[0052]
A monitor screen (not shown) connected to the output of the video processor 13 is displayed on a monitor screen (not shown) connected to the output of the MPEG decoder 9, for example, as shown in FIG. A superimposed image is displayed by superimposing a two-dimensional display image 13a composed of a frequency component in the X-axis direction, a signal component demodulated in the Y-axis direction, and a shift component indicating a change in the demodulated signal on the image 9a.
[0053]
In this embodiment, since there is no band limitation for writing, there is no problem such as distorted display that occurs in a conventional oscilloscope or the like.
[0054]
In addition, according to the present embodiment, in the two-dimensional display signal 13a on the display screen of FIG. 2, the noise component of the carrier in the deteriorated band increases. It is displayed thick. Also, the thickness changes according to the degree of the deterioration. For this reason, it is possible to easily determine whether frequency selective fading has occurred in the used band and partially deteriorated, or whether the entire band has deteriorated and improvement is difficult.
[0055]
In the case of frequency selective fading, there is a possibility that the level of the multipath wave that causes an adverse effect is reduced by changing the direction of the receiving antenna, and as a result, frequency selective fading can be avoided.
[0056]
FIG. 11 is a block diagram showing the overall configuration of the second embodiment of the digital transmission apparatus according to the present invention. FIG. 12 is a block diagram of the video processing unit 13A in FIG.
[0057]
FIG. 11 is a diagram showing the overall configuration of the conventional digital transmission apparatus of FIG. 14, in which the oscilloscope 10 is removed and a video processor 13A is added. The video processor 13A receives the output I data of the demodulator (DEM) 7 as an input. The video processor 13A shown in FIG. 12 removes the A / D converter 14q and the change point detector 15q in the video processor 13 shown in FIG. 4, and has no change period detector 22 and SAW (sawtooth wave) generator 23. Was added. FIG. 13 is a timing chart showing an operation in the video processing unit 13A of FIG.
[0058]
The I data from the demodulator (DEM) 7 is input to the AD converter 14i. The output of the AD converter 14 i is input to the change point detector 15 i and the writing unit 16. The output henka of the change point detector 15 i is input to the writing unit 16 and the no-change detector 22. The output nasi signal of the no-change detector 22 is input to the SAW generator 23. The output Ys signal of the SAW generator 23 is input to the writing unit 16.
[0059]
The change point detector 15i outputs, as henka, the timing at which the level of the I data has changed.
[0060]
The no-change period detector 22 detects a state where there is no henka for a certain period, and outputs a nasi signal whose level is at level H.
[0061]
The SAW generator 23 generates a SAW wave whose level is constantly amplified every symbol period from the timing when the nasi signal falls, and outputs a Ys signal that outputs the SAW wave again from the initial level when the nasi falls again. .
[0062]
The address output, data output, and WE output of the writing unit 16 are input to the control unit 19.
[0063]
The address output, data output, and WE output of the initialization unit 17 are input to the control unit 19.
[0064]
The address output and RE output of the readout display unit 18 are input to the control unit 19.
[0065]
The control unit 19 outputs two EN signals permitting operation to the writing unit 16, the initialization unit 17, and the reading display unit 18 based on the video signal output from the MPEG decoder 9 of FIG. Further, the address output, data output, and control signals WE and RE of the writing unit 16, the initialization unit 17, and the reading display unit 18 are switched and selected between the memory 20a and the memory 20b and output. Further, the data read from the memories 20 a and 20 b is output to the adder 21.
[0066]
The adder 21 superimposes the data read from the memories 20a and 20b on the video signal which is the output of the MPEG decoder 9 in FIG.
[0067]
As a result, the values of the I and Q data from the demodulator (DEM) 7 are converted into the corresponding memory address space, and the level H is written into the memory 20a or 20b. In each of the memories 20a and 20b, the level “H” is read from the corresponding memory address in the reading period. The contents of the non-corresponding memory address remain “L”. Erasing (initialization) performed after completion of reading initializes the accumulated contents of mapping points by writing “L” in an address space corresponding to reading.
[0068]
The read constellation space is superimposed by the adder 21 on the video signal that is the output of the MPEG decoder 9 in FIG. 11 and output as a video XY signal.
[0069]
A monitor screen (not shown) connected to the output of the video processor 13A is displayed on a monitor screen (not shown) connected to the output of the MPEG decoder 9, for example, as shown in FIG. A superimposed image in which a two-dimensional display image 13a composed of a frequency component in the X-axis direction and a demodulated signal component in the Y-axis direction is superimposed on the image 9a is displayed.
[0070]
Even in this embodiment mode, there is no problem such as distorted display that occurs in an oscilloscope because there is no band limitation for writing.
[0071]
Also in the present embodiment, in the two-dimensional display signal 13a in the display screen of FIG. 2, the noise component of the carrier in the degraded band increases, so that when displayed two-dimensionally, the horizontal line is thicker than the band in good condition. Is displayed. Also, the thickness changes according to the degree of the deterioration. For this reason, it is possible to easily determine whether frequency selective fading has occurred in the band being used and partially deteriorated, or whether the entire band has deteriorated and improvement is difficult.
[0072]
In the above-described embodiment of the present invention, only the display of two-dimensional I and Q data has been described. However, the superimposed video signal includes information related to a delay profile, bit error, and input electric field, The video signal including the synchronization state of the transmission apparatus and the decompression state of the MPEG codec may be included.
[0073]
【The invention's effect】
According to the present invention, in a digital transmission apparatus that transmits and receives a transmission signal modulated by a digital modulation system, the digital transmission apparatus that can grasp a deterioration state of a specific carrier and converts it into a video signal that can be easily recorded and stored. Can be obtained.
[Brief description of the drawings]
1 is an overall configuration diagram showing a first embodiment of a digital transmission apparatus according to the present invention;
2A is a diagram illustrating an example of an image displayed on a monitor screen, and FIG. 2B is a diagram illustrating an example of an image displayed on a monitor screen and a two-dimensional display image.
FIG. 3 is a timing diagram showing operations of the timing controller CNT and the sampling and holding device in FIG. 1;
4 is a block diagram of the video processing unit in FIG. 1. FIG.
5 is a configuration diagram of a change point detector in FIG. 4. FIG.
FIG. 6 is a diagram for explaining operation of change point detection and writing processing;
7 is a configuration diagram of a writing unit in FIG. 4. FIG.
FIG. 8 is a configuration diagram of an initialization unit in FIG. 4;
FIG. 9 is a diagram for explaining the control operation in FIG. 4;
10 is a configuration diagram of a readout display unit in FIG. 4;
FIG. 11 is a block diagram showing an overall configuration of a second embodiment of the digital transmission apparatus according to the present invention.
12 is a block diagram of the video processing unit in FIG. 11. FIG.
FIG. 13 is a timing chart showing an operation in the video processing unit of FIG. 12;
FIG. 14 is an overall configuration diagram of a conventional digital transmission apparatus.
FIGS. 15A and 15B are diagrams showing received signal mapping points (signal points) observed by the oscilloscope in FIG. 14, where FIG. 15A shows a case where the transmission state is good, and FIG. 15B shows a case where the transmission state is bad. is there.
[Explanation of symbols]
1: MPEG encoder, 2: Mapping circuit, 3: Modulation unit (MOD, 4-1: Transmission high frequency unit (Th), 4-2: Antenna, 5: Transmission path, 6-1: Antenna, 6-2: Reception High-frequency unit (Rh), 7: Demodulation unit (DEM), 8: Discriminator / determiner, 9: MPEG decoder, 9a: Image displayed on monitor screen (not shown) connected to the output of MPEG decoder, 10: Oscilloscope 11: Timing controller (CNT), 12: Sampling hold device (SH), 13, 13A: Video processing unit, 13a: Two-dimensional display image, 14i, 14q: A / D converter, 15i, 15q: Change inspection Decoder, 16: writing unit, 17: initialization unit, 18: reading display unit, 19: control unit, 20a, 20b: memory, 21: adder, 22: no change period detector 23: SAW generator.

Claims (3)

In a digital transmission device that transmits a transmission signal that is modulated by a digital modulation method and that is two-dimensionally mapped, and that reproduces the transmission signal by identifying the received two-dimensional data, the received transmission signal A digital transmission device comprising a two-dimensional display output device connected to a demodulator that demodulates the signal and outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction. In a digital transmission device that transmits a transmission signal that is modulated by a digital modulation method and that is two-dimensionally mapped, and that reproduces the transmission signal by identifying the received two-dimensional data, the received transmission signal A hold signal that holds the demodulated data according to the timing of the demodulating process for demodulating the transmission signal by the demodulator, and a level increase signal that increases the level constantly according to the timing And a video processor for outputting a frequency component in the X-axis direction and a demodulated signal component in the Y-axis direction from the hold signal and the level increase signal. A digital transmission apparatus characterized by the above. In a digital transmission device that transmits a transmission signal that is modulated by a digital modulation method and that is two-dimensionally mapped, and that reproduces the transmission signal by identifying the received two-dimensional data, the received transmission signal Is generated from the data demodulated in the demodulating unit, and a level increasing signal that increases the level constantly according to the timing of the demodulating process for demodulating the transmission signal in the demodulating unit is generated, A digital transmission apparatus comprising: a video processor for outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction from the demodulated data and the level increase signal.

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