JP2004357106A - Digital transmission apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital transmission apparatus, for transmitting/receiving a modulated transmission signal modulated according to a digital modulation scheme, capable of grasping the deterioration state of a specific carrier and converting it into an image signal easy to record and save. <P>SOLUTION: This digital transmission apparatus is characterized by comprising output devices (11, 12, 13) for two dimensional display on the receiving device side. The output devices (11, 12, 13) are connected to a demodulation unit for demodulating a received transmission signal and output a frequency component in the X-axis direction, and a demodulated signal component in the Y-axis direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital transmission device, and more particularly to a digital transmission device for visualizing a transmission state.
[0002]
[Prior art]
In recent years, a QAM (Quadrature Amplitude Modulation) system and an OFDM (Orthogonal Frequency Division Multiplexing) system have begun to be used as modulation systems for digital transmission.
[0003]
The data is a transport stream (hereinafter, referred to as TS) obtained by compressing a video or audio signal by MPEG processing.
[0004]
A few years ago, video and audio were transmitted by analog FM. In the analog FM, the SN of video and audio changes depending on the received electric field level. In mobile transmission such as a marathon relay where the level of the received electric field changes drastically, the relayed video signal tends to be a low-quality signal with much noise and disturbance.
[0005]
In digital transmission, information is digitized and error correction processing is used together. Therefore, even in a state where the reception electric field level changes, the same quality video can be relayed and transmitted as long as the error correction works. When the electric field level falls below the limit value, error correction becomes impossible and image transmission becomes impossible. This limit can be grasped to some extent by the signal state after demodulation.
[0006]
For example, in the case of a 64 QAM mode with a large transmission amount of 60 Mbps, the limit CN is about 27 dB, and the limit of the reception electric field needs to be about -70 dBm or more. In the case of the 16 QAM2 mode, which has a small transmission amount of 35 Mbps, the limit CN is about 18 dB, and the limit of the reception electric field is about -80 dBm or more, and the image can be transmitted.
[0007]
FIG. 14 is an overall configuration diagram of a conventional digital transmission device. In FIG. 14, a video signal is input to the MPEG encoder 1 and becomes compressed data TS. The compressed data TS is converted into two-dimensional data Dm by the mapping circuit 2 that determines the modulation mode.
[0008]
The data Dm is modulated by the modulating unit (MOD) 3 and becomes, for example, Dmod which is an intermediate frequency signal in a 130 MHz band, and is sent to the transmitting high frequency unit (Th) 4-1.
[0009]
The transmission high-frequency section (Th) 4-1 converts the frequency of the intermediate frequency signal Dmod into a signal in the microwave band, amplifies the power, and transmits the signal from the antenna 4-2.
[0010]
The radio wave that has reached the receiving antenna 6-1 via the transmission path 5 is input to the receiving high-frequency unit (Rh) 6-2. The reception high frequency unit (Rh) 6-2 amplifies the weak signal and converts it into an intermediate frequency signal Ddem in the 130 MHz band.
[0011]
The Ddem signal is subjected to time timing reproduction and frequency reproduction by the demodulation unit (DEM) 7 to become two-dimensional data Dd. The data Dd is sent to the identification judging unit 8 and is returned to the reproduction compressed data TSr. The playback compression data TSr is input to the MPEG decoder 9 and is expanded into a video signal.
[0012]
Here, in order to ascertain whether the transmission state or the synchronous reproduction state is good or not, the output I and Q data of the demodulation unit (DEM) 7 are usually connected to the XY input of the oscilloscope 10 and observed. If the transmission state is good, each mapping point (signal point) of the received signal is small as shown in FIG. However, when the transmission state is poor, the mapping points become large and scattered as shown in FIG.
[0013]
Observing each data by receiving and demodulating a modulated (transmission) signal modulated by the OFDM method and displaying the signal on an oscilloscope is known, for example, from Patent Document 1.
[0014]
[Patent Document 1]
JP-A-2002-340937 (pages 2-3)
[0015]
[Problems to be solved by the invention]
However, the frequency response of the oscilloscope 10 in the X-axis is usually less than 1 MHz, and cannot follow a high-speed signal point change. Therefore, it is usually necessary to prepare a thinned-out signal exclusively for observation.
[0016]
Further, the state of the transmission line 5 is not always constant, and changes every moment depending on the water level of a river, sea, or paddy field in the middle of the transmission line. Therefore, it is difficult to record and save the ever-changing digital transmission line conditions.
[0017]
Further, when a modulated (transmission) signal modulated by a digital modulation method of many carriers is received as in the above-mentioned OFDM method, it is difficult to grasp the deterioration state of a specific carrier.
[0018]
SUMMARY OF THE INVENTION An object of the present invention is to provide a digital transmission apparatus for transmitting and receiving a transmission signal modulated by a digital modulation method, wherein the deterioration state of a specific carrier can be grasped, and the digital transmission apparatus converts the deterioration state into a video signal which can be easily recorded and stored. Is to provide.
[0019]
[Means for Solving the Problems]
The present invention relates to a digital transmission apparatus for transmitting a transmission signal modulated by a digital modulation scheme and mapped in two dimensions and reproducing the transmission signal by identifying the received two-dimensional data. A two-dimensional display output device connected to a demodulation unit for demodulating the transmission signal and outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction.
[0020]
Further, the present invention provides a digital transmission apparatus which transmits a transmission signal modulated by a digital modulation method and mapped in two dimensions and reproduces the transmission signal by identifying received two-dimensional data. A hold signal that is connected to a demodulation unit that demodulates the received transmission signal and that holds data after demodulation in accordance with the timing of demodulation processing for demodulating the transmission signal in the demodulation unit, and a level that is constant according to the timing. An output section for outputting an increasing level increase signal; and a video signal connected to the output section for outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction from the hold signal and the level increase signal. A processor is provided.
[0021]
Further, the present invention provides a digital transmission apparatus which transmits a transmission signal modulated by a digital modulation method and mapped in two dimensions and reproduces the transmission signal by identifying received two-dimensional data. A level increase signal connected to a demodulation unit for demodulating the received transmission signal and constantly increasing the level from data after demodulation in the demodulation unit in accordance with the timing of demodulation processing for demodulating the transmission signal in the demodulation unit. And a video processor for outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction from the demodulated data and the level increase signal.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the present invention. FIG. 1 is a diagram showing the entire configuration of the conventional digital transmission apparatus shown in FIG. 14, in which an oscilloscope 10 is removed, a timing controller (hereinafter, referred to as CNT) 11 and a sampling and holding device (hereinafter, referred to as SH) 12 are added. A chemical processor 13 was added.
[0023]
As a result, an image 9a is displayed on a monitor screen (not shown) connected to the output of the MPEG decoder 9 in FIG. 1, for example, as shown in FIG. A monitor screen (not shown) connected to the output of the image 9a includes a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction on the image 9a as shown in FIG. A superimposed image on which the three-dimensional display image 13a is superimposed is displayed.
[0024]
In FIG. 1, an FST (frame start pulse) signal from a demodulation unit (DEM) 7 is input to a CNT 11.
[0025]
The CNT 11 outputs an sp signal (sampling pulse) to the SH 12 and outputs a Ys signal (sawtooth of the Y component), and the Ys signal is input to the video processor 13.
[0026]
The SH 12 receives the output I data of the demodulation unit (DEM) 7 as an input. The output Xh (I) signal (X component sample and hold of I data) of the SH 12 is input to the other terminal of the video processor 13.
[0027]
FIG. 3 is a timing chart showing the operation of the timing controller CNT11 and the sampling and holding unit SH12 in FIG.
[0028]
In response to an FST (frame start pulse) signal from the demodulation unit (DEM) 7, the CNT 11 outputs an sp signal whose phase is shifted by FFT processing period × N in each symbol period (cycle). As a result, the SH 12 outputs an Xh (I) signal obtained by sequentially sampling the level of each carrier arranged for each FFT period of the I signal from data of a low frequency component for each symbol period.
[0029]
The CNT 11 creates and outputs a Ys signal whose level is constantly increased every symbol period. The number of increase N of the Ys signal may be the same value as the number of carriers. Alternatively, the maximum number of FFT processes (for example, 1024) may be used.
[0030]
FIG. 4 is a configuration diagram of the video processing unit 13 in FIG. The Xh (I) signal output from the SH 12 and the Ys signal output from the CNT 11 in FIG.
[0031]
The Xh (I) signal and the Ys signal, which are input signals, are input to A / D converters 14i and 14q, respectively. The outputs of the A / D converters 14i and 14q are input to the change point detectors 15i and 15q, respectively, and are also input to the writing unit 16. The outputs of the change point detectors 15i and 15q are input to the writing unit 16.
[0032]
The address output, data output, and write enable (WE) output of the writing unit 16 are input to the control unit 19. The address output, data output, and WE output of the initialization unit 17 are input to the control unit 19. The address output and read enable (RE) output of the read display unit 18 are input to the control unit 19.
[0033]
The control unit 19 outputs an enable (EN) signal for permitting the operation to the writing unit 16, the initialization unit 17, and the reading display unit 18 based on the video signal output from the MPEG decoder 9 in FIG. Further, the address output, data output, and control signals WE and RE of the writing unit 16, the initialization unit 17, and the reading display unit 18 are selectively switched to the memory 20a and the memory 20b and output. The data read from the memories 20a and 20b is output to the adder 21.
[0034]
The adder 21 superimposes the data read from the memories 20a and 20b on the video signal output from the MPEG decoder 9 in FIG. 1 and outputs it as a video XY signal.
[0035]
FIG. 5 is a configuration diagram of the change point detectors 15i and 15q in FIG. 4 (the change point detectors 15i and 15q have the same configuration). FIG. 6 is a diagram for explaining the operation of the change point detection and the write processing described next.
[0036]
It is assumed that the I and Q data output from the demodulation unit (DEM) 7 shown in FIG. In this case, the Xh (I) signal and the Ys signal, which are the input signals of the video processor 13, are input to the latch 15-1 and are sampled at 14.3 MHz ((1) in FIG. 6). The output signal of the latch 15-1 is input to the latch 15-2 and the subtractor 15-3. The output signal of the latch 15-2 is input to the other of the subtractor 15-3. The output signal of the subtractor 15-3, that is, the input differential signal is input to the absolute value converter 15-4, and the positive and negative components are converted to absolute values. The output signal of the absolute value converter 15-4 is input to the determiner 15-5, and is compared with the reference value Th by the determiner 15-5 to indicate "henka" in which a component equal to or greater than the reference value Th is regarded as a change. A change point pulse ((2) in FIG. 6) is output.
[0037]
FIG. 7 is a configuration diagram of the writing unit 16 in FIG. The Xh (I) signal and the Ys signal are converted into a two-dimensional address in the display space by the synthesizer 16-1. The conversion result is held by the S1 pulse from the WE generator 16-2 (operating or stopping according to the EN input) and outputs an address. The gate 16-3 outputs a pulse h1 that is the logical sum of the Xh (I) signal and the change point pulse (“2” in FIG. 6) indicating “henka” of the Ys signal.
[0038]
This pulse h1 is input to the gate 16-4 and the gate 16-5.
[0039]
Gate 16-4 is the source of the WE pulse. The gate 16-4 receives a W1 pulse (a sampling pulse W1 created by dividing 14.3 MHz by 10) from the WE generator 16-2 ((3) in FIG. 6) to generate the sampling pulse W1. It is checked whether the timing coincides with the pulse h1 that is the logical sum of the change point pulse ((2) in FIG. 6). If they do not match ((4) in FIG. 6), they are sampled as they are (write "1" to the SRAM address), and a WE pulse is output. If they match ((5) in FIG. 6), the sample is stopped. , WE are turned off. In this case, the phase of the sample is shifted because the probability that the next sample also hits the change point is high ([6] in FIG. 6). The writing unit 16 always outputs data H. As a result, level "H" data is written to the memory space corresponding to the values of the I and Q data.
[0040]
Here, the operation of the writing unit 16 will be described again with reference to FIG. It is assumed that the I and Q data output from the demodulation unit (DEM) 7 shown in FIG. In this case, the Xh (I) signal and the Ys signal, which are the input signals of the video processing unit 13, and the values of the I and Q data are the 4, 10, 16,..., (6n + 4) th sample pulses, , At the timing of six sample periods.
[0041]
In such a case, at the sixteenth sample pulse timing, the timing of “henka” and the sample pulse coincide (5 in FIG. 6). Therefore, when the I and Q values are captured at the 16th sample point, the trajectory that is originally transiently moving from the normal signal point A in FIG. Will take in the value of the midpoint of. If a large number of such intermediate points of the trajectory are taken in, the signal points appear to be scattered as shown in FIG.
[0042]
Therefore, in the embodiment of the present invention, the acquisition of the Xh (I) signal and the Ys signal value at the sample point where the timing of the sample pulse coincides with “henka” is suspended. Further, since the next sample timing also has a high probability of hitting the change point, the generation timing of the sample pulse is changed ([6] in FIG. 6). Then, the Xh (I) signal and the Ys signal value at the sampling points where the timings do not match are taken into the writing unit 16 as they are.
[0043]
FIG. 8 is a configuration diagram of the initialization unit 17 in FIG. The address generator 17-1 and the WE generator 17-2 operate or stop according to the EN input. The address generator 17-1 outputs an address corresponding to the EN input. The WE generator 17-2 outputs a WE corresponding to the EN input. Also, "L" is output as data. As an overall operation, data “L” is written into a memory address space corresponding to the address generator 17-1 according to the EN input. Specifically, the display space in which the constellation is accumulated is initialized in a form of black.
[0044]
FIG. 9 is a diagram illustrating the operation of the control unit 19 in FIG. First, an F pulse is internally generated as a frame cycle timing from an input video signal. Then, in accordance with the F pulse, display (read), erase (initialization), and constellation write (write) are performed on the memories 20a and 20b on the two surfaces.
[0045]
Specifically, when the memory 20a performs display (reading) and erasing (initialization), the memory 20b performs constellation writing (writing). When the memory 20a performs (1) constellation write (write), the memory 20b stores (2) display (read), (3) erase (initialize) of field 1 and (4) display (read) of field 2, (5) Erase (initialize).
[0046]
Here, in the above (1) constellation writing, "1" is written to the SRAM address corresponding to the sampled Xh (I), Ys values (perform one frame period (period)). In the above (2) display (field 1), the data of the SRAM address corresponding to the scanning line is read out for each pixel. If the corresponding Xh (I), Ys values exist, the read value becomes "1", and one pixel of the NTSC screen is displayed in white. In the above (3) erase (field 1), "0" is written to the address read in the above (2) (the memory is initialized and the memory content of the displayed pixel area is returned to black). In the above (4) display (field 2), the same operation as in the above (2) display (field 1) is performed. In (5) erase (field 2), the same operation as in (3) erase (field 1) is performed.
[0047]
When the memory 20a performs display (reading) and erasing (initialization) and the memory 20b performs constellation writing (writing), the following is repeated.
First half of field 1 of frame 1: reading of even address of memory 20a.
-The latter half of field 1 of frame 1: erasing of even addresses of memory 20a.
-First half of field 2 of frame 1: reading of odd address of memory 20a.
-The latter half of field 2 of frame 1: erasing of odd addresses in memory 20a.
-Field 1 of frame 2: Write to the memory 20a at the address corresponding to the Xh (I), Ys signal.
-Field 2 of frame 2: Write to memory 20a at an address corresponding to Xh (I) and Ys signals.
The first half of the field 1 of the frame 3: reading the even address of the memory 20 a.
-The latter half of the field 1 of the frame 3: erase the even address of the memory 20a.
Thereafter, the above operation is repeated.
[0048]
Conversely, when the memory 20b performs display (reading) and erasing (initialization) and the memory 20b performs constrator writing (writing), the following is repeated.
-Field 1 of frame 1: Write Xh (I), Ys signal corresponding address to memory 20b.
Field 2 of frame 1: Write to memory 20b at an address corresponding to Xh (I) and Ys signals.
The first half of the field 1 of the frame 2: reading of an even address of the memory 20b.
The latter half of the field 1 of the frame 2: the erasure of the even address of the memory 20b.
The first half of the field 2 of the frame 2: reading of an odd address of the memory 20 b.
-Second half of field 2 of frame 2: Erasure of odd addresses in memory 20b.
Thereafter, the above operation is repeated.
[0049]
As a result, the value of the I data from the demodulation unit (DEM) 7 is converted into the corresponding memory address space, and the level “H” is written to the memory 20a or 20b. In each of the memories 20a and 20b, the level “H” is read from the corresponding memory address during the reading period. The content of the uncorresponding memory address remains "L". In the erasing (initialization) performed after the completion of the reading, the accumulated contents of the mapping points are initialized by writing "L" in an address space corresponding to the reading.
[0050]
FIG. 10 is a configuration diagram of the reading display unit 18 in FIG. The operations of the address generator 18-1 and the RE generator 18-2 operate or stop according to the EN input. The address generator 18-1 outputs an address corresponding to the display screen. RE generator 18-2 outputs RE. As an overall operation, data in a memory address space corresponding to the display address generator 18-1 is read according to the EN input. That is, the display space in which the constellation is accumulated is output in accordance with the scanning line timing for display.
[0051]
The read constellation space is superimposed on the video signal output from the MPEG decoder 9 in FIG. 1 by the adder 21 and output as a video XY signal.
[0052]
On a monitor screen (not shown) connected to the output of the video processor 13, for example, as shown in FIG. 2B, a monitor screen (not shown) connected to the output of the MPEG decoder 9 is displayed. A superimposed image is displayed in which a two-dimensional display image 13a including a frequency component in the X-axis direction, a signal component demodulated in the Y-axis direction, and a shift component indicating a change in the demodulated signal is superimposed on the image 9a.
[0053]
In the present embodiment, since there is no band limitation for writing, there is no problem such as display distortion that occurs in a conventional oscilloscope or the like.
[0054]
Further, according to the present embodiment, in the two-dimensional display signal 13a on the display screen of FIG. 2, the carrier of the deteriorated band has an increased noise component. It is displayed thick. The thickness also changes according to the degree of the deterioration. Therefore, it is possible to easily determine whether frequency selective fading occurs in the used band and the band is partially deteriorated, or whether the entire band is deteriorated and the improvement is difficult.
[0055]
In the case of frequency selective fading, by changing the direction of the receiving antenna, the level of a multipath wave which causes an adverse effect may be reduced, and as a result, frequency selective fading may be avoided.
[0056]
FIG. 11 is a block diagram showing the overall configuration of the second embodiment of the digital transmission apparatus according to the present invention. FIG. 12 is a configuration diagram of the video processing unit 13A in FIG.
[0057]
FIG. 11 shows the overall configuration of the conventional digital transmission apparatus of FIG. 14, in which the oscilloscope 10 is removed and a video processor 13A is added. The video processor 13A receives the output I data of the demodulation unit (DEM) 7 as an input. A video processor 13A shown in FIG. 12 removes the A / D converter 14q and the change point detector 15q in the video processor 13 of FIG. 4, and outputs a no-change period detector 22 and a SAW (saw wave) generator 23. Was added. FIG. 13 is a timing chart showing an operation in the video processor 13A of FIG.
[0058]
The I data from the demodulation unit (DEM) 7 is input to the AD converter 14i. The output of the AD converter 14i is input to the change point detector 15i and the writing unit 16. The output henka of the change point detector 15i is input to the writing unit 16 and the no-change detector 22. The output nasi signal of the no-change detector 22 is input to the SAW generator 23. The output Ys signal of the SAW generator 23 is input to the writing unit 16.
[0059]
The change point detector 15i outputs the timing at which the level of the I data has changed as henka.
[0060]
The no-change period detector 22 detects a state in which there is no henka for a certain period, and outputs a nasi signal in which the level becomes H during that period.
[0061]
The SAW generator 23 generates a SAW wave for amplifying the level constantly at every symbol period from the timing when the nasi signal falls, and outputs the Ys signal for outputting the SAW wave again from the initial level when the nasi signal falls again. .
[0062]
The address output, data output, and WE output of the writing unit 16 are input to the control unit 19.
[0063]
The address output, data output, and WE output of the initialization unit 17 are input to the control unit 19.
[0064]
The address output and the RE output of the read display unit 18 are input to the control unit 19.
[0065]
The control unit 19 outputs two EN signals permitting the operation to the writing unit 16, the initialization unit 17, and the reading display unit 18 based on the video signal output from the MPEG decoder 9 in FIG. Further, the address output, data output, and control signals WE and RE of the writing unit 16, the initialization unit 17, and the reading display unit 18 are selectively switched between the memory 20a and the memory 20b and output. Further, the data read from the memories 20a and 20b is output to the adder 21.
[0066]
The adder 21 superimposes the data read from the memories 20a and 20b on the video signal output from the MPEG decoder 9 shown in FIG. 11 and outputs it as a video XY signal.
[0067]
Thereby, the values of the I and Q data from the demodulation unit (DEM) 7 are converted into the corresponding memory address space, and the level H is written to the memory 20a or the memory 20b. In each of the memories 20a and 20b, the level "H" is read from the corresponding memory address in the read period. The contents of the non-corresponding memory address remain "L". In the erasing (initialization) performed after the completion of the reading, the accumulated contents of the mapping points are initialized by writing "L" in an address space corresponding to the reading.
[0068]
The read constellation space is superimposed by the adder 21 on the video signal output from the MPEG decoder 9 in FIG. 11 and output as a video XY signal.
[0069]
On a monitor screen (not shown) connected to the output of the video processor 13A, for example, as shown in FIG. 2B, a monitor screen (not shown) connected to the output of the MPEG decoder 9 is displayed. A superimposed image is displayed in which a two-dimensional display image 13a composed of a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction is superimposed on the image 9a.
[0070]
Also in the present embodiment, since there is no band limitation in writing, there is no problem such as distorted display that occurs in an oscilloscope.
[0071]
Also in the present embodiment, in the two-dimensional display signal 13a on the display screen of FIG. 2, the carrier in the deteriorated band has an increased noise component. Is displayed. The thickness also changes according to the degree of the deterioration. Therefore, it is possible to easily determine whether frequency selective fading occurs in the used band and the band is partially deteriorated, or whether the entire band is deteriorated and the improvement is difficult.
[0072]
In the above-described embodiment of the present invention, only the display of two-dimensional I and Q data has been described. However, a video signal to be superimposed includes information related to a delay profile, a bit error, an input electric field, The video signal may include the synchronization state of the transmission device and the expanded state of the MPEG codec.
[0073]
【The invention's effect】
According to the present invention, in a digital transmission apparatus for transmitting and receiving a transmission signal modulated by a digital modulation method, a digital transmission apparatus capable of ascertaining a deterioration state of a specific carrier and converting it into a video signal which can be easily recorded and stored. Can be obtained.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram showing a first embodiment of a digital transmission device according to the present invention.
2A is a diagram illustrating an example of an image displayed on a monitor screen, and FIG. 2B is a diagram illustrating an example of an image displayed on a monitor screen and a two-dimensional display image.
FIG. 3 is a timing chart showing operations of a timing controller CNT and a sampling and holding device in FIG.
FIG. 4 is a configuration diagram of a video processing unit in FIG. 1;
FIG. 5 is a configuration diagram of a change point detector in FIG. 4;
FIG. 6 is a diagram for explaining operations of a change point detection and a writing process.
FIG. 7 is a configuration diagram of a writing unit in FIG. 4;
FIG. 8 is a configuration diagram of an initialization unit in FIG. 4;
FIG. 9 is a diagram for explaining the control operation in FIG. 4;
FIG. 10 is a configuration diagram of a reading display unit in FIG. 4;
FIG. 11 is a block diagram showing an entire configuration of a digital transmission device according to a second embodiment of the present invention.
FIG. 12 is a configuration diagram of a video processing unit in FIG. 11;
FIG. 13 is a timing chart showing an operation in the video processing unit of FIG. 12;
FIG. 14 is an overall configuration diagram of a conventional digital transmission device.
15 is a diagram showing each mapping point (signal point) of a received signal observed by the oscilloscope of FIG. 14, where (a) is a diagram when the transmission state is good, and (b) is a diagram when the transmission state is bad. is there.
[Explanation of symbols]
1: MPEG encoder, 2: mapping circuit, 3: modulation unit (MOD, 4-1: transmission high-frequency unit (Th), 4-2: antenna, 5: transmission line, 6-1: antenna, 6-2: reception High frequency section (Rh), 7: demodulation section (DEM), 8: identification determiner, 9: MPEG decoder, 9a: image displayed on monitor screen (not shown) connected to output of MPEG decoder, 10: oscilloscope , 11: timing controller (CNT), 12: sampling and holding unit (SH), 13, 13A: video processing unit, 13a: two-dimensional display image, 14i, 14q: A / D converter, 15i, 15q: change check Output unit, 16: writing unit, 17: initialization unit, 18: read-out display unit, 19: control unit, 20a, 20b: memory, 21: adder, 22: no change period detector 23: SAW generator.

Claims (3)

In a digital transmission apparatus for transmitting a transmission signal modulated by a digital modulation method and mapped in two dimensions, and reproducing the transmission signal by identifying the received two-dimensional data, the transmission apparatus receives the transmission signal on a receiving apparatus side. A digital transmission device comprising: a two-dimensional display output device connected to a demodulation unit for demodulating the signal and outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction. In a digital transmission apparatus for transmitting a transmission signal modulated by a digital modulation method and mapped in two dimensions, and reproducing the transmission signal by identifying the received two-dimensional data, the transmission apparatus receives the transmission signal on a receiving apparatus side. A hold signal that is connected to a demodulation unit that demodulates the data, and that holds the demodulated data in accordance with the timing of the demodulation processing that demodulates the transmission signal in the demodulation unit; And a video processing unit connected to the output unit for outputting a frequency component in the X-axis direction and a signal component demodulated in the Y-axis direction from the hold signal and the level increase signal. A digital transmission device characterized by the above-mentioned. In a digital transmission apparatus for transmitting a transmission signal modulated by a digital modulation method and mapped in two dimensions, and reproducing the transmission signal by identifying the received two-dimensional data, the transmission apparatus receives the transmission signal on a receiving apparatus side. Is connected to a demodulation unit that demodulates, from the data after demodulation in the demodulation unit, generates a level increase signal that constantly increases in level according to the timing of demodulation processing for demodulating the transmission signal in the demodulation unit, A digital transmission device comprising: a video processor for outputting a frequency component in an X-axis direction and a signal component demodulated in a Y-axis direction from demodulated data and the level increase signal.

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