JP4212594B2 - Multilevel semiconductor memory device, writing method thereof, and storage medium - Google Patents

Description

The present invention relates to a multilevel semiconductor memory device, a writing method and a reading method thereof, and a storage medium.

For example, a method using a Hamming code has been generally used as an error correction function of a code stored in a semiconductor memory device. In a semiconductor memory device using the Hamming code,
For example, when 4 information bits (m1, m2, m3, m4) are stored, 3 check bits (p1, p2, p3) are obtained by the encoder, and a total of 7 bits of information bits and check bits are stored. To do.

When the Hamming code stored in the semiconductor memory device is read, the read information (y1, y2, y3, y4, y5, y6, y7) is given to the decoder, and the error corrected information (m1, m2) , M3, m4). In such a semiconductor memory device, an error of up to 1 bit can be corrected in the read information (y1, y2, y3, y4, y5, y6, y7). For details, refer to, for example, Hideki Imai “Code Theory” (issued June 10, 1994 (5th edition)) published by the Institute of Electronics, Information and Communication Engineers.

Recently, as disclosed in Japanese Patent Laid-Open No. 6-195687, there is a multi-value semiconductor memory device that stores three or more values in one memory cell. In the multilevel semiconductor memory device, a plurality of threshold voltages are set. For example, in the case of a quaternary nonvolatile semiconductor memory, each memory cell has four threshold voltages (0V, 2V, 4V). , 6V), and 2 bits of information can be stored in one memory cell. In other words, memory
00, 01, 10, 11), the threshold voltages of the memory cells are 0V, 2V, 4V,
It is set to 6V.

Here, when an error correction function using a Hamming code is given to such a multilevel semiconductor memory device, conventionally, since each bit of a code string to be stored obtained by encoding is stored in order, Adjacent bits were stored in the same memory cell.

For example, information bits (m11, m21, m31, m41) and (m12, m22, m32)
, M42), check bits (p11, p21, p31) and (p12, p22, p32)
A case will be described in which these are stored in a multilevel memory cell. Conventionally, when storing a Hamming code consisting of these information bits and check bits in a multilevel memory cell, m11 and m21 are used.
, M31 and m41, p11 and p21, p31 and m12, m22 and m32, m42 and p12
, P22 and p32 were stored in order.

An example of how an error occurs in a multi-level semiconductor memory device will be described by taking the multi-level non-volatile memory described above as an example. Since an error occurs due to a change in threshold voltage, for example, “10” is “01”.
As shown, there is a very high probability that 2-bit information pairs will cause errors simultaneously.

That is, the error that occurs in the multilevel semiconductor memory device is a so-called burst error that occurs in a concentrated manner in a certain section of the code sequence corresponding to the number of values stored in one multilevel memory cell. It is. When such a burst error occurs, the storage state of one multilevel memory cell changes and a 2-bit error occurs. In this case, two or more errors occur in one Hamming code, and decoding cannot be performed correctly.

In addition to a method using a Hamming code, an error correction method for a multilevel semiconductor memory device is disclosed in
Although a method using a multi-element code as shown in Japanese Patent Laid-Open No. 0-163300 has been proposed, it is also considered that this method has a high probability of occurrence of an error in a multilevel semiconductor memory device as a burst error. There is a problem that the efficiency of error correction is poor.

In addition, the multi-level memory as described above has a problem that the number of read operations for one memory cell increases. A conventional reading method will be described with reference to the reading operation of the above four-value semiconductor memory device. When this semiconductor memory device receives a read command from the outside, it waits for input of an address. Since the input address is not a physical address corresponding to an actual memory cell but a logical address, the physical address is calculated from the input logical address.

Next, the threshold voltage of the memory cell designated by the calculated physical address is (0V
, 2V, 4V, 6V), and converts the data into 2-bit data. Specifically, for example, 1V, 3V, and 5V determination voltages are sequentially applied to the memory cells. In this case, if a current flows through the source / drain of the memory cell when the determination voltage of 1 V is applied, it is determined that the threshold voltage of the memory cell is 0 V, and data “00” is read out. On the other hand, 1V
In the case where no current flows, if a current flows at 3 V, the threshold voltage of the memory cell is 2
The data is recognized as V, and data of “01” is read out.

Furthermore, if current does not flow at 1V and 3V and current flows for the first time at 5V, the threshold voltage of the memory cell is found to be 4V, and data “10” is read out. Further, when no current flows at all voltages applied to the memory cell, it is found that the threshold voltage of the memory cell is 6V, and data “11” is read out. In the example described above, 1
Although four-value data, that is, 2-bit data is stored in one memory cell, it has been studied to store multi-value data.

However, the multi-level memory as described above has a problem that the number of read operations for one memory cell increases. For example, when four values are stored in one memory cell as described above, in the conventional four-value semiconductor memory device, as described above,
Regardless of the value of the input address, three read detection operations for specifying which of the four values the threshold voltage of the memory cell is always performed. Actually, 1V → 3
Read detection is performed by applying a voltage stepwise changing from V to 5 V, but the read detection operation is still required three times.

In view of this, the present inventors have disclosed a method for speeding up the read operation of a memory cell in Japanese Patent Application Laid-Open No. 7-201189. If this method is described in correspondence with the above-described quaternary semiconductor memory device, a voltage of 3 V is first applied to the memory cell, and the upper bit of the 2-bit data is determined depending on whether or not a current flows. In this case, if current flows, the upper bit is “0”.
If the current does not flow, the upper bit is “1”. Then the upper bits are “
If it is determined that the voltage is 0 ", if a voltage of 1V is further applied to the memory cell and a current flows, the 2-bit data in the memory cell is" 00 ". If the current does not flow For example, data is determined to be “01” and output, whereas if it is determined that the upper bit is “1”, a voltage of 5 V is further applied to the memory cell and a current flows. For example, if the 2-bit data of the memory cell is “10”, if no current flows, it is determined that the data is “11” and is output, as described in JP-A-7-201189. According to the read method, 2-bit data stored in one memory cell can be specified by two read operations.

However, even in the reading method described in Japanese Patent Application Laid-Open No. 7-201189, the threshold voltage of the memory cell is used regardless of the logical address, in other words, even when the logical address specifies, for example, the upper bit of the memory cell. Is one of the four values.

As described above, the conventional multilevel semiconductor memory device outputs data after completely specifying the stored contents of the memory cell in the read operation regardless of the input logical address, and therefore takes more time than necessary. There is a problem that the reading speed is inevitably limited.

In view of the above problems, it is a first object of the present invention to enable error correction to be performed efficiently even if multi-value information stored in one memory cell is lost.

It is a second object of the present invention to make it possible to read out frequently accessed data at high speed according to the input logical address and to further shorten the access time at the time of reading. .

The multilevel semiconductor memory device of the present invention is one of three or more different predetermined storage states.
A plurality of multi-level memory cells holding one and at least a first code and a second code encoded by an arbitrary encoding method, and a plurality of first values constituting the first code Among the plurality of second information bits constituting the information bit and the second code, the information bits of the same digit are stored in the corresponding multi-level memory cell as a pair, and stored in the corresponding multi-value memory cell. Rearrangement means for rearranging second information bits, voltage generation means for generating a predetermined voltage corresponding to the rearranged information bits, and the multi-value memory corresponding to the address information upon receiving address information Voltage applying means for applying the predetermined voltage to the cell.

In one aspect of the multilevel semiconductor memory device of the present invention, the rearranging means controls the number of bits stored in each multilevel memory cell according to the error correction capability of the encoding method.

In one aspect of the multilevel semiconductor memory device of the present invention, the rearranging means outputs m information bits when the number of bits stored in one of the plurality of multilevel memory cells is m.
The m codes having the code length n are rearranged as each row of the m × n array so as to be stored in one multilevel memory cell.

In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel memory cell is a nonvolatile semiconductor memory.

According to the present invention, there is provided a method for writing to a multilevel semiconductor memory device, comprising: a multilevel semiconductor memory device having a plurality of multilevel memory cells each holding one of three or more different predetermined memory states. A method of writing information bits, wherein at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first information bits constituting the first code, Among a plurality of second information bits constituting the second code, information bits of the same digit are 1
A first step of rearranging the first and second information bits so as to be stored in the corresponding multi-value memory cell in a set; and a predetermined voltage corresponding to the rearranged information bits. A second step of generating, and a third step of receiving address information and applying the predetermined voltage to the multilevel memory cell corresponding to the address information.

A storage medium according to the present invention is for writing information bits in a multilevel semiconductor memory device having a plurality of multilevel memory cells each holding one of three or more different predetermined storage states by a computer. A storage medium storing a program, and at least a first code and a second code encoded by an arbitrary encoding method, a plurality of first information bits constituting the first code; Among the plurality of second information bits constituting the second code,
A program for rearranging the first and second information bits is stored so that information bits of the same digit are stored as one set in one of the plurality of multilevel memory cells.

In one aspect of the storage medium of the present invention, the multi-value memory corresponding to the address information is generated by generating a predetermined voltage corresponding to the rearranged first and second information bits, receiving the address information, and A program for applying the predetermined voltage to the cell is stored.

The multi-value semiconductor memory device of the present invention is arranged corresponding to a conversion means for converting a logical address to a physical address and a physical address space including the physical address, and n (n ≧ 2).
) Components (X ₁ , X ₂ ,..., X _n ), a plurality of multi-value memory cells holding a 2 ⁿ -value storage state, and a logical address space including the logical address as the physical address space A determination unit that determines whether or not they match, and a determination unit that specifies the highest-order component X _{1 at a time according} to a predetermined determination value when it is determined that the logical address space matches the physical address space And output means for outputting the specified component X ₁ from the multi-level memory cell corresponding to the physical address among the plurality of multi-level memory cells.

In one aspect of the multilevel semiconductor memory device of the present invention, each multilevel memory cell includes at least one transistor, and the specifying unit generates a voltage corresponding to the determination value; A second means for outputting an address signal in response to the physical address; a third means for supplying the voltage to the multilevel memory cell corresponding to the physical address in response to the address signal; Fourth means for determining whether or not a current flows between the source and drain of the given transistor, and fifth means for specifying the highest-order component X _{1 based} on a determination result in the fourth means Including.

In an exemplary aspect of the multi-level semiconductor memory device of the present invention, the specific means, which is connected the one input terminal to the output portion of the multi-level memory cell, voltages corresponding to the component X ₁ of the uppermost And a voltage supply circuit connected to the other input terminal of the comparator and supplying a voltage corresponding to the predetermined determination value to the other input terminal. Based on the result, the topmost component X ₁ is specified.

In one aspect of the multilevel semiconductor memory device of the present invention, when it is determined that the logical address space does not match the physical address space, the specifying unit is configured to output the components (X ₁ , X _2).
,..., X _n ) are specified at most n times by a predetermined maximum of n different judgment values.

In one embodiment of the multilevel semiconductor memory device of the present invention, each multilevel memory cell includes at least one transistor, and the specifying unit generates n voltages corresponding to the n determination values. A first means for outputting an address signal given the physical address;
A current flows between the source and drain of the transistor to which the voltage is applied, and a third means for applying the voltage to the multi-level memory cell corresponding to the physical address in response to the address signal. A fourth means for applying a maximum of n kinds of voltages to the gate of the transistor in a predetermined order, and the components (X ₁ , X ₂ ,..., X _n by detecting the current.
And a fifth means for specifying.

In one aspect of the multilevel semiconductor memory device of the present invention, the specifying means has one input terminal connected to the output portion of each multilevel memory cell, and the components (X ₁ , X ₂ ,..., X _n ) and a voltage supply connected to the other input terminal of the comparator and supplying a voltage corresponding to the maximum of n determination values to the other input terminal. The highest-order component (X ₁ , X ₂ ,..., X _n ) is specified based on the determination result of the comparator.

The reading method of the multilevel semiconductor memory device of the present invention is arranged corresponding to the physical address space, and 2 ⁿ expressed by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A method of reading the component from a plurality of multi-value memory cells holding a storage state of a value, the first step of converting a logical address into a physical address included in the physical address space, and a logic including the logical address a second step address space determines whether matches the physical address space, if the logical address space is determined to match said physical address space, the uppermost the components X ₁ a predetermined the third step and the fourth scan to output the components X ₁ identified from the multilevel memory cell corresponding to the physical address of the plurality of multilevel memory cells by determination value identified in one Tsu and a flop.

In one aspect of the method for reading a multilevel semiconductor memory device of the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the second step Thereafter, the method further includes a fifth step of specifying the component (X ₁ , X ₂ ,..., X _n ) at maximum n times by a predetermined maximum n different determination values.

The reading method of the multilevel semiconductor memory device of the present invention is arranged corresponding to the physical address space, and 2 ⁿ expressed by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A method of reading a component from a plurality of multi-valued memory cells each having a storage state of values and including at least one transistor, wherein the logical address is converted into a physical address included in the physical address space. A step, a second step for determining whether a logical address space including the logical address matches the physical address space, and if it is determined that the logical address space matches the physical address space, Applying a predetermined determination voltage to the gate of the transistor, the third component X ₁ is specified according to whether or not a current flows between the source and drain of the transistor. And a step of outputting the identified component X ₁ from the multilevel memory cell corresponding to the physical address among the plurality of multilevel memory cells.
Steps.

In one aspect of the method for reading a multilevel semiconductor memory device of the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the second step Thereafter, n different determination voltages are applied to the gate of the transistor in a predetermined order up to n times until a current flows between the source and drain of the transistor, and the components (X ₁ , X ₂ ,..., X _{n are applied.} ) Is further included.

The reading method of the multilevel semiconductor memory device of the present invention is arranged corresponding to the physical address space, and 2 ⁿ expressed by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A method of reading a component from a plurality of multi-valued memory cells each having a storage state of values and including at least one transistor, wherein the logical address is converted into a physical address included in the physical address space. A step, a second step of determining whether or not a logical address space including the logical address matches the physical address space, and if it is determined that the logical address space matches the physical address space, compares the voltage with a predetermined determination voltage corresponding to the component X ₁ of the upper, the plurality and the third step of identifying the components X ₁ by comparison, the components X ₁ identified And a fourth step of outputting from the multilevel memory cell corresponding to the physical address of the multilevel memory cell.

In one aspect of the method for reading a multilevel semiconductor memory device of the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the second step after the components _{(X 1, X 2, ...} , X n) voltage and the component corresponding to the _{(X 1, X 2, ...} , X n) is compared with the voltage corresponding to each component of the comparison result Further includes a fifth step of identifying the components (X ₁ , X ₂ ,..., X _n ).

The storage medium of the present invention is arranged by a computer corresponding to the physical address space,
Stores a program for reading the component from a plurality of multi-valued memory cells holding a storage state of 2 ⁿ values expressed by n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A first step of converting a logical address into a physical address included in the physical address space, and determining whether the logical address space including the logical address matches the physical address space And a third step of specifying the highest-order component X _{1 at a time according} to a predetermined determination value when it is determined that the logical address space matches the physical address space. And a fourth step of outputting the component X ₁ from the multi-level memory cell corresponding to the physical address among the plurality of multi-level memory cells.

In an aspect of the storage medium of the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the component (X ₁ , X ₂ ,..., X _n ) is stored, which further includes a fifth step of specifying the maximum n times by a predetermined maximum n different determination values.

The storage medium of the present invention is arranged by a computer corresponding to the physical address space,
From a plurality of multi-valued memory cells that hold a storage state of 2 ⁿ values expressed by n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ), each having at least one transistor. A storage medium storing a program for reading the component, wherein the logical address is converted to a physical address included in the physical address space, and the logical address space including the logical address is the physical address. A second step of determining whether or not to match a space; and when it is determined that the logical address space matches the physical address space, a predetermined determination voltage is applied to the gate of the transistor, and the transistor source - a third step of identifying the components X ₁ the uppermost by whether current flows between the drain, the components X ₁ identified the plurality of multi Program and a fourth step of outputting from the multilevel memory cell corresponding to the physical address of the memory cell is stored.

In one aspect of the storage medium of the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the gate of the transistor is provided after the second step. N different judgment voltages are applied to the components (X ₁ , X _{2) in a} predetermined order up to n times until a current flows between the source and drain of the transistor.
,..., X _n ), a program further including a fifth step is stored.

The storage medium of the present invention is arranged by a computer corresponding to the physical address space,
From a plurality of multi-valued memory cells that hold a storage state of 2 ⁿ values expressed by n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ), each having at least one transistor. A storage medium storing a program for reading the component, wherein the logical address is converted to a physical address included in the physical address space, and the logical address space including the logical address is the physical address. A second step for determining whether or not the space coincides with a space, and when it is determined that the logical address space coincides with the physical address space, a voltage corresponding to the topmost component X ₁ and a predetermined determination voltage comparing the door, the corresponding a third step of specifying the component X ₁ by the comparison result, the components X ₁ identified in the physical address of the plurality of multilevel memory cells Program and a fourth step of outputting from the multilevel memory cell is stored.

In an aspect of the storage medium of the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the component (X ₁ , X ₂ ,..., X _n ) and the components (X ₁ , X ₂ ,
.., X _n ) are compared with the voltage corresponding to each component, and the component (X ₁ , X _n ,
A program that further includes a fifth step of specifying X ₂ ,..., X _n ) is stored.

A multilevel semiconductor memory device according to the present invention includes a plurality of multilevel memory cells, and each multilevel memory cell holds one of three or more different predetermined storage states. An information bit distribution means is provided that distributes and stores each bit constituting one code encoded by an arbitrary encoding method in the plurality of multi-level memory cells.

In one aspect of the multilevel semiconductor memory device of the present invention, the information bit distribution means determines the number of bits in the same code stored in one multilevel memory cell according to the error correction capability of the one code. Control.

In one aspect of the multi-level semiconductor memory device of the present invention, the information bit distribution means arranges codes to be distributed and stored in the plurality of multi-level memory cells, and an m × n array of m codes of code length n When the number of bits stored in the multilevel memory cell is m, m pieces of information arranged in each column of the array are stored in one of the multilevel memories.

In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel memory cell is a nonvolatile semiconductor memory.

The storage medium of the present invention stores a program for causing a computer to function as the information bit distribution means described above.

The multilevel semiconductor memory device writing method of the present invention includes a multilevel memory cell having a plurality of multilevel memory cells that hold three or more storage states of a code string encoded by an arbitrary encoding method. A method of writing to a semiconductor memory device, wherein the encoded 1 is encoded by the arbitrary encoding method
Each bit constituting one code is distributed and stored in a plurality of multilevel memory cells.

The storage medium of the present invention stores the above-described writing method of the multilevel semiconductor memory device so that it can be read from a computer.

The multi-value semiconductor memory device of the present invention comprises input means for inputting a logical address, conversion means for calculating a physical address from the logical address, a control gate and a charge storage layer, and corresponds to the physical address. A multi-value memory cell that holds a storage state of three or more values represented by components of two or more dimensions, and the multi-value memory cell corresponding to the physical address, and the input Control means for designating a component to be output from among the components stored in the multi-value memory cell selected according to the logical address inputted to the means; and the multi-value memory cell designated by the control means Output means for outputting the data of the component, and there is a determination value for specifying data of at least one of the components in one determination, and the input means When the input logical address is included in a partial space that has a one-to-one correspondence with the address space spanned by the physical address, the data of the component of the multilevel memory cell designated by the control means Is specified by the determination value, and this data is output from the output means.

In one example of the multilevel semiconductor memory device of the present invention, the multilevel memory cell has n-dimensional (
n ≧ 2) holds a storage state of 2 ⁿ values expressed by components (X ₁ , X ₂ ,..., X _n ), and a determination value for specifying at least the data of the X ₁ component in one determination together present, the multi-valued data of the logical address included in the partial space is stored in the X ₁ component, when the logical address included in the partial space is input to the input means, the corresponding among the storage state of the memory cell, and outputs the data of the X ₁ components identified by the determination value by the control means from said output means.

In one embodiment of the multilevel semiconductor memory device of the present invention, each determination value for specifying data of the X ₂ ,..., X _n component exists and an address space close to the address space A ₁ which is the partial space. a _2, ..., the data of the logical address included in a _n is the order of closeness to the address space a ₁ X _2, ..., are sequentially stored in the X _n components, the logical address that is input to said input means According to the address space of X _k (where k = 1,
2,..., N) component is specified by k determinations based on the respective determination values, and data of this X _k component is output from the output means.

In one embodiment of the multilevel semiconductor memory device of the present invention, the charge storage layer is a floating gate.

A multi-level semiconductor memory device reading method according to the present invention includes a multi-level memory cell that includes a control gate and a charge storage layer and is arranged corresponding to a physical address calculated from an input logical address. A reading method for a semiconductor memory device, wherein the multilevel memory cell holds a storage state of three or more values each represented by a two or more-dimensional component, and data of at least one of the components And the logical address input to the input means is included in a partial space that has a one-to-one correspondence with the address space spanned by the physical address. Depending on whether or not a current flows between the source / drain of the multi-level memory cell by applying a voltage of the determination value to the control gate of the multi-level memory cell. Identify and outputs the data of the components of the multi-level memory cell.

In one example of the reading method of the multilevel semiconductor memory device of the present invention, the multilevel memory cell is expressed by n-dimensional (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). 2 ⁿ value storage state is held, there is at least a determination value for specifying the data of the X ₁ component, and data of the logical address included in the partial space is stored in the X ₁ component. When the logical address included in the partial space is input to the input means, the X specified by the value among the storage states of the corresponding multilevel memory cell.
_One- component data is output from the output means.

In one example of the reading method of the multilevel semiconductor memory device of the present invention, X ₂ ,..., X _n
With each decision value that identifies the data components are present, the address space A ₂ in proximity to the address space A ₁ is the partial space, ..., the data of the logical address included in A _n is in the address space A ₁ The X ₂ components are sequentially stored in the order of X ₂ ,..., X _n , and X _k (where k = 1, 2, depending on the address space of the logical address input to the input means).
,..., N) component data is specified by k determinations based on the respective determination values, and this X _k component is output.

The storage medium of the present invention stores a program for causing a computer to execute the procedure of the reading method described above.

The multilevel semiconductor memory device of the present invention is one of three or more different predetermined storage states.
A plurality of multi-level memory cells holding the first storage means, and first encoding means for converting the first storage information into a first code value having at least two digits by an arbitrary encoding method; , Second storage means for converting the second stored information into a second code value having at least two digits by an arbitrary encoding method, and the same as the first and second code values Sorting means for generating two or more sets of code value information between digits as one set so as to be stored in the corresponding multi-value memory cell.

In one embodiment of the multilevel semiconductor memory device of the present invention, the first and second code values have the same number of digits.

In one aspect of the multilevel semiconductor memory device of the present invention, the arbitrary encoding method is an encoding method based on a binary system.

In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel memory cell has a control gate and a floating gate.

In an example of the multilevel semiconductor memory device according to the present invention, the multilevel memory cell includes an MNOS.
, Mask ROM, EEPROM, EPROM, PROM, or flash nonvolatile memory.

In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel semiconductor memory device further comprises a correction means for detecting and correcting an error occurring in the first and second stored information from the first and second code values. .

The multilevel semiconductor memory device of the present invention is one of three or more different predetermined storage states.
A plurality of multi-level memory cells that hold the data, encoding means for converting the input storage information into a code value having at least two digits by an arbitrary encoding method, and the encoding means The obtained code value is divided by an arbitrary number of digits to create at least two encoded information blocks, and the encoded information of the same digit of each encoded information block is set as one set to the multilevel memory cell And divided storage means for storing the data.

In one aspect of the multilevel semiconductor memory device of the present invention, the encoded information stored in each of the multilevel memory cells is read, and the code string comprising the encoded information according to the error correction capability of the encoding method Readout means for correcting and outputting the error is further included.

In one aspect of the multilevel semiconductor memory device of the present invention, the reading means reads at least predetermined bit information from each multilevel memory cell to create and output the code string.

In one aspect of the multilevel semiconductor memory device of the present invention, the multilevel memory cell can hold one of four different predetermined storage states, and the divided storage The means divides the code value into two encoded information blocks having the same number of digits, and stores the two encoded information of the same digit of each encoded information block as a set in the multilevel memory cell.

In one aspect of the multilevel semiconductor memory device of the present invention, the reading means outputs each of the two encoded information blocks as a redundant bit added to an information bit.

In one aspect of the multilevel semiconductor memory device of the present invention, the multilevel memory cell can hold one of eight different predetermined storage states, and the divided storage The means divides the code value into three encoded information blocks having the same number of digits, and stores the three encoded information of the same digit of each encoded information block as a set in the multilevel memory cell.

In one embodiment of the multilevel semiconductor memory device of the present invention, the reading means outputs each of the three encoded information blocks as a redundant bit added to an information bit.

In one aspect of the multi-level semiconductor memory device of the present invention, the reading means uses each information block formed by combining one encoded information block and two encoded information blocks as an information bit. The output is made with redundant bits added.

In one aspect of the multilevel semiconductor memory device of the present invention, the multilevel memory cell can hold one of 16 different predetermined storage states, and the divided storage The means divides the code value into four encoded information blocks having the same number of digits, and stores the four encoded information of the same digit in each encoded information block as a set in the multilevel memory cell.

In one embodiment of the multilevel semiconductor memory device of the present invention, the reading means outputs each of the four encoded information blocks as a result of adding redundant bits to information bits.

In one aspect of the multi-value semiconductor memory device of the present invention, the reading means includes 2 each.
Each of the information blocks formed by combining the two encoded information blocks is output as a redundant bit added to the information bit.

In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel memory cell has a control gate and a floating gate.

In an example of the multilevel semiconductor memory device according to the present invention, the multilevel memory cell includes an MNOS.
, Mask ROM, EEPROM, EPROM, PROM, or flash nonvolatile memory.

In one aspect of the multilevel semiconductor memory device of the present invention, the redundant bits are generated corresponding to each of the two encoded information blocks based on the two encoded information blocks, and the respective encoded The redundant bits are such that the sum of the information bits of the information block and the corresponding redundant bits is the number of bits of the coded sequence.

In one aspect of the multilevel semiconductor memory device of the present invention, the redundant bits are generated corresponding to each of the three encoded information blocks based on the three encoded information blocks, and The redundant bits are such that the sum of the redundant bits corresponding to the information bits of the information block is the number of bits of the coded sequence.

In one aspect of the multilevel semiconductor memory device according to the present invention, the redundant bits correspond to each of the three encoded information blocks by Hamming encoding based on the three encoded information blocks. Redundant bits are generated, a code string is generated by adding the first redundant bits corresponding to each of the three encoded information blocks, and an exclusive OR of all the bits included in each code string is calculated. Second redundant bits are generated corresponding to each code string, and the sum of the bits of each code string and the corresponding second redundant bits is the number of bits of the code string. is there.

In one aspect of the multilevel semiconductor memory device of the present invention, the redundant bit is formed by combining the one encoded information block and the two encoded information blocks based on the three encoded information blocks. The information block is generated corresponding to each of the information blocks, and the information block formed by combining the two encoded information blocks with the sum of the redundant bits corresponding to the information bits of the one encoded information block is divided. Sometimes the redundant bits are such that the information bits of each of the divided blocks and the sum of the corresponding redundant bits are the number of bits of the coded sequence.

In one aspect of the multilevel semiconductor memory device of the present invention, the redundant bits are generated corresponding to each of the four encoded information blocks based on the four encoded information blocks, and The redundant bits are such that the sum of the redundant bits corresponding to the information bits of the information block is the number of bits of the coded sequence.

In one aspect of the multilevel semiconductor memory device of the present invention, the redundant bits correspond to each of the four encoded information blocks by Hamming encoding based on the four encoded information blocks. Redundant bits are generated, a code string is generated by adding the first redundant bits corresponding to each of the four encoded information blocks, and an exclusive OR of all the bits included in each code string is calculated. Second redundant bits are generated corresponding to each code string, and the sum of the bits of each code string and the corresponding second redundant bits is the number of bits of the code string. is there.

In one aspect of the multilevel semiconductor memory device of the present invention, the redundant bit corresponds to each of the information blocks formed by combining the two encoded information blocks based on the four encoded information blocks. When each of the information blocks generated by combining the two encoded information blocks is divided into two, the sum of redundant bits corresponding to the information bits of each of the divided blocks is the encoded Redundant bits that are the number of bits in a column.

In the multilevel semiconductor memory device of the present invention, even if an error occurs in the multilevel information stored in one memory cell, information of the minimum number of bits that can be error corrected is only lost for one code. Thus, error correction can be performed efficiently.

According to another feature of the present invention, logical addresses are hierarchized into an address space having a high access speed and an address space having a relatively low access speed, and one-to-one correspondence with an address space spanned by physical addresses among the logical addresses. The corresponding partial space is defined as an address space with a high access speed. Then, data in the address space having a high access speed is stored in a specific component of the storage state of the multilevel memory cell, for example, the most significant bit. The data of this specific component is determined by one determination value.

When the input logical address is included in the partial space, the logical address designates the data of the specific component, and the data of the specific component can be immediately identified by one determination based on the determination value. Will be output. Therefore, by storing data with the highest access frequency in this specific component and storing data with a relatively low access frequency in the other components, it becomes possible to read the semiconductor memory device very efficiently.

As described above, according to the present invention, error correction can be performed efficiently even if multi-value information stored in one memory cell is lost.

In addition, according to another feature of the present invention, it is possible to read data with high access frequency at high speed according to the input logical address, and to greatly shorten the access time at the time of reading.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a multilevel semiconductor memory device, a writing method and a reading method thereof, and a storage medium according to the invention will be described with reference to the drawings.

FIG. 1 shows the main configuration of the multi-value storage EEPROM of this embodiment. In FIG. 1, a memory cell array 1 has a plurality of memory cells arranged in a matrix. As shown in FIG. 2, each memory cell constituting the memory cell array 1 is a floating gate type memory cell, and a drain 12 and a source 13 made of an n-type impurity diffusion layer are formed on the surface region of the p-type silicon substrate 11, respectively. A channel region 14 is formed between them.

A bit line 15 is connected to the drain 12 and a source line 16 is connected to the source 13. A tunnel insulating film 20 made of a SiO ₂ film having a thickness of about 10 nm is formed on the channel region 14, and a floating gate 17 made of low-resistance polysilicon is formed thereon.
Then, an interlayer insulating film 18 and a control gate (word line) 19 made of low-resistance polysilicon are sequentially formed.

The word lines 19 are connected to the decoder 2 along the column direction of the memory cell array 1, respectively.
On the other hand, the bit lines 15 are connected to the multiplexer 4 in the row direction. The source line 16 is grounded.

When writing data to the multi-value storage EEPROM of this embodiment configured as described above, the operation mode is set to the program mode. Then, write information is input via the input / output interface I / F 8 and an address is input via the input interface I / F 7. Since the input address is a logical address, the conversion circuit 9 converts it into a physical address.

Information input via the input / output interface I / F 8 is given to the signal control circuit 6,
The information bit distribution means 6a provided here rearranges information bits as will be described in detail later.

The input information on which the information bits have been rearranged is then supplied to the voltage generation and voltage control circuit 3 to generate a voltage corresponding to the information bits. The generated voltage is applied to the memory cell array 1 via the decoder 2, and a predetermined threshold voltage is set for each memory cell.

(First Embodiment of Writing Method)
The first embodiment of the writing method of the present invention will be specifically described below with reference to FIG.

In the multi-value storage EEPROM targeted in this embodiment, the threshold voltage of each memory cell corresponds to four bits of information (00, 01, 10, 11) stored (00, 01, 10, 11). 4,
6V) and uses a crossing method in which a code C having a code length n and a burst error correction capability L is crossed m times as a burst error correction code.

In rewriting by this apparatus, every time 8 bits of stored contents are received, this is converted to 4 × 2 bits of information bits (m11, m21, m31, m41) (m12, m22, m
32, m42), and 3 × 2 bits of redundant bits for inspection (p1) from this information bit
1, p21, p31) (p12, p22, p32).

And these information bits (m11, m21, m31, m41) (m12, m22,
m32, m42) and redundant bits (p11, p21, p31) (p12, p22, p32)
) To two code words (m11, m21, m31, m41, p11, p21, p31),
(M12, m22, m32, m42, p12, p22, p32) are generated.

The two code words generated in this way are given to the information bit distribution means 6a, and arranged in rows in a 2 × 7 array as shown in FIG. And in each of the seven memory cells,
m11 and m12, m21 and m22, m31 and m32, m41 and m42, p11 and p12,
The data is sequentially stored in a combination of p21 and p22 and p31 and p32.

That is, in FIG. 3, the upper bit of the memory cell 1 is m11 and the lower bit is m12. Similarly, the memory cell 2 has m21 and m22, the memory cell 3 has m31 and m32, and the memory cell 4
M41 and m42, p11 and p12 in the memory cell 5, p21 and p22 in the memory cell 6, and p31 and p32 in the memory cell 7, respectively.

As will be described in detail later, each code word can be corrected even if one error occurs, and the threshold voltage of the third memory cell changes as shown in FIG. Even if a burst error of length 2 occurs, there is one error for each codeword, so correction is possible. That is, the threshold voltage of one of the seven memory cells changes, for example, “01”
Even if a burst error occurs in which the stored content changes to “10”, correction is possible.

(Second Embodiment of Writing Method)
The second embodiment of the writing method of the present invention will be described below.

In the apparatus targeted by the writing method of this embodiment, the threshold voltage of each memory cell is stored as 3-bit information (000, 001, 010, 011, 100, 101, 110, 11
Corresponding to 1), it is an 8-value memory set to 8 values (0, 1, 2, 3, 4, 5, 6, 7V).

In rewriting by this apparatus, every time 12 bits of stored contents are received, this is converted into 4 × 3 bits of information bits (m11, m21, m31, m41) (m12, m22,
m32, m42) (m13, m23, m33, m43) and 3 bits from this information bit
X 3-bit redundant bits (p11, p21, p31) (p12, p22, p32) (p1
3, p23, p33).

And three code words (m11, m21, m31, m41, p11, p21, p31)
(M12, m22, m32, m42, p12, p22, p32) (m13, m23, m3
3, m43, p13, p23, p33) are arranged in each row of a 3 × 7 array, and as shown in FIG. 4, m11, m12, m13, m21, m22, m23, m
31 and m32 and m33, m41 and m42 and m43, p11 and p12 and p13, p21 and p
22 and p23, p31, p32 and p33 are stored.

That is, in FIG. 4, the upper bit of the memory cell 1 is m11 and the lower bit is m12. Similarly, the memory cell 2 has m21 and m22, the memory cell 3 has m31 and m32, and the memory cell 4
M41 and m42, the memory cell 5 contains m51 and m52, the memory cell 6 contains m61 and m62, and the memory cell 7 contains m71 and m72.

Each codeword can be corrected even if one error occurs. Therefore, as shown in FIG. 4, even if a burst error of length 3 occurs in the third memory cell, for example, On the other hand, since one error occurs, correction is possible. That is, even if a burst error occurs in which the memory voltage of “100” changes to “011”, for example, when the threshold voltage of one memory cell changes among the seven memory cells, correction is possible. It is.

  Subsequently, some modifications of the second embodiment of the writing method will be described.

-Modification 1-
In the apparatus targeted by the writing method of this embodiment, the threshold voltage of each memory cell is stored as 3-bit information (000, 001, 010, 011, 100, 101, 110, 11
Corresponding to 1), it is an 8-value memory set to 8 values (0, 1, 2, 3, 4, 5, 6, 7V). In the first modification, a case where a predetermined linear coding rule capable of error correction up to two errors in each bit constituting a code word is illustrated.

In the rewriting by this apparatus, first, every time the stored content receives a predetermined bit, for example, k bits, it is divided into three (k / 3) information bits. Then, redundant bits are obtained from each information bit, and a 14-bit code word (m11, m21, m31, m4) is obtained.
1, m51, m61, m71, m12, m22, m32, m42, m52, m62, m7
2) and 7-bit codewords (m13, m23, m33, m43, m53, m63, m73)
). That is, of the 14-bit and 7-bit codewords, a predetermined number of bits are information bits, and the rest are redundant bits for error correction.

Next, a 14-bit codeword (m11, m21, m31, m41, m51, m61, m7
1, m12, m22, m32, m42, m52, m62, m72) is a 7-bit code string (m11, m21, m31, m41, m51, m61, m71) (m12, m22, m
32, m42, m52, m62, m72). The code string a (m11, m2
1, m31, m41, m51, m61, m71) and code string b (m12, m22, m32)
, M42, m52, m62, m72) and one code word c (m13, m23, m33, m4)
3, m53, m63, m73) are arranged in each row of a 3 × 7 array, and as shown in FIG. 5, m11, m12 and m13, m21, m22 and m23, and m31 and m32 are arranged in seven memory cells, respectively. And m33, m41 and m42 and m43, m51 and m52 and m53, m61 and m62 and m63, and m71 and m72 and m73 are stored.

That is, in FIG. 5A, the upper bit of the memory cell 1 is m11 and the middle bit is m12.
, The lower bit is m13, and similarly, m21, m22, and m23 in the memory cell 2, m31, m32, and m33 in the memory cell 3, m41, m42, and m43 in the memory cell 4, and the memory cell 5
M51, m52 and m53, memory cell 6 with m61, m62 and m63, and memory cell 7 with m
71, m72, and m73 are stored.

The code strings a and b and the code word c can be corrected even if one error occurs. Therefore, as shown in FIG. 5A, for example, a burst error of length 3 is generated in the third memory cell. Even if it happens
For each codeword a, b and code string c, one error occurs. At this time, the code string a,
Since the code word composed of b has two errors, it can be corrected. That is,
Among the seven memory cells, the threshold voltage of one memory cell changes, for example, “100
Even if a burst error in which the stored content of “01” changes to “011” occurs, correction is possible.

-Modification 2-
In the apparatus targeted by the writing method of this embodiment, the threshold voltage of each memory cell is stored as 3-bit information (000, 001, 010, 011, 100, 101, 110, 11
Corresponding to 1), it is an 8-value memory set to 8 values (0, 1, 2, 3, 4, 5, 6, 7V). In the second modification, an example is shown in which, according to an encoding rule that can correct an error up to one error and can detect an error up to two errors in each bit constituting a code word. To do.

In rewriting by this apparatus, every time 12 bits of stored contents are received, this is converted into 4 × 3 bits of information bits (m11, m21, m31, m41) (m12, m22,
m32, m42) (m13, m23, m33, m43) and 3 × 3 redundant bits (p11, p21, p31) (p12, p) from this information bit by Hamming coding
22, p32) (p13, p23, p33).

Subsequently, three code strings (m11, m21, m31, m41, p11, p21, p31)
(M12, m22, m32, m42, p12, p22, p32) (m13, m23, m3
3, m43, p13, p23, p33), all 7 bits of EX-O
R is calculated, and each redundant bit q1, q2, q3 obtained as a result is added to each code string, and three code words (m11, m21, m31, m41, p11, p21, p31, q1)
(M12, m22, m32, m42, p12, p22, p32, q2) (m13, m23
, M33, m43, p13, p23, p33, q3).

Then, these three code words are arranged in each row of a 3 × 8 array, and as shown in FIG.
M11, m12, and m13, m21, m22, m23, and m31, respectively.
And m32 and m33, m41 and m42 and m43, p11 and p12 and p13, p21 and p22
And p23, p31, p32 and p33, q1, q2 and q3 are stored.

That is, in FIG. 5B, the upper bit of the memory cell 1 is m11 and the middle bit is m12.
, The lower bit is m13, and similarly, m21, m22, and m23 in the memory cell 2, m31, m32, and m33 in the memory cell 3, m41, m42, and m43 in the memory cell 4, and the memory cell 5
P11, p12, and p13, p21, p22, and p23 in the memory cell 6, and p in the memory cell 7, respectively.
31, p 32 and p 33, and q 1, q 2 and q 3 are stored in the memory cell 8.

Each codeword can be corrected even if one error occurs. Therefore, FIG.
As shown in FIG. 6, even if a burst error of length 3 occurs in the third memory cell, for example, one error is generated for each code word, and correction is possible. That is, the threshold voltage of one of the eight memory cells changes, and for example, the stored content of “100” becomes “011”.
Even if a burst error that changes to "" occurs, it is possible to correct it. Furthermore, although it seems to be extremely rare, for example, a burst error of length 1 to 3 occurred in another memory cell. In this case, there are two errors for at least one codeword. At this time, the two errors can be detected, and one of them can be corrected.

(Third embodiment of writing method)
Hereinafter, a third embodiment of the writing method of the present invention will be described.

In the target device in the writing method of this embodiment, the threshold voltage of each memory cell is stored as 4-bit information (0000, 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101,
11 values corresponding to 1110, 1111), for example, (0, 1, 1.25, 1.5, 1.7).
5, 2, 2.25, 2.5, 2.75, 3, 3.25, 3.5, 3.75, 4, 4.25
, 4.5V).

In rewriting by this apparatus, every time 16 bits of stored contents are received, this is converted into 4 × 4 information bits (m11, m21, m31, m41) (m12, m22,
m32, m42) (m13, m23, m33, m43) (m14, m24, m34, m4)
4) and 3 × 4 redundant bits (p11, p21, p31) are divided from this information bit.
) (P12, p22, p32) (p13, p23, p33) (p14, p24, p34)
Get.

And four code words (m11, m21, m31, m41, p11, p21, p31)
(M12, m22, m32, m42, p12, p22, p32) (m13, m23, m3
3, m43, p13, p23, p33) (m14, m24, m34, m44, p14, p
24, p34) are arranged in each row of a 4 × 7 array, and as shown in FIG. 6, m11, m12, m13, and m14, m21, m22, m23, and m24, m31 and m32, respectively, are arranged in seven memory cells. m33 and m34, m41, m42, m43 and m44, p11 and p12 and p13 and p14, p21 and p22 and p23 and p24, and p31 and p32 and p33 and p34 are stored.

That is, in FIG. 6, the first bit of the memory cell 1 is m11, the second bit is m12, the third bit is m13, and the fourth bit is m14. Similarly, the memory cell 2 has m21, m22 and m14.
23 and m24, memory cell 3 with m31, m32, m33 and m34, and memory cell 4 with m41.
, M42, m43 and m44, p11, p12, p13 and p14 in the memory cell 5, p21, p22, p23 and p24 in the memory cell 6, and p31, p32, p33 and p3 in the memory cell 7.
4 is stored.

Each code string can be corrected even if one error occurs. Therefore, even if a burst error of length 4 occurs in the third memory cell, for example, as shown in FIG. On the other hand, since one error occurs, correction is possible. That is, the threshold voltage of one of the seven memory cells changes, and for example, the stored content of “1000” becomes “0111”.
Even if a burst error that changes to 1 occurs, correction is possible.

  Subsequently, some modified examples of the third embodiment of the writing method will be described.

-Modification 1-
In the target device in the writing method of this embodiment, the threshold voltage of each memory cell is stored as 4-bit information (0000, 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101,
11 values corresponding to 1110, 1111), for example, (0, 1, 1.25, 1.5, 1.7).
5, 2, 2.25, 2.5, 2.75, 3, 3.25, 3.5, 3.75, 4, 4.25
, 4.5V). In this modified example, a case where a predetermined linear coding rule capable of error correction up to two errors in each bit constituting a code word is illustrated.

In rewriting by this apparatus, first, every time a stored content receives a predetermined bit, for example, p bits, it is divided into four (p / 3) bits of information bits. Then, redundant bits are obtained from each information bit, and two 14-bit code words (m11, m21, m31) are obtained.
, M41, m51, m61, m71, m12, m22, m32, m42, m52, m62
, M72) (m13, m23, m33, m43, m53, m63, m73, m14, m2
4, m34, m44, m54, m64, m74). That is, among these 14-bit code words, a predetermined number of bits are information bits, and the rest are redundant bits for error correction.

Next, each 14-bit codeword (m11, m21, m31, m41, m51, m61, m
71, m12, m22, m32, m42, m52, m62, m72) (m13, m23,
m33, m43, m53, m63, m73, m14, m24, m34, m44, m54,
m64, m74) is a 7-bit code string (m11, m21, m31, m41,
m51, m61, m71) (m12, m22, m32, m42, m52, m62, m72)
) And (m13, m23, m33, m43, m53, m63, m73) (m14, m24
, M34, m44, m54, m64, m74). And each code string is 4 × 7
Arranged in each row of the array, and as shown in FIG.
12 and m13 and m14, m21 and m22 and m23 and m24, m31 and m32 and m33 and m
34, m41, m42, m43, m44, m51, m52, m53, m54, m61, m
62, m63 and m64, m71, m72, m73 and m74 are stored.

That is, in FIG. 7A, the first bit of the memory cell 1 is m11 and the second bit is m12.
The third-order bit is m13 and the fourth-order bit is m14. Similarly, in the memory cell 2, m21 and m2
2 and m23 and m24, memory cell 3 with m31, m32 and m33 and m34, memory cell 4 with m41, m42 and m43 and m44, memory cell 5 with m51, m52 and m53 and m54, memory cell 6 with m61 and m62 and m63 and m64, and memory cell 7 includes m71, m72 and m73
And m74 are stored.

Each code string can be corrected even if one error occurs. Therefore, as shown in FIG. 7, even if a burst error of length 4 occurs in the third memory cell, for example, On the other hand, there is one error, and at this time, there are two errors for each codeword composed of two code strings, so correction is possible. That is, even if a burst error occurs in which the memory voltage of “1000” changes to “0111”, for example, when the threshold voltage of one memory cell changes among the seven memory cells, correction is possible. It is.

-Modification 2-
In the target device in the writing method of this embodiment, the threshold voltage of each memory cell is stored as 4-bit information (0000, 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101,
11 values corresponding to 1110, 1111), for example, (0, 1, 1.25, 1.5, 1.7).
5, 2, 2.25, 2.5, 2.75, 3, 3.25, 3.5, 3.75, 4, 4.25
, 4.5V). In this modification, an example is shown in which, according to an encoding rule that can correct an error up to one error and can detect an error up to two errors in each bit constituting a code word. .

In rewriting by this apparatus, every time 16 bits of stored contents are received, this is converted into 4 × 4 information bits (m11, m21, m31, m41) (m12, m22,
m32, m42) (m13, m23, m33, m43) (m14, m24, m34, m4)
4) and 3 × 4 redundant bits (p) from this information bit by Hamming coding.
11, p21, p31) (p12, p22, p32) (p13, p23, p33) (p1
4, p24, p34).

Subsequently, four code strings (m11, m21, m31, m41, p11, p21, p31)
(M12, m22, m32, m42, p12, p22, p32) (m13, m23, m3
3, m43, p13, p23, p33) (m14, m24, m34, m44, p14, p
24, p34), EX-OR of all 7 bits is calculated, and the resulting redundant bits q1, q2, q3, q4 are added to each code string, and four codewords are obtained. (M11, m21, m31, m41, p11, p21, p31, q1) (m12, m22
, M32, m42, p12, p22, p32, q2) (m13, m23, m33, m43)
, P13, p23, p33, q3) (m14, m24, m34, m44, p14, p24
, P34, q4).

Then, these four code words are arranged in each row of a 4 × 8 array, and as shown in FIG.
M11, m12, m13, and m14, m21, m22, and m23, respectively.
And m24, m31, m32, m33 and m34, m41, m42, m43 and m44, p11
, P12, p13, p14, p21, p22, p23, p24, p31, p32, p33
And p34, q1, q2, q3 and q4 are stored.

That is, in FIG. 7B, the first bit of the memory cell 1 is m11 and the second bit is m12.
The third-order bit is m13 and the fourth-order bit is m14. Similarly, in the memory cell 2, m21 and m2
2 and m13 and m14, m31, m32, m33 and m34 in the memory cell 3, m41, m42, m43 and m44 in the memory cell 4, m51, m52, p13 and p14 in the memory cell 5, and m61 and m62 in the memory cell 6 p23 and p24, and memory cell 7 includes m71, m72 and p33
And p34, and q1, q2, q3, and q4 are stored in the memory cell 8.

Each codeword can be corrected even if one error occurs. Therefore, FIG.
As shown in FIG. 6, even if a burst error of length 4 occurs in the third memory cell, for example, one error is generated for each code word, and correction is possible. That is, the threshold voltage of one memory cell among the eight memory cells changes, and for example, the stored content of “1000” becomes “01”.
Even if a burst error that changes to 11 ″ occurs, correction is possible. Furthermore, although it seems to be extremely rare, for example, a burst error of length 1 to 4 occurs in another memory cell. In this case, there are two errors for at least one codeword. At this time, the two errors can be detected, and one of them can be corrected.

In addition to the encoding methods shown in the respective modifications of the second and third embodiments of the writing method, there are methods that are considered useful. For example, 56 bits of “0” data are first added to 64 original data to obtain a total of 120 bits of information bits. Subsequently, a 127-bit Hamming code is created from 120 information bits. Subsequently, EX-OR of all 127 bits is calculated, and an additional 128-bit code is obtained from the result. Thereafter, the previously added 56-bit “0” is removed to obtain a 72-bit codeword. In this encoding method, error correction is performed for up to one error in each bit constituting a code word, and error detection is possible for up to two errors. The SEC / DED code ( single-er
error-correcting / double-error-detecting co
de) is frequently used.

Next, a specific example in which correction is possible even if one error occurs in one codeword will be described. Table 1 below shows a Hamming code in which 3 redundant bits are added to 4 information bits.

In this code, the first, second and fourth digits are redundant bits, and (1, 3, 5, 7), (2, 3, 6
, 7) and (4, 5, 6, 7), the redundant bits are determined so that the parity becomes even parity. For example, when the code “0111100” corresponding to the decimal number “12” is written and an error occurs and “0101100” is read out, as shown in Table 1, two digits with errors are displayed. Since it can be obtained as a decimal number (011 in this case), even if an error occurs, it can be easily and reliably corrected.

This code can be extended to a case where the number of information bits is larger, and the number of redundant bits m required for n information bits is expressed by the following equation.
2 ^m = n + m + 1 (1 set)

In the above description, the case where the present invention is applied to a nonvolatile memory device having a floating gate type memory cell has been described as an example. However, as a memory cell for performing multi-value storage, a floating gate type memory cell is used. However, the MNOS type may be used. In addition to the EEPROM, the present invention also provides a mask for obtaining a memory state by changing the threshold value by controlling the amount of impurities ion-implanted into the channel region of the field effect transistor, in addition to the EEPROM and PROM. It can also be applied to ROM. Moreover, although the case of 4 value and 8 value was mentioned as an example, it is not limited to this value by any means.

In addition, the crossing method has been described as an example of a method for obtaining an error correction code, but any method other than the crossing method may be used as long as the error correction code can correct a burst length error according to the amount of information stored in the memory cell. It may be a cyclic code or a shortened cyclic code.

Next, a preferred embodiment of the reading method of the present invention will be described in detail with reference to the drawings.

(First Embodiment of Reading Method)
First, a first embodiment of the reading method of the present invention will be described. In the first embodiment, a multi-value storage EEPROM as a semiconductor memory device and a reading method thereof are exemplified.

During the reading operation, first, a logical address signal is input from the outside to the conversion circuit 9 via the input I / F 7, and a physical address signal corresponding to an actual memory cell is calculated from the logical address signal. Subsequently, this physical address signal is input to the signal control circuit 6. The signal control circuit 6 determines the word line 19 and the bit line 15 to be selected according to the input physical address signal, and commands the result to the decoder 2 and the multiplexer 4. In response to this instruction, the decoder 2 selects the word line 19 and the multiplexer 4 selects the bit line 15.

Further, the signal control circuit 6 determines the magnitude of the voltage to be applied to the control gate 19 of the selected memory cell, and instructs the voltage control circuit 3 of the result. The voltage control circuit 3 includes a decoder 2
A predetermined voltage is applied to the selected word line 19 via. On the other hand, a predetermined voltage is applied to the selected bit line 15 by the multiplexer 4. Whether or not a current flows through the selected bit line 15 is determined by the threshold state of the selected memory cell.

The current state of the selected bit line 15 is transmitted from the multiplexer 4 to the sense amplifier 5. The sense amplifier 5 detects the presence / absence of a current in the selected bit line 15 and transmits the result to the signal control circuit 6. The signal control circuit 6 determines the next voltage to be applied to the control gate 19 of the selected memory cell based on the detection result of the sense amplifier 5 and instructs the voltage control circuit 3 of the result. The signal control circuit 6 outputs the storage data of the selected memory cell finally obtained by repeating the above procedure via the output I / F 8.

FIG. 8 shows a flowchart of the reading method according to the first embodiment. In the first embodiment, a four-value multi-value storage EEPROM having a storage capacity of 8 megabits is illustrated. This 4-value multi-value storage EEPROM is [00 0000] to [7F in hexadecimal notation.
FFFF] logical address space and [00 0000] to [3F FFFF] physical address space. In addition, each memory cell has 2-bit (= 4 values) data (
00, 01, 10, 11) are stored, and threshold voltages of (0V, 2V, 4V, 6V) are set in each memory cell in correspondence with these data.

Then, when the physical address of a predetermined memory cell is Ap, this memory cell has the data of the logical address Ap in the upper bits and the logical address (Ap + [40 0000]) in the lower bits of each component of 2 bits. It is designed to memorize data.

In other words, during the data rewrite operation, [00 0000] to [3F FF
When the logical address Al of FF] and the data to be stored (0 or 1) are designated, the upper bits of the memory cells existing at the physical address Al are rewritten to the designated data.

On the other hand, during the data rewrite operation, [40 0000] to [7F FFFF
When the logical address Al and the data to be stored (0 or 1) are designated, the lower bits of the memory cells existing at the physical address (Al- [40 0000]) are rewritten to the designated data.

First, a read command is received from the outside (step S1), and a logical address signal is input I / O.
When input to F7 (step S2), the signal control circuit 6 indicates that the logical address signal is [0.
It is determined whether it is 0 0000] to [3F FFFF] (step S3).

Here, when the logical address signal is [00 0000] to [3F FFFF], the logical address matches the physical address, and the data for which reading is requested is the upper bit of the two bits. (Step S4). In this case, a determination voltage of 3 V is applied to the control gate 19 of the selected memory cell, and it is detected through the selected bit line 15 and the sense amplifier 5 whether or not a current flows between the drain 12 and the source 13 (step S5).

In step S5, when a current flows between the drain 12 and the source 13 of the selected memory cell, that is, when the selected memory cell becomes conductive, the threshold voltage of the memory cell is either 0V or 2V. Therefore, it is determined that the upper bit is “0” among the components of the storage state of this memory cell, and this data is immediately output from the output I / F 8 (step S6).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S5, the threshold voltage of this memory cell is either 4V or 6V. Of these, it is determined that the upper bit is “1”, and this data is immediately output from the output I / F 8 (step S7).

In step S3, the logical address signal input to the input I / F 7 is [40 0.
000] to [7F FFFF], the logical address does not match the physical address, the physical address = (logical address− [40 0000]), and the data requested to be read out of 2 bits (Step S8).
In this case, a determination voltage of 3 V is applied to the control gate 19 of the selected memory cell, and the drain 12−
Whether or not a current flows between the sources 13 is detected through the selected bit line 15 and the sense amplifier 5 (step S9).

In step S9, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is either 0V or 2V. The voltage control circuit 3 is instructed to apply a determination voltage of 1 V to the control gate 19 of the selected memory cell (step S10).

In step S10, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 0 V, and the lower order of the components of the storage state of the memory cell. It is determined that the bit is “0”, and this data is output to the output I / F 8
(Step S11).

On the other hand, when no current flows between the drain 12 and the source 13 of the selected memory cell in step S10, the threshold voltage of the memory cell is 2 V, and among the components of the storage state of the memory cell, It is determined that the lower bit is “1”, and this data is output as I / O
Output from F8 (step S12).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S9, the threshold voltage of the memory cell is either 4V or 6V. 6 instructs the voltage control circuit 3 to apply a determination voltage of 5 V to the control gate 19 of the selected memory cell (step S13).

In step S13, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 4V. It is determined that the bit is “0”, and this data is output to the output I / F 8
(Step S12).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S13, the threshold voltage of the memory cell is 6V, and among the storage state components of the memory cell, It is determined that the lower bit is “1”, and this data is output as I / O
Output from F8 (step S13).

Here, referring to FIG. 1 and FIG. 9, whether or not a current flows between the drain 12 and the source 13 by applying the determination voltage of 1, 3 or 5 V to the control gate 19 of the selected memory cell in the reading method. A method of determining the will be described.

For example, in step 4 of FIG. 8, when the signal control circuit 6 receives the physical address from the conversion circuit 9 and finds that the data requested to be read is the upper bit, the control gate 19 of the selected memory cell. Is determined to be 3 V, and the result is transmitted to the voltage control circuit 3. As shown in FIG. 9, the voltage control circuit 3 includes a 1V reference voltage generation circuit 3a.
A reference voltage generating circuit 3b of 3V and a reference voltage generating circuit 3c of 5V are provided. In this example, the reference voltage generating circuit 3b generates a voltage of 3V and outputs it to the switch circuit 55.

Further, the signal control circuit 6 determines a word line to be selected according to the input physical address signal, and transmits the result to the decoder 2. In response to this, the decoder 2 outputs a decode signal to the switch circuit 55.

The switch circuit 55 that has received the reference voltage of 3V and the decode signal outputs 3 to the word line to be selected.
A reference voltage of V is given. Whether the current flows between the drain 12 and the source 13 of the memory cell 1a to be selected in the cell array 1 is determined by the sense amplifier 5. Sense amplifier 5
Compares the voltage from the memory cell 1 a with a predetermined voltage from the reference voltage generation circuit 56 and transmits the result to the signal control circuit 6.

Based on the detection result of the sense amplifier 5, the signal control circuit 6 determines the voltage 1V or 5V to be applied subsequently to the memory cell 1a and transmits it to the voltage control circuit 3. Then, the signal control circuit 6 outputs the storage data of the finally obtained memory cell 1a via the output I / F 8.

As described above, in the first embodiment, the logical address [00 0000] to
The address space A ₁ (logical address [00
0000] to [3F FFFF]) and an address space A ₂ ( ₂
The logical addresses [40 0000] to [7F FFFF]) are hierarchized, and the physical addresses [00 0000] among the logical addresses [00 0000] to [7F FFFF] are arranged.
] To [3F FFFF] address space A having a one-to-one correspondence (logical address [00 0000] to [3F FFFF]).
_Set to ₁ . Then, the data of the address space A ₁ is stored in a specific component of the memory state of the memory cell, here the upper bit.

The input logical address is included in the partial space (logical address [00 000
0] to [3F FFFF]), this logical address designates the upper bit data, and the upper bit data can be immediately found and output by one determination based on the determination voltage of 3V. It will be. In this case, the reading speed is approximately doubled as compared with the case where each threshold voltage is checked with all the determination voltages. Therefore, by storing the data with the highest access frequency in the upper bits and storing the data with a relatively low access frequency in the lower bits, the operator (programmer) has a single high-speed storage device. As a result, the multi-value storage EEPROM can be read very efficiently.

Note that data and programs that are preferably stored in the multi-value storage EEPROM include, for example, a BIOS of a computing device with a high access frequency, and a document file with a relatively low access frequency. In this case, the former may be stored in the high-order bits having a high access speed and the latter in the low-order bits having a relatively low access speed.

(Second Embodiment of Reading Method)
Next, a second embodiment of the reading method of the present invention will be described. In this embodiment, as in the first embodiment, a multi-value storage EEPROM and its reading method are exemplified as a semiconductor memory device. The main configuration of the multi-value storage EEPROM is the same as that of the first embodiment, but the multi-value storage EEPROM is different from the first embodiment in that the multi-value storage EEPROM has an 8-value storage capacity of 12 megabits. In addition, about the component similar to the multi-value storage EEPROM of 1st Embodiment, the same code | symbol is described and description is abbreviate | omitted.

FIG. 10 shows a flowchart of a reading method according to the second embodiment. In the second embodiment, an 8-value multi-value storage EEPROM having a storage capacity of 12 megabits is illustrated. This 8-value multi-value storage EEPROM is [00 0000] to [B] in hexadecimal notation.
F FFFF] logical address space and [00 0000] to [3F FFFF]
Physical address space. Each memory cell stores 3-bit (= 8 values) data (000, 001, 010, 011, 100, 101, 110, 111), and each memory cell corresponds to these data. (0V, 1V, 2V, 3V, 4V, 5V
, 6V, 7V) are set.

When the physical address of a predetermined memory cell is Ap, the memory cell stores the data of the logical address Ap in the most significant bit among the components of 3 bits, and the logical address (Ap + [ 40 0000]), and the logical address (Ap + [80 0000]) is stored in the least significant bit.

In other words, in the data rewrite operation, [00 0000] to [3F FFF
When the logical address Al of F] and the data to be stored (0 or 1) are designated, the most significant bit of the memory cell present at the physical address Al is rewritten to the designated data.

In the data rewrite operation, [40 0000] to [7F FFFF]
When the logical address Al and the data to be stored (0 or 1) are specified, the physical address (
Al− [40 0000]), the middle bit of the memory cell is rewritten to the designated data.

Further, in the data rewrite operation, [80 0000] to [BF FFFF
When the logical address Al and the data to be stored (0 or 1) are designated, the least significant bit of the memory cell existing at the physical address (Al− [80 0000]) is rewritten to the designated data.

First, a read command is received from the outside (step S21), and a logical address signal is input I
When the signal is input to / F7 (step S22), the signal control circuit 6 determines whether the logical address signal is [00 0000] to [3F FFFF] (step S23).
).

Here, when the logical address signal is [00 0000] to [3F FFFF], the logical address matches the physical address, and the data for which reading is requested is the most significant bit of the 3 bits. (Step S24). In this case, a determination voltage of 3.5 V is applied to the control gate 19 of the selected memory cell, and it is detected through the selected bit line 15 and the sense amplifier 5 whether or not a current flows between the drain 12 and the source 13 (step S25). ).

In step S25, when a current flows between the drain 12 and the source 13 of the selected memory cell, that is, when the selected memory cell is turned on, the threshold voltage of this memory cell is 0V, 1V, 2V, Since the 3-bit data specified by these threshold voltages is “000”, “001”, “010”, and “011”, respectively, the storage state of this memory cell is 3V. Among the components, it is determined that the most significant bit is “0”, and this data is immediately output from the output I / F 8 (step S26).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S25, the threshold voltage of this memory cell is any one of 4V, 5V, 6V, and 7V. The 3-bit data specified by the voltage is “100”, “
Since it is 101 ”,“ 110 ”, and“ 111 ”, it is determined that the most significant bit is“ 1 ”among the components of the storage state of this memory cell, and this data is immediately output from the output I / F 8 (Step S27).

In step S23, the logical address signal input to the input I / F 7 is [00.
If it is not [0000] to [3F FFFF], the input logical address signal is [4].
It is determined whether it is 00000] to [7F FFFF] (step S28).

Here, when the logical address signal is [40 0000] to [7F FFFF], the logical address does not coincide with the physical address, and physical address = (logical address− [40
0000]), it can be seen that the data requested to be read is the middle bit of the three bits (step S29). In this case, the control gate 19 of the selected memory cell
Is applied with a determination voltage of 3.5 V, and whether or not a current flows between the drain 12 and the source 13 is determined.
Detection is performed through the selected bit line 15 and the sense amplifier 5 (step S30).

In step S30, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is one of 0V, 1V, 2V, and 3V. Here, the 3-bit data specified by the threshold voltages of 0V and 1V is “000”, “001”.
The middle bits are both “0”, the 3-bit data specified by the threshold voltages of 2V and 3V are “010” and “011”, and both the middle bits are “ Therefore, in order to determine this middle bit, the signal control circuit 6 commands the voltage control circuit 3 to apply a determination voltage of 1.5 V to the control gate 19 of the selected memory cell (step S1). S
31).

In step S31, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 0V or 1V. Of the components of the storage state of the memory cell, The middle bit is determined to be “0”, and this data is output from the output I / F 8 (step S32).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S31, the threshold voltage of the memory cell is 2V or 3V, and the storage state component of this memory cell is Among these, it is determined that the middle bit is “1”, and this data is output from the output I / F 8 (step S33).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S30, the threshold voltage of the memory cell is any one of 4V, 5V, 6V, and 7V. Here, the 3-bit data specified by the threshold voltages of 4V and 5V is “1”.
00 and 101 and both middle bits are “0”, and the 3-bit data specified by 6V and 7V threshold voltages is “010” and “011”. Both of the bits are “1.” Therefore, in order to determine the middle bit, the signal control circuit 6 applies a determination voltage of 5.5 V to the control gate 19 of the selected memory cell. (Step S34).

In step S34, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 4V or 5V. Of the components of the storage state of the memory cell, The middle bit is determined to be “0”, and this data is output from the output I / F 8 (step S32).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S34, the threshold voltage of the memory cell is 6V or 7V. Among these, it is determined that the middle bit is “1”, and this data is output from the output I / F 8 (step S33).

In step S28, the logical address signal input to the input I / F 7 is [40].
If it is not [0000] to [7F FFFF], the logical address signal is [80 00].
00] to [BF FFFF], that is, physical address = (logical address− [80
0000]), it can be seen that the data requested to be read is the least significant bit of the three bits (step S35). In this case, the control gate 19 of the selected memory cell
Is applied with a determination voltage of 3.5 V, and whether or not a current flows between the drain 12 and the source 13 is determined.
Detection is performed through the selected bit line 15 and the sense amplifier 5 (step S36).

In step S36, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is any one of 0V, 1V, 2V, and 3V. The 3-bit data specified by voltage is “000” and “001”, respectively.
"0", "010", and "011", the least significant bit cannot be specified at this stage. Therefore, in order to specify the least significant bit, the signal control circuit 6 first determines the control gate of the selected memory cell. The voltage control circuit 3 is commanded to apply a determination voltage of 1.5 V to 19 (step S37).

In step S37, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is 0V or 1V, and 3 bits specified by these threshold voltages. This data is “000” or “001”. Therefore, in order to specify the least significant bit, the signal control circuit 6 applies 0.5 to the control gate 19 of the selected memory cell.
The voltage control circuit 3 is commanded to apply the determination voltage of V (step S38).

In step S38, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 0 V. Of the components of the storage state of the memory cell, It is determined that the lower bit is “0”, and this data is output to the output I / F.
8 (step S39).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S38, the threshold voltage of the memory cell is 1V, and among the storage state components of the memory cell, It is determined that the least significant bit is “1”, and this data is output as I
Output from / F8 (step S40).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S37, the threshold value of the memory cell is 2V or 3V, which is designated by each of these threshold voltages. The 3-bit data is “010” or “011”.
Therefore, in order to specify the least significant bit, the signal control circuit 6 instructs the voltage control circuit 3 to apply a determination voltage of 2.5 V to the control gate 19 of the selected memory cell (step S41).
).

In step S41, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 2V. Of the components of the storage state of the memory cell, It is determined that the lower bit is “0”, and this data is output to the output I / F.
8 (step S39).

On the other hand, in step S41, when no current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 3V, and among the components of the storage state of the memory cell, It is determined that the lowest bit is “1”, and this data is output as I / O.
Output from F8 (step S40).

When no current flows between the drain 12 and the source 13 of the selected memory cell in step S36, the threshold value of the memory cell is any one of 4V, 5V, 6V, and 7V. Each of the 3-bit data specified by the threshold voltage is “100”.
”,“ 101 ”,“ 110 ”, and“ 111 ”, the least significant bit cannot be specified yet at this stage, so the signal control circuit 6 first selects the selected memory to identify the least significant bit. The voltage control circuit 3 is commanded to apply a determination voltage of 5.5 V to the control gate 19 of the cell (step S42).

In step S42, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is 4V or 5V, and 3 bits specified by these threshold voltages. This data is “100” or “101”. Therefore, in order to specify the least significant bit, the signal control circuit 6 applies 4.5 to the control gate 19 of the selected memory cell.
The voltage control circuit 3 is commanded to apply the determination voltage of V (step S43).

In step S43, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 4V. Of the components of the storage state of the memory cell, It is determined that the lower bit is “0”, and this data is output to the output I / F.
8 (step S39).

On the other hand, when no current flows between the drain 12 and the source 13 of the selected memory cell in step S43, the threshold voltage of the memory cell is 5V, and among the components of the storage state of the memory cell, It is determined that the least significant bit is “1”, and this data is output as I
Output from / F8 (step S40).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S42, the threshold value of the memory cell is 6V or 7V, which is designated by each of these threshold voltages. The 3-bit data is “110” or “111”.
Therefore, in order to specify the least significant bit, the signal control circuit 6 instructs the voltage control circuit 3 to apply a determination voltage of 6.5 V to the control gate 19 of the selected memory cell (step S44).
).

In step S44, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 6V. It is determined that the lower bit is “0”, and this data is output to the output I / F.
8 (step S39).

On the other hand, when no current flows between the drain 12 and the source 13 of the selected memory cell in step S44, the threshold voltage of the memory cell is 7 V, and among the components of the storage state of the memory cell, It is determined that the least significant bit is “1”, and this data is output as I
Output from / F8 (step S40).

As described above, in the second embodiment, the logical address [00 0000] to
[BF FFFF] is hierarchized into an address space having a high access speed and an address space having a relatively low access speed. Here, an address space having a high access speed is designated as address space A.
₁ (logical address [00 0000] to [3F FFFF]), the address space having a relatively slow access speed is further subdivided, and the address space having the fastest access speed after the address space A ₁ is address space A ₂ (logical address). [40 0000] to [BF
FFFF]), and the address space having the fastest access speed after the address space A ₂ is hierarchized as the address space A ₃ (logical addresses [40 0000] to [BF FFFF]).

Of the logical addresses [00 0000] to [7F FFFF], the physical address [0
A partial space (logical address [00 0000] to [3F FFFF]) corresponding to the address space spanned by 0 0000] to [3F FFFF] is defined as an address space A ₁ having a high access speed. Then, the data of the address space A ₁ is stored in a specific component of the storage state of the memory cell, here, the most significant bit. Then, the address space A _{1 is} stored in the middle bit.
Fast address space A ₂ data access speed next to stores each access speed faster address space A ₃ of data next to the least significant bit in the address space A _2.

The input logical address is included in the partial space (logical address [00 000
0] to [3F FFFF]), this logical address designates the most significant bit data, and the most significant bit data is immediately known by a single determination with a determination voltage of 3.5V. Will be output. The input logical address is not included in the partial space, but is included in an address space close to the partial space (logical address [4
0 0000] to [7F FFFF]), this logical address designates the middle bit data, and is determined by two determinations by determination of 3.5V, 1.5V or 5.5V. The middle bit data is understood and output.

That is, when reading the most significant bit data, the reading speed is about three times faster than when checking each threshold voltage with all judgment values, and when reading the middle bit data, As compared with the case where each threshold voltage is examined by all judgment voltages, the reading speed is about 1.5 times. Therefore, by storing the most frequently accessed data in the most significant bit, storing the most frequently accessed data next to the most significant bit in the middle bit, and storing relatively infrequently accessed data in the least significant bit, respectively. For the operator (programmer), it looks as if a single (or two-stage) high-speed storage device exists, and the multi-value storage EEPROM can be read very efficiently.

As described above, the present invention has been described by taking as an example a case where multi-value storage is performed in an EEPROM having a floating gate type memory cell. However, a memory cell that performs multi-value storage is not limited to a floating gate type. An MNOS type may be used.

In addition to the EEPROM, the present invention provides a reading method when multi-value storage is performed in an EPROM or PROM, and further controls, for example, the amount of impurities implanted into the channel region of a field effect transistor. Mask RO that changes the threshold value to obtain the memory state
The present invention can also be applied to a reading method when M is stored in multi-value storage.

Furthermore, the reading method of the present invention can be applied to a DRAM. In this case, it goes without saying that the furnace is fresh.

Further, in the first and second embodiments described above, one memory cell has a storage capacity of 2 bits or 3 bits. However, the present invention has four values (2 bits) or more in one memory cell. The present invention can be applied to all cases having the above storage capacity. In particular, the larger the storage capacity, the more effective.

In the first and second embodiments described above, after the address is determined, a predetermined determination voltage is applied to the control gate of the memory cell in which the threshold voltage of each value is set, so that the drain of the memory cell Although a method for detecting whether or not a current flows between sources has been described, data can also be determined by comparing an output voltage from a memory cell with a predetermined determination voltage. This method is illustrated in FIG.
This will be described with reference to the circuit diagram of FIG.

The determination circuit in FIG. 7 is provided between the cell array 1 and the multiplexer 4 in FIG. A threshold voltage Vth1 corresponding to the lower bit set in the memory cell 1a of the cell array 1 is
The sense amplifier 4 is connected via an output buffer including an inverter 40 and transistors 41 and 42.
3 to the inverting input terminal. The non-inverting input terminal of the sense amplifier 43 has a transistor 4
A determination voltage V47 set to 7 is applied through an output buffer including an inverter 46 and transistors 44 and 45.

When the threshold voltage Vth1 is smaller than the determination voltage V47, the output of the sense amplifier 43 is H
Therefore, the lower bit D0 stored in the memory cell 1a is determined to be “1”.
Since the output of the sense amplifier 43 is High, the transistor 52 is turned on, while the inverter 53 is turned off. Therefore, the determination voltage V52 set in the transistor 52 is applied to the non-inverting input terminal of the sense amplifier 48 through the output buffer including the inverter 51 and the transistors 49 and 50. The threshold voltage Vth2 corresponding to the upper bit set in the memory cell 1a is supplied to the sense amplifier 48 via the output buffer.
Is applied to the inverting input terminal.

When the threshold voltage Vth2 is smaller than the determination voltage V52, the output of the sense amplifier 48 is H
Therefore, the upper bit D1 stored in the memory cell 1a is determined to be “1”.
On the other hand, when the threshold voltage Vth2 is larger than the determination voltage V52, the output of the sense amplifier 48 becomes Low, so the upper bit D1 stored in the memory cell 1a is determined to be “0”.

Next, when the threshold voltage Vth1 is larger than the determination voltage V47, the output of the sense amplifier 43 becomes Low, so the lower bit D0 stored in the memory cell 1a is determined to be “0”. Since the output of the sense amplifier 43 is Low, the transistor 52 is turned off, while the transistor 54 is turned on by the inverter 53. Therefore, the determination voltage V54 set in the transistor 54 is applied to the non-inverting input terminal of the sense amplifier 48 through the output buffer. The threshold voltage Vth2 corresponding to the upper bit set in the memory cell 1a is
The signal is applied to the inverting input terminal of the sense amplifier 48 through the output buffer.

When the threshold voltage Vth2 is smaller than the determination voltage V54, the output of the sense amplifier 48 is H
Therefore, the upper bit D1 stored in the memory cell 1a is determined to be “1”.
On the other hand, when the threshold voltage Vth2 is larger than the determination voltage V54, the output of the sense amplifier 48 is Low, so the upper bit D1 stored in the memory cell 1a is determined to be “0”.

In this way, 2-bit (4-value) data (00, 01, 10, 11) is determined. This technique can also be applied to multilevel memory cells having four or more levels by increasing the number of sense amplifiers and determination voltage supply circuits according to the number of bits.

In order to operate various devices so as to realize the functions of the above-described embodiments,
A program stored in a computer (CPU or MPU) of the system or apparatus is supplied to a computer in the apparatus or system connected to the various devices with software program codes for realizing the functions of the embodiment. In the present invention, those implemented by operating the various devices according to the above are also included in the scope of the present invention.

In this case, the program code of the software itself realizes the functions of the above-described embodiments, and the program code itself and means for supplying the program code to the computer, for example, the program code is stored. Storage medium 31
Constitutes the present invention.

The storage medium 31 is a storage / reproduction device 3 connected to the signal control circuit 6 via the input / output I / F 8.
0 reads the program code stored therein, and operates the computer constituting the signal control circuit 6. A storage medium 31 for storing the program code
For example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, magnetic tape, nonvolatile memory card, ROM, or the like can be used.

Moreover, the example of each embodiment of this invention is shown below.
[Embodiment 1]
A plurality of multilevel memory cells each holding one of three or more different predetermined storage states, and at least a first code and a second code encoded by an arbitrary encoding method, Among the plurality of first information bits constituting the first code and the plurality of second information bits constituting the second code, information bits of the same digit correspond to each other as a set Rearrangement means for rearranging the first and second information bits so as to be stored in the multilevel memory cell; and voltage generation means for generating a predetermined voltage corresponding to the rearranged information bits;
A multi-value semiconductor memory device comprising: voltage application means for receiving the address information and applying the predetermined voltage to the multi-value memory cell corresponding to the address information.

[Embodiment 2]
The multilevel semiconductor memory device according to the first embodiment, wherein the rearranging means controls the number of bits stored in each multilevel memory cell according to the error correction capability of the encoding method.

[Embodiment 3]
The reordering means has a code length of n so that m information bits are stored in the one multi-level memory cell when the number of bits stored in one of the plurality of multi-level memory cells is m. 3. The multilevel semiconductor memory device according to the embodiment 1 or 2, wherein m symbols are rearranged as rows of an m × n array.

[Embodiment 4]
4. The multilevel semiconductor memory device according to any one of Embodiments 1 to 3, wherein the multilevel memory cell is a nonvolatile semiconductor memory.

[Embodiment 5]
A method for writing information bits to a multi-level semiconductor memory device comprising a plurality of multi-level memory cells each holding one of three or more different predetermined storage states, comprising any encoding At least a first code and a second code encoded by the method are provided, and a plurality of first information bits constituting the first code and a plurality of second information constituting the second code A first step of rearranging the first and second information bits so that information bits of the same digit are stored in the corresponding multi-level memory cell as a set, and the rearrangement A second step of generating a predetermined voltage corresponding to the received information bit, and a third step of receiving the address information and applying the predetermined voltage to the multilevel memory cell corresponding to the address information. To prepare Writing method and butterflies.

[Embodiment 6]
A storage medium storing a program for writing information bits in a multilevel semiconductor memory device having a plurality of multilevel memory cells each holding one of three or more different predetermined storage states by a computer A plurality of first information bits constituting the first code and the second code in at least the first code and the second code encoded by an arbitrary encoding method. Among the plurality of second information bits, the first and second information bits are rearranged so that the information bits of the same digit are stored as one set in one of the plurality of multi-level memory cells. A storage medium in which a program is stored.

[Embodiment 7]
A program for generating a predetermined voltage according to the rearranged first and second information bits, receiving address information, and applying the predetermined voltage to the multilevel memory cell corresponding to the address information is stored. Embodiment 7. The storage medium according to embodiment 6, wherein:

[Embodiment 8]
A conversion means for giving a logical address and converting it to a physical address, and arranged corresponding to a physical address space including the physical address, and having n (n ≧ 2) components (X ₁ , X ₂ ,..., X
_n ) a plurality of multi-value memory cells that hold a 2 ⁿ -value storage state, and a determination unit that determines whether a logical address space including the logical address matches the physical address space; When it is determined that the logical address space coincides with the physical address space, specifying means for specifying the highest-order component X _{1 at a time according} to a predetermined determination value, and specifying the specified component X ₁ with the plurality of components An output means for outputting from a multilevel memory cell corresponding to the physical address among the multilevel memory cells.

[Embodiment 9]
Each multi-level memory cell includes at least one transistor, and the specifying unit is a first unit that generates a voltage corresponding to the determination value, and a second unit that outputs an address signal given the physical address. And a third means for applying the voltage to the multilevel memory cell corresponding to the physical address in response to the address signal, and whether a current flows between a source and a drain of the transistor to which the voltage is applied. A fourth means for determining whether or not the fourth means
The multi-value semiconductor memory device according to the embodiment 8, further comprising: a fifth means for specifying the topmost component X _{1 based} on a determination result in the means.

[Embodiment 10]
The specifying means has one input terminal connected to the output part of each multi-level memory cell, and a voltage to which the voltage corresponding to the topmost component X ₁ is supplied, and the other input of the comparator A voltage supply circuit connected to a terminal and supplying a voltage corresponding to the predetermined determination value to the other input terminal, and specifying the highest-order component X _{1 according} to a determination result of the comparator The multivalued semiconductor memory device according to the eighth embodiment, which is characterized in that

[Embodiment 11]
When it is determined that the logical address space does not coincide with the physical address space, the specifying unit determines the component (X ₁ , X ₂ ,..., X _n ) to a maximum n by a predetermined maximum n different determination values The multi-value semiconductor memory device according to Embodiment 8, wherein the multi-value semiconductor memory device is specified by times.

[Embodiment 12]
Each of the multi-value memory cells includes at least one transistor, and the specifying means includes first means for generating n voltages corresponding to the n judgment values, and an address signal provided with the physical address. , Second means for outputting the voltage to the multilevel memory cell corresponding to the physical address in response to the address signal, and a source-drain of the transistor to which the voltage is applied A fourth means for applying a maximum of n kinds of voltages to the gate of the transistor in a predetermined order until a current flows between them, and the components (X ₁ , X ₂ ,..., X _n ) by detecting the current. The multi-value semiconductor memory device according to claim 11, further comprising: a fifth means for specifying.

[Embodiment 13]
The specifying means includes a comparator to which one input terminal is connected to the output part of each multi-level memory cell, and each voltage corresponding to the component (X ₁ , X ₂ ,..., X _n ) is supplied. A voltage supply circuit that is connected to the other input terminal of the comparator and supplies a voltage corresponding to the maximum of n determination values to the other input terminal. 12. The multilevel semiconductor memory device according to the embodiment 11, wherein the components (X ₁ , X ₂ ,..., X _n ) are specified.

[Embodiment 14]
N (n ≧ 2) components (X ₁ , X ₂ ,..., X arranged corresponding to the physical address space
_n ) is a method for reading the component from a plurality of multi-valued memory cells holding a ^2n- value storage state represented by _n ), and a first step of converting a logical address into a physical address included in the physical address space A second step of determining whether or not a logical address space including the logical address matches the physical address space, and when it is determined that the logical address space matches the physical address space, third step and, multilevel memory cell corresponding to the physical address of the component X ₁ identified the plurality of multilevel memory cells to identify the components X ₁ at one time with a predetermined determination value And a fourth step of outputting from the first step.

[Embodiment 15]
In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,..., X _n
The reading method according to claim 14, further comprising: a fifth step of specifying at a maximum n times by a predetermined maximum n different determination values.

[Embodiment 16]
N (n ≧ 2) components (X ₁ , X ₂ ,..., X arranged corresponding to the physical address space
_n ) is a method of reading the component from a plurality of multi-valued memory cells each having a 2 ⁿ value storage state represented by _n ), each of which includes at least one transistor, and includes a logical address in the physical address space A first step of converting to a physical address; a second step of determining whether or not a logical address space including the logical address matches the physical address space; and the logical address space matches the physical address space If it is determined,
A third step of applying a predetermined determination voltage to the gate of the transistor and specifying the highest-order component X ₁ depending on whether or not a current flows between the source and drain of the transistor; and the specified component X _And a fourth step of outputting 1 from the multilevel memory cell corresponding to the physical address among the plurality of multilevel memory cells.

[Embodiment 17]
In the second step, when it is determined that the logical address space does not match the physical address space, n different determination voltages are applied to the gates of the transistors in a predetermined order after the second step. And a fifth step of identifying the component (X ₁ , X ₂ ,..., X _n ) by applying n times at a maximum until a current flows between the source and drain of the transistor. 17. The reading method according to 16.

[Embodiment 18]
N (n ≧ 2) components (X ₁ , X ₂ ,..., X arranged corresponding to the physical address space
_n ) is a method of reading the component from a plurality of multi-valued memory cells each having a 2 ⁿ value storage state represented by _n ), each of which includes at least one transistor, and includes a logical address in the physical address space A first step of converting to a physical address; a second step of determining whether or not a logical address space including the logical address matches the physical address space; and the logical address space matches the physical address space If it is determined,
A third step of comparing a voltage corresponding to the highest-order component X ₁ with a predetermined determination voltage and specifying the component X _{1 based} on a comparison result; and specifying the specified component X ₁ as the plurality of multi-values And a fourth step of outputting from the multilevel memory cell corresponding to the physical address of the memory cells.

[Embodiment 19]
In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,..., X _n
) Voltage corresponding to said components _{(X 1, X 2, ...} , compares the voltage corresponding to each component of the X _n), the components by comparison _{(X 1, X 2, ...} , X n) The reading method according to claim 18, further comprising a fifth step of specifying

[Embodiment 20]
A plurality of computers that are arranged corresponding to the physical address space by a computer and hold a storage state of 2 ⁿ values expressed by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A storage medium storing a program for reading the component from a value memory cell, the first step of converting a logical address into a physical address included in the physical address space, and a logical address space including the logical address There a second step of determining whether or not matching the physical address space, the logical address if the space is determined to match said physical address space, the component X ₁ of the uppermost predetermined determination value the allowed output from the third step and the multilevel memory cell corresponding to the physical address of the component X ₁ identified the plurality of multilevel memory cells to identify a single Storage medium in which a program and a fourth step is characterized in that it is stored.

[Embodiment 21]
In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,..., X _n
21. The storage medium according to claim 20, wherein a program further including a fifth step of specifying n) at maximum n times by a predetermined maximum n different determination values is stored.

[Embodiment 22]
The computer stores 2 ⁿ values stored in correspondence with the physical address space and expressed by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A storage medium storing a program for reading the component from a plurality of multi-value memory cells including at least one transistor, wherein the logical address is converted into a physical address included in the physical address space; A second step of determining whether or not a logical address space including the logical address matches the physical address space, and when it is determined that the logical address space matches the physical address space, A predetermined determination voltage is applied to the gate, and the highest-order component X ₁ is specified depending on whether or not a current flows between the source and drain of the transistor. And a fourth step of outputting the identified component X ₁ from the multi-level memory cell corresponding to the physical address of the plurality of multi-level memory cells. A storage medium characterized by that.

[Embodiment 23]
In the second step, when it is determined that the logical address space does not match the physical address space, n different determination voltages are applied to the gates of the transistors in a predetermined order after the second step. A program is further stored that further includes a fifth step of specifying the components (X ₁ , X ₂ ,..., X _n ) by applying n times at most until a current flows between the source and drain of the transistor. Embodiment 23. A storage medium according to embodiment 22 characterized by.

[Embodiment 24]
The computer stores 2 ⁿ values stored in correspondence with the physical address space and expressed by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). A storage medium storing a program for reading the component from a plurality of multi-value memory cells including at least one transistor, wherein the logical address is converted into a physical address included in the physical address space; A second step of determining whether or not a logical address space including the logical address matches the physical address space, and when it is determined that the logical address space matches the physical address space, A voltage corresponding to the component X ₁ is compared with a predetermined determination voltage, and the component X ₁ is specified based on the comparison result.
And a fourth step of outputting the identified component X ₁ from the multi-level memory cell corresponding to the physical address among the plurality of multi-level memory cells. A storage medium characterized by the above.

[Embodiment 25]
In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,..., X _n
) Voltage corresponding to said components _{(X 1, X 2, ...} , compares the voltage corresponding to each component of the X _n), the components by comparison _{(X 1, X 2, ...} , X n) 25. The storage medium according to embodiment 24, in which a program further including a fifth step of specifying is stored.

[Embodiment 26]
In a multi-level semiconductor memory device comprising a plurality of multi-level memory cells, each multi-level memory cell holding one of three or more different predetermined storage states, encoded by an arbitrary encoding method A multi-level semiconductor memory device comprising information bit distribution means for distributing and storing each bit constituting a single code in the plurality of multi-level memory cells.

[Embodiment 27]
The information bit distribution means controls the number of bits in the same code stored in one multi-level memory cell according to the error correction capability of the one code.
The multi-value semiconductor memory device described in 1.

[Embodiment 28]
The information bit distribution means distributes and stores codes stored in the plurality of multilevel memory cells.
When m codes of code length n are arranged as rows in an m × n array and the number of bits stored in the multilevel memory cell is m, m pieces of information arranged in each column of the array are 28. The multi-value semiconductor memory device according to embodiment 27, wherein the multi-value semiconductor memory device is stored in one of value memories.

[Embodiment 29]
Embodiments 26 to 2 wherein the multilevel memory cell is a nonvolatile semiconductor memory
9. The multivalued semiconductor memory device according to any one of 8 above.

[Embodiment 30]
A storage medium storing a program for causing a computer to function as information bit distribution means in the multilevel semiconductor memory device according to any one of embodiments 26 to 29.

[Embodiment 31]
In the method of writing a code string encoded by an arbitrary encoding method to a multilevel semiconductor memory device having a plurality of multilevel memory cells holding three or more storage states, the arbitrary encoding A writing method of a multi-level semiconductor memory device, wherein each bit constituting one code encoded by the method is distributed and stored in a plurality of multi-level memory cells.

[Embodiment 32]
A storage medium in which the writing method of the multilevel semiconductor memory device according to Embodiment 31 is stored so as to be readable from a computer.

[Embodiment 33]
An input means for inputting a logical address, a conversion means for calculating a physical address from the logical address, a control gate and a charge storage layer are arranged corresponding to the physical address, each of which is two-dimensional A multi-value memory cell holding a storage state of three or more values expressed by the above components and the multi-value memory cell corresponding to the physical address are selected, and in accordance with the logical address input to the input means Control means for designating a component to be output from among the components stored in the selected multi-value memory cell, and output means for outputting the data of the component of the multi-value memory cell designated by the control means And there is a determination value for specifying data of at least one of the components in one determination, and the logical address input to the input means is a previous value. When the physical address is included in a partial space corresponding to one-to-one correspondence with the address space spanned by the physical address, the control means specifies the data of the component of the multilevel memory cell designated by the control means by the determination value A multi-value semiconductor memory device characterized in that the data is output from the output means.

[Embodiment 34]
The multilevel memory cell holds a storage state of 2 ⁿ values expressed by n-dimensional (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ) and stores at least the data of the X ₁ component. together with the determination value identifying a single determination exists, the included in the partial space is stored the logical address data in said X ₁ component, the logical address is the input means included in the partial space When input, the X ₁ component data specified by the determination value by the control means among the storage states of the corresponding multi-level memory cell is output from the output means. 34. The multi-value semiconductor memory device according to 33.

[Embodiment 35]
X _2, ..., with each judgment value identifying the data of X _n component is present, the address space A ₂ in proximity to the address space A ₁ is the partial space, ..., the logical address of the data contained in A _n Are sequentially stored in the X ₂ ,..., X _n components in the order close to the address space A ₁ , and the control means _sets X _k (however, depending on the address space of the logical address input to the input means. , K = 1, 2,..., N) component is specified by k determinations using the respective determination values, and data of the X _k component is output from the output means. Multi-value semiconductor memory device.

[Embodiment 36]
Any one of embodiments 33 to 35, wherein the charge storage layer is a floating gate.
The multilevel semiconductor memory device according to item.

[Embodiment 37]
In a method of reading a multi-level semiconductor memory device, comprising a multi-level memory cell comprising a control gate and a charge storage layer and arranged corresponding to a physical address calculated from an input logical address, the multi-level memory cell Each holds a storage state of three or more values represented by components of two or more dimensions, and there is a determination value for specifying data of at least one component of the components, which is input to the input means When the logical address is included in a partial space corresponding to the address space spanned by the physical address, the voltage of the determination value is applied to the control gate of the multilevel memory cell selected by the physical address. The data of the component of the multi-level memory cell is specified according to whether a current flows between the source / drain of the multi-level memory cell Method of reading multi-level semiconductor memory device which is characterized in that force.

[Embodiment 38]
The multi-level memory cell holds a 2 ⁿ value storage state expressed by n-dimensional (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ), and at least the X ₁ component A determination value for specifying the data of the logical address, and the data of the logical address included in the partial space is the X
When the logical address contained in _one component and included in the partial space is input to the input means, the X specified by the value among the storage states of the corresponding multi-level memory cell The reading method for a multi-level semiconductor memory device according to embodiment 37, wherein _one- component data is output from said output means.

[Embodiment 39]
X _2, ..., with each judgment value identifying the data of X _n component is present, the address space A ₂ in proximity to the address space A ₁ is the partial space, ..., the logical address of the data contained in A _n Are sequentially stored in the X ₂ ,..., X _n components in order from the closest to the address space A ₁ , and according to the address space of the logical address input to the input means, X _k (
However, the multi-value semiconductor according to embodiment 38, wherein k = 1, 2,..., N) component data is specified by k determinations based on the respective determination values, and this X _k component is output. A reading method of a storage device.

[Embodiment 40]
A storage medium storing a program for causing a computer to execute the procedure of the reading method according to any one of the embodiments 37 to 39.

[Embodiment 41]
A plurality of multi-level memory cells each holding one of three or more different predetermined storage states, and the first storage information are converted into at least two digits by an arbitrary encoding method. A first encoding means for converting to a first code value, and a second code for converting the second stored information into a second code value having at least two digits by an arbitrary encoding method. Encoding means and reordering means for creating two or more sets of code value information of the same digits of the first and second code values as one set so as to be stored in the corresponding multilevel memory cell A multi-value semiconductor memory device comprising:

[Embodiment 42]
42. The multilevel semiconductor memory device according to embodiment 41, wherein the first and second code values have the same number of digits.

[Embodiment 43]
Embodiment 4 wherein the arbitrary encoding method is a binary encoding method.
45. The multilevel semiconductor memory device according to 1 or 42.

[Embodiment 44]
44. The multi-value semiconductor memory device according to any one of embodiments 41 to 43, wherein the multi-value memory cell has a control gate and a floating gate.

[Embodiment 45]
The multi-level memory cell includes MNOS, mask ROM, EEPROM, EPROM, PRO
45. The multi-value semiconductor memory device according to any one of embodiments 41 to 44, wherein the multi-value semiconductor memory device is at least one of M and a flash nonvolatile memory.

[Embodiment 46]
46. Any one of Embodiments 41 to 45, further comprising a correction unit that detects and corrects an error occurring in the first and second stored information from the first and second code values. The multi-value semiconductor memory device described in 1.

[Embodiment 47]
A plurality of multi-level memory cells each holding one of three or more different predetermined storage states, and the input storage information are converted into at least two digits by an arbitrary encoding method. An encoding unit for converting the encoded value into a code value, and dividing the code value obtained by the encoding unit by an arbitrary number of digits to create at least two encoded information blocks; A multi-value semiconductor memory device comprising: divided storage means for storing the same digit encoded information as a set in the multi-value memory cell.

[Embodiment 48]
It further comprises reading means for reading out the encoded information stored in each of the multi-level memory cells, correcting the code string composed of the encoded information according to the error correction capability of the encoding method, and outputting it. 48. A multilevel semiconductor memory device according to Embodiment 47.

[Embodiment 49]
49. The multilevel semiconductor memory device according to embodiment 48, wherein said read means reads at least predetermined bit information from each of said multilevel memory cells to create and output said code string.

[Embodiment 50]
The multi-level memory cell is capable of holding one of four different predetermined storage states, and the divided storage means converts the code value into two codes having the same number of digits. 50. The multilevel semiconductor memory device according to embodiment 49, wherein the multilevel semiconductor memory device is divided into encoded information blocks, and two sets of encoded information of the same digit of each encoded information block are stored in the multilevel memory cell as a set. .

[Embodiment 51]
51. The multilevel semiconductor memory device according to embodiment 50, wherein said reading means outputs each of said two encoded information blocks as a result of adding redundant bits to information bits.

[Embodiment 52]
The multilevel memory cell is capable of holding one of eight different predetermined storage states, and the divided storage means converts the code value into three codes having the same number of digits. 50. The multilevel semiconductor memory device according to embodiment 49, wherein the multilevel semiconductor memory device is divided into encoded information blocks, and three encoded information of the same digit of each encoded information block is stored in the multilevel memory cell as a set. .

[Embodiment 53]
53. The multi-level semiconductor memory device according to embodiment 52, wherein said reading means outputs each of said three encoded information blocks as a result of adding redundant bits to information bits.

[Embodiment 54]
The reading means outputs each information block formed by combining one encoded information block and two encoded information blocks, each of which includes a redundant bit added to an information bit. The multi-value semiconductor memory device according to embodiment 52.

[Embodiment 55]
The multilevel memory cell is capable of holding one of 16 different predetermined storage states, and the divided storage means converts the code value into four codes having the same number of digits. 50. The multilevel semiconductor memory device according to embodiment 49, wherein the multilevel semiconductor memory device is divided into encoded information blocks, and four encoded information of the same digit of each encoded information block is stored in the multilevel memory cell as a set. .

[Embodiment 56]
56. The multi-level semiconductor memory device according to embodiment 55, wherein said reading means outputs each of said four encoded information blocks as a result of adding redundant bits to information bits.

[Embodiment 57]
55. The embodiment according to embodiment 55, wherein the reading means outputs each information block formed by combining the two encoded information blocks with each information bit being added with a redundant bit. Multi-value semiconductor memory device.

[Embodiment 58]
58. The multi-value semiconductor memory device according to any one of embodiments 47 to 57, wherein the multi-value memory cell has a control gate and a floating gate.

[Embodiment 59]
The multi-level memory cell includes MNOS, mask ROM, EEPROM, EPROM, PRO
58. The multi-value semiconductor memory device according to any one of embodiments 47 to 57, wherein the multi-value semiconductor memory device is at least one of M and a flash nonvolatile memory.

[Embodiment 60]
The redundant bits are generated corresponding to each of the two encoded information blocks based on the two encoded information blocks, and the sum of the information bits of the encoded information blocks and the corresponding redundant bits 52. The multilevel semiconductor memory device according to embodiment 51, wherein is a redundant bit such that becomes the number of bits of the coded sequence.

[Embodiment 61]
The redundant bits are generated corresponding to each of the three encoded information blocks based on the three encoded information blocks, and the total of the redundant bits corresponding to the information bits of each encoded information block is 54. The multilevel semiconductor memory device according to embodiment 53, wherein the number of redundant bits is the number of bits of the coded sequence.

[Embodiment 62]
The redundant bits are obtained by the Hamming coding based on the three coded information blocks.
A first redundant bit is generated corresponding to each of the encoded information blocks, a code string is generated by adding the first redundant bit corresponding to each of the three encoded information blocks, A second redundant bit is generated corresponding to each code string by calculating an exclusive OR of all the bits included in the code string, and the sum of the bits of each code string and the corresponding second redundant bits 56. The multilevel semiconductor memory device according to embodiment 53, wherein is a redundant bit such that becomes the number of bits of the code string.

[Embodiment 63]
The redundant bits are generated on the basis of the three encoded information blocks and corresponding to each of the information blocks formed by combining the one encoded information block and the two encoded information blocks. The sum of the redundant bits corresponding to the information bits of one encoded information block, the information bits of each of the divided blocks when the information block formed by combining the two encoded information blocks is divided, and 56. The multilevel semiconductor memory device according to embodiment 53, wherein the total number of corresponding redundant bits is a redundant bit such that the number of bits of the encoded sequence is the same.

[Embodiment 64]
The redundant bits are generated corresponding to each of the four encoded information blocks based on the four encoded information blocks, and a sum of the redundant bits corresponding to the information bits of each encoded information block is calculated. 57. The multilevel semiconductor memory device according to embodiment 56, wherein the number of redundant bits is the number of bits of the encoded sequence.

[Embodiment 65]
The redundant bits are obtained by the Hamming coding based on the four coded information blocks.
A first redundant bit is generated corresponding to each of the encoded information blocks, a code string is generated by adding the first redundant bit corresponding to each of the four encoded information blocks, A second redundant bit is generated corresponding to each code string by calculating an exclusive OR of all the bits included in the code string, and the sum of the bits of each code string and the corresponding second redundant bits 57. The multi-value semiconductor memory device according to embodiment 56, wherein is a redundant bit such that becomes the number of bits of the code string.

[Embodiment 66]
The redundant bits are generated corresponding to each of the information blocks formed by combining the two encoded information blocks based on the four encoded information blocks, and the two encoded information blocks are combined. When each of the information blocks is divided into two, the redundant bits corresponding to the information bits of each of the divided blocks and the corresponding redundant bits are the number of bits of the coded sequence. 56. The multilevel semiconductor memory device according to the embodiment 57.

It is a block diagram which shows the main structures of EEPROM by embodiment of this invention. 1 is a schematic cross-sectional view of an EEPROM floating gate type memory cell according to an embodiment of the present invention; It is a schematic diagram explaining 1st Embodiment of the writing method of this invention. It is a schematic diagram explaining 2nd Embodiment of the writing method of this invention. It is a schematic diagram explaining the modification of 2nd Embodiment of the writing method of this invention. It is a schematic diagram explaining 3rd Embodiment of the writing method of this invention. It is a schematic diagram explaining the modification of 3rd Embodiment of the writing method of this invention. It is a flowchart of the reading method by 1st Embodiment of the reading method of this invention. It is a block diagram explaining the method of determining the threshold voltage in the flowchart of FIG. It is a flowchart of the reading method by 2nd Embodiment of the reading method of this invention. It is a block diagram explaining the other method of determining a threshold voltage.

Explanation of symbols

1 memory cell array 2 decoder 3 voltage generation and voltage control circuit 4 multiplexer 5 sense amplifier 6 signal control circuit 6a information bit distribution means 7 input I / F
8 output I / F
9 Conversion circuit 11 Silicon substrate 12 Drain 13 Source 17 Floating gate 19 Control gate 30 Storage / reproduction device 31 Storage medium 40, 46, 51, 53 Inverters 41, 42, 44, 45, 47, 49, 50, 52, 54 Transistor 43 , 48 Sense amplifier 55 Switch circuit 56 Reference voltage generation circuit

Claims (6)

A plurality of multi-value memory cells each storing three or more information bits , wherein one of the information bits stores data that is accessed more frequently than data stored in other information bits. A plurality of multi-value memory cells ;
Voltage generating means for generating a predetermined voltage to access the multilevel memory cell ;
Voltage application means for receiving address information and applying the predetermined voltage at least once to the multilevel memory cell corresponding to the address information;
The multi-value semiconductor memory of the memory system in which the frequently accessed data is accessed when the voltage applying means applies a predetermined voltage only once to each of the plurality of multi-value memory cell sets. apparatus.   The multilevel semiconductor memory device according to claim 1, wherein the multilevel memory cell is a nonvolatile semiconductor memory. Each including a plurality of multi-value memory cells storing three or more information bits , wherein one of the information bits stores data that is accessed more frequently than data stored in other information bits; A method for writing information bits to a multilevel semiconductor memory device of a memory system , comprising:
A first step in which a voltage generating means generates a predetermined voltage to access the multilevel memory cell ;
Voltage applying means, and a second step of receiving the address information, and applies a predetermined voltage at least once to the multilevel memory cell corresponding to the address information,
The writing method, wherein the voltage application means applies a predetermined voltage only once to each of the plurality of sets of multi-valued memory cells, thereby accessing the frequently accessed data.   A computer-readable storage medium storing a program for causing a computer to execute the steps of the writing method according to claim 3. A multi-level semiconductor memory device comprising a plurality of multi-level memory cells each storing three or more information bits , wherein one of the information bits is compared with data stored in another information bit To store frequently accessed data,
Voltage generating means for generating a predetermined voltage to access the multilevel memory cell ;
Voltage application means for receiving address information and applying the predetermined voltage at least once to the multilevel memory cell corresponding to the address information;
The multi-value semiconductor memory of the memory system in which the frequently accessed data is accessed when the voltage applying means applies a predetermined voltage only once to each of the plurality of multi-value memory cell sets. apparatus.   6. The multi-value semiconductor memory device according to claim 5, wherein the multi-value memory cell is a nonvolatile semiconductor memory.

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