JPH10222989A - Multiple-value semiconductor storage, its writing method and reading method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently correct an error even if multiple-value information stored in a multiple-value memory cell is lost. SOLUTION: A bit information dispersion means 6a for storing each bit for constituting one coded word that is coded by an arbitrary coding method by dispersing it into a plurality of multiple-value memory cells is provided at a memory cell array 1 of a multiple-value semiconductor storage with a plurality of multiple-value memory cells for retaining at least three storage states. Then, even an error results in a plurality of bits stored at one multiple- value memory, only information on the minimum number of bits whose error can be corrected is lost for one coded word.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilevel semiconductor memory device, a method of writing and reading the same, and a storage medium.

[0002]

2. Description of the Related Art As an error correction function of a code stored in a semiconductor memory device, for example, a method using a Hamming code has been generally used. In a semiconductor memory device using the Hamming code, for example, when storing four information bits (m1, m2, m3, m4), three check bits (p1, p2, p3) are obtained by an encoder. A total of 7 bits of information bits and check bits are stored.

When reading the Hamming code stored in the semiconductor memory device, the read information (y1, y1,
y2, y3, y4, y5, y6, y7) are supplied to a decoder to obtain error-corrected information (m1, m2, m3, m4). In such a semiconductor memory device,
The read information (y1, y2, y3, y4, y5,
(y6, y7), it is possible to correct an error of up to 1 bit. For details, see, for example, “Code Theory” (published on June 10, 1994 (5th edition)) by Hideki Imai, published by the Institute of Electronics, Information and Communication Engineers.

Incidentally, recently, Japanese Patent Application Laid-Open No. Hei 6-195687
As shown in the publication, there is a multilevel semiconductor memory device that stores three or more values in one memory cell. In the multi-level semiconductor memory device, a plurality of threshold voltages are set. For example, in the case of a quaternary nonvolatile semiconductor memory, each memory cell has four threshold voltages (0 V, 2 V, and 4 V). , 6
V), so that two bits of information can be stored in one memory cell. That is,
The threshold voltages of the memory cells are set to 0 V, 2 V, 4 V, and 6 V corresponding to the stored contents (00, 01, 10, 11).

Here, when an error correction function using a Hamming code is provided to such a multilevel semiconductor memory device, conventionally, each bit of a code string to be stored obtained by encoding is stored in order. Therefore, adjacent bits are stored in the same memory cell.

For example, information bits (m11, m21, m
31, m41) and (m12, m22, m32, m42)
From the check bits (p11, p21, p31) and (p1
2, p22, p32) and storing them in a multi-level memory cell. When a Hamming code composed of these information bits and check bits is stored in a multilevel memory cell, conventionally, m11 and m21, m31 and m41, p
11 and p21, p31 and m12, m22 and m32, m4
2 and p12, and p22 and p32.

[0007]

The error occurrence in the multi-level semiconductor memory device will be described with reference to the above-described multi-level non-volatile memory as an example. There is a very high probability that two-bit information pairs will simultaneously cause an error so that "10" becomes "01".

That is, an error occurring in the multi-level semiconductor memory device is a so-called burst error which occurs in a certain section of the code sequence in correspondence with the number of values stored in one multi-level memory cell. It is characteristic. When such a burst error occurs, the storage state of one multi-level memory cell changes, and a 2-bit error occurs.
In this case, two or more errors occur in one Hamming code, and decoding cannot be performed correctly.

In addition to the method using a Hamming code, Japanese Patent Application Laid-Open No. 60-163 discloses an error correction method for a multilevel semiconductor memory device.
A method using a multiple code as disclosed in Japanese Patent Publication No. 300 is also proposed. However, this method also takes into account that the probability of an error occurring in a multilevel semiconductor memory device is a high probability of a burst error. There was a problem that the efficiency of error correction was poor.

In the above-described multi-valued memory, 1
There is a problem that the number of read operations for one memory cell increases. The conventional reading method is described in the above 4
A read operation of the value semiconductor memory device will be described. When receiving a read command from the outside, the semiconductor memory device waits for input of an address. The input address is not a physical address corresponding to a real memory cell, but a logical address. Therefore, a physical address is calculated from the input logical address.

Next, the threshold voltage of the memory cell specified by the calculated physical address is set to (0 V, 2 V, 4
V, 6V) and converts it into 2-bit data. Specifically, for example, 1 V, 3
V and 5V judgment voltages are sequentially applied. In this case, if a current flows through the source / drain of the memory cell when the determination voltage of 1 V is applied, the threshold voltage of the memory cell is found to be 0 V, and the data “00” is read. On the other hand, if the current did not flow at 1 V, but if the current flowed at 3 V, the threshold voltage of the memory cell was found to be 2 V, and the data “01” was read.

Further, no current flows at 1 V and 3 V, and 5 V
When the current flows for the first time at the time of, the threshold voltage of the memory cell is found to be 4 V, and the data of "10" is read. Further, when no current flows at all the voltages applied to the memory cell, the threshold voltage of the memory cell is found to be 6 V, and the data "11" is read. In the example described above, one memory cell has four
Although a value, that is, 2-bit data is stored, storing multi-valued data is also being studied.

However, in the above-mentioned multi-valued memory,
There is a problem that the number of read operations for one memory cell increases. For example, when the four values are stored in one memory cell as described above, in the conventional four-value semiconductor memory device, the read operation is performed as described above.
Regardless of the value of the input address, three read detection operations are always performed to specify which of the four values the threshold voltage of the memory cell is. Actually, read detection is performed by applying a voltage that changes in a stepwise manner from 1 V to 3 V to 5 V, but the read detection operation is still required three times.

Therefore, the present inventors have disclosed in Japanese Patent Application Laid-Open No. 7-201.
No. 189 discloses a method for speeding up a read operation of a memory cell. According to this method, which corresponds to the above-described quaternary semiconductor memory device, first, three
A voltage of V is applied, and an upper bit of 2-bit data is determined based on whether or not a current flows. In this case, if a current flows, the upper bit is “0”, and if no current flows, the upper bit is “1”. Next, when it is determined that the upper bit is “0”, a voltage of 1 V is further applied to the memory cell, and if a current flows, the 2-bit data of the memory cell is “00”. If no current flows, the data is determined to be "01" and output. On the other hand, when it is determined that the upper bit is “1”, a voltage of 5 V is further applied to the memory cell, and if a current flows, the 2-bit data of the memory cell is “10”. If no current flows, the data is determined to be "11" and output. As described above, according to the reading method disclosed in Japanese Patent Application Laid-Open No. Hei 7-201189, it is possible to specify 2-bit data stored in one memory cell by performing two reading operations.

However, even in the reading method described in Japanese Patent Application Laid-Open No. 7-201189, even if the logical address specifies, for example, the upper bit of the memory cell, it does not depend on the logical address. It is determined whether the threshold voltage is one of four values.

As described above, the conventional multi-valued semiconductor memory device outputs data after completely specifying the storage content of the memory cell regardless of the input logical address in the read operation. As described above, it takes time, and there is a problem that the reading speed is necessarily limited.

SUMMARY OF THE INVENTION In view of the above problems, it is a first object of the present invention to enable efficient error correction even when multi-value information stored in one memory cell is lost. I do.

Further, according to the input logical address,
It is a second object of the present invention to enable high-speed reading of frequently accessed data and to further shorten the reading access time.

[0019]

According to the present invention, there is provided a multi-level semiconductor memory device comprising: a plurality of multi-level memory cells each holding one of three or more different predetermined storage states; At least a first code and a second code encoded by the encoding method are provided, and a plurality of first information bits forming the first code and a plurality of second information bits forming the second code are provided. And a rearranging means for rearranging the first and second information bits so that information bits of the same digit among the information bits are stored as a set in the corresponding multi-level memory cell. Voltage generating means for generating a predetermined voltage in response to the information bit, and voltage applying means for receiving address information and applying the predetermined voltage to the multi-level memory cell corresponding to the address information.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the rearranging means controls the number of bits stored in each of the multi-level memory cells according to the error correction capability of the encoding method. .

In one embodiment of the multi-level semiconductor memory device according to the present invention, the rearrangement means is configured to output m information bits when one of the plurality of multi-level memory cells stores m bits. Are stored in the one multi-valued memory cell, and m codes of code length n are rearranged as each row of an m × n array.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the multi-level memory cell is a nonvolatile semiconductor memory.

A multi-level semiconductor memory device having a plurality of multi-level memory cells each holding one of three or more different predetermined storage states is provided. A method for writing information bits to a device, wherein at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first information constituting the first code are provided. The first and second information bits of the same digit of the plurality of second information bits forming the second code are stored in the corresponding multi-level memory cell as a set. A first step of rearranging two information bits, a second step of generating a predetermined voltage corresponding to the rearranged information bits, and a step of receiving address information and receiving the address information. Value memory cell And a third step of applying a predetermined voltage to the.

The storage medium of the present invention can store one or more of three or more different predetermined storage states by a computer.
A storage medium storing a program for writing information bits in a multi-level semiconductor memory device including a plurality of multi-level memory cells holding at least one In a code and a second code, information bits of the same digit among a plurality of first information bits forming the first code and a plurality of second information bits forming the second code Are stored as one set in one of the plurality of multi-valued memory cells.
And a program for rearranging the second information bits.

In one embodiment of the storage medium of the present invention,
A program for generating a predetermined voltage according to the rearranged first and second information bits, receiving address information, and applying the predetermined voltage to the multi-level memory cell corresponding to the address information is stored. ing.

The multi-level semiconductor memory device according to the present invention comprises: a conversion unit which receives a logical address and converts it to a physical address;
The components (X ₁ , X ₂ ,...,..., N) are arranged corresponding to the physical address space including the physical address.
X _n ), a plurality of multi-valued memory cells holding a 2 ⁿ -valued storage state represented by X _n ), and determination means for determining whether or not a logical address space including the logical address matches the physical address space; When it is determined that the logical address space coincides with the physical address space, specifying means for specifying the component X ₁ at the top at one time by a predetermined determination value, and specifying the specified component X ₁ Output means for outputting from the multi-valued memory cell of the multi-valued memory cell corresponding to the physical address.

In one embodiment of the multi-level semiconductor memory device according to the present invention, each of the multi-level memory cells includes at least one transistor, and the specifying means generates a voltage corresponding to the determination value. Means, a second means for receiving the physical address and outputting an address signal, and a third means for applying the voltage to the multi-level memory cell corresponding to the physical address in response to the address signal;
Fourth means for determining whether or not current flows between the source and the drain of the transistor to which the voltage is applied;
The result of the determination in said fourth means includes a fifth means for specifying the component X ₁ of said uppermost.

[0028] In an exemplary aspect of the multi-level semiconductor memory device of the present invention, the specifying unit, the is one input terminal connected to an output portion of the multi-level memory cell, the component X ₁ of the uppermost A comparator to which a corresponding voltage is supplied, and a voltage supply circuit connected to the other input terminal of the comparator and supplying a voltage corresponding to the predetermined determination value to the other input terminal. vessels of the determination result by specifying the component X ₁ of said uppermost.

In one embodiment of the multi-valued semiconductor memory device according to the present invention, when it is determined that the logical address space does not match the physical address space, the specifying means sets the components (X ₁ , X ₂ , .., X _n ) are specified at a maximum of n times by a predetermined maximum of n different determination values.

In one embodiment of the multi-valued semiconductor memory device according to the present invention, each of the multi-valued memory cells includes at least one transistor, and the specifying means outputs n voltage values corresponding to the n judgment values. And a second means for outputting an address signal given the physical address.
Means, the third means for applying the voltage to the multi-level memory cell corresponding to the physical address in response to the address signal, and a current flowing between the source and the drain of the transistor to which the voltage is applied. Up to n kinds of voltages to the gate of the transistor in a predetermined order
Means and the component (X
_1, X _2, ..., and a fifth means for specifying the X _n).

In one embodiment of the multi-valued semiconductor memory device according to the present invention, the identification means has one input terminal connected to an output portion of each of the multi-valued memory cells, and the component (X ₁ ,
X ₂ ,..., X _n ) and connected to the other input terminal of the comparator, and the other input terminal corresponds to the maximum n determination values. And a voltage supply circuit for supplying a voltage, wherein the component (X ₁ , X ₂ ,...,
X _n ).

According to the method of reading a multilevel semiconductor memory device of the present invention, n (n)
≧ 2) represented by components (X ₁ , X ₂ ,..., X _n )
^A method of reading the component from a plurality of multi-valued memory cells holding an ^n- valued storage state, the method comprising: converting a logical address to a physical address included in the physical address space.
And a second step of determining whether or not a logical address space including the logical address matches the physical address space, and when it is determined that the logical address space matches the physical address space, A third step of specifying the highest-order component X ₁ at one time based on a predetermined determination value, and a multi-level corresponding to the physical address of the plurality of multi-level memory cells to specify the specified component X ₁ And outputting the data from the memory cell.

In one embodiment of the method for reading a multi-level semiconductor memory device according to the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the second After the above step, the components (X ₁ , X ₂ ,..., X _n ) are converted to a predetermined maximum n
The method further includes a fifth step of specifying a maximum of n times by the number of different determination values.

According to the method of reading a multilevel semiconductor memory device of the present invention, n (n)
≧ 2) represented by components (X ₁ , X ₂ ,..., X _n )
^A method for reading said components from a plurality of multi-valued memory cells each having an ^n- valued storage state and each including at least one transistor, wherein a first logical address is converted to a physical address included in said physical address space. And a second step of determining whether or not a logical address space including the logical address matches the physical address space, and when it is determined that the logical address space matches the physical address space, A third step of applying a predetermined determination voltage to the gate of the transistor to specify the component X ₁ at the top based on whether or not a current flows between the source and the drain of the transistor; a fourth step of outputting a ₁ from the multilevel memory cell corresponding to the physical address of the plurality of multilevel memory cells Including.

In one embodiment of the method for reading a multi-level semiconductor memory device according to the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the second After the step, n different judgment voltages are applied to the gate of the transistor in a predetermined order at a maximum of n times until a current flows between the source and the drain of the transistor, and the component (X
_1, X _2, ..., further comprising a fifth step of identifying X _n).

According to the method of reading a multi-level semiconductor memory device of the present invention, n (n)
≧ 2) represented by components (X ₁ , X ₂ ,..., X _n )
^A method for reading said components from a plurality of multi-valued memory cells each having an ^n- valued storage state and each including at least one transistor, wherein a first logical address is converted to a physical address included in said physical address space. And a second step of determining whether or not a logical address space including the logical address matches the physical address space, and when it is determined that the logical address space matches the physical address space, The top component X
Comparing a voltage corresponding to ₁ and a predetermined determination voltage, the comparison result by the third step of identifying the components X _1, wherein the said component X ₁ identified among the plurality of multilevel memory cells And outputting the data from the multi-level memory cell corresponding to the physical address.

In one embodiment of the method for reading a multi-level semiconductor memory device according to the present invention, when it is determined in the second step that the logical address space does not match the physical address space, the second after the step, the components _{(X 1, X 2, ...} , X n) voltage and the component corresponding to the _{(X 1, X 2, ...} , X n) is compared with the voltage corresponding to each component of the According to the comparison result, the component (X
_1, X _2, ..., further comprising a fifth step of identifying X _n).

The storage media according to the present invention are arranged by a computer in correspondence with the physical address space, and the number of storage media is n (n ≧ n).
Component of _{2) (X 1, X 2} , ..., 2 n represented by X _n)
A storage medium storing a program for reading the component from a plurality of multi-valued memory cells holding a value storage state, wherein a first step of converting a logical address into a physical address included in the physical address space And a second step of determining whether or not a logical address space including the logical address matches the physical address space; and determining that the logical address space matches the physical address space, third step and, multilevel memory cell corresponding to the physical address of the component X ₁ identified the plurality of multilevel memory cells to identify the components X ₁ at one time with a predetermined determination value And a fourth step of outputting the data from the program.

In one embodiment of the storage medium of the present invention,
If it is determined in the second step that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,
.., X _n ) are stored. The program further includes a fifth step of specifying at most n times by a predetermined maximum of n different determination values.

The storage media of the present invention are arranged by the computer in correspondence with the physical address space, and are stored in n (n ≧ n)
Component of _{2) (X 1, X 2} , ..., 2 n represented by X _n)
A storage medium storing a program for reading a component from a plurality of multilevel memory cells each holding a value storage state and each including at least one transistor, wherein a logical address is included in the physical address space. A first step of converting to a physical address, a second step of determining whether a logical address space including the logical address matches the physical address space, and a logical address space matching the physical address space then when it is determined, by applying a predetermined determination voltage to the gate of the transistor, the source of the transistor - the third step of identifying the components X ₁ the uppermost by whether current flows between the drain , multilevel memory cell corresponding to the components X ₁ identified in the physical address of the plurality of multilevel memory cells And a fourth step of outputting the data from the program.

In one embodiment of the storage medium of the present invention,
In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, n different determination voltages are applied to the gate of the transistor in a predetermined order. , A maximum of n until a current flows between the source and the drain of the transistor.
A program is stored which further includes a fifth step of specifying the components (X ₁ , X ₂ ,..., X _n ) by applying once.

The storage media of the present invention are arranged by the computer in correspondence with the physical address space, and the number of storage media is n (n ≧ n).
Component of _{2) (X 1, X 2} , ..., 2 n represented by X _n)
A storage medium storing a program for reading a component from a plurality of multilevel memory cells each holding a value storage state and each including at least one transistor, wherein a logical address is included in the physical address space. A first step of converting to a physical address, a second step of determining whether a logical address space including the logical address matches the physical address space, and a logical address space matching the physical address space Then, when it is determined, the voltage corresponding to the highest-order component X ₁ is compared with a predetermined determination voltage, and based on the comparison result, the component X ₁ is determined.
_A third step of identifying ₁ and the identified component X
Outputting a ₁ from a multi-valued memory cell corresponding to the physical address of the plurality of multi-valued memory cells.

In one embodiment of the storage medium of the present invention,
If it is determined in the second step that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,
, X _n ) and the components (X ₁ , X ₂ ,
, X _n ) are compared with the voltages corresponding to the respective components, and a program is further stored which includes a fifth step of specifying the components (X ₁ , X ₂ ,..., X _n ) based on the comparison result. I have.

The multi-level semiconductor memory device of the present invention comprises a plurality of multi-level memory cells, each of which has one or more of three or more different predetermined storage states. The semiconductor memory device includes information bit dispersing means for distributing and storing each bit constituting one code encoded by an arbitrary encoding method in the plurality of multi-level memory cells.

In one embodiment of the multi-level semiconductor memory device of the present invention, the information bit dispersing means stores the bits in the same code stored in one multi-level memory cell in accordance with the error correction capability of the one code. Control the number of.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the information bit dispersing means converts the codes stored in the plurality of multi-level memory cells in a distributed manner into m codes having a code length of n. When the number of bits stored in the multilevel memory cell is m, m pieces of information arranged in each column of the array are stored in one of the multilevel memories.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the multi-level memory cell is a nonvolatile semiconductor memory.

The storage medium of the present invention stores a program for causing a computer to function as the information bit distributing means described above.

A writing method for a multi-level semiconductor memory device according to the present invention is characterized in that a code string coded by an arbitrary coding method is provided with a plurality of multi-level memory cells holding three or more storage states. In this method, each bit constituting one code encoded by the arbitrary encoding method is dispersedly stored in a plurality of multi-valued memory cells.

In the storage medium of the present invention, the above-described writing method for the multi-value semiconductor memory device is stored so as to be readable by a computer.

The multi-valued semiconductor memory device of the present invention has input means for inputting a logical address, conversion means for calculating a physical address from the logical address, a control gate and a charge storage layer, And a multi-valued memory cell that holds a storage state of three or more values, each of which is represented by a component of two or more dimensions, and the multi-valued memory cell corresponding to the physical address. Control means for designating a component to be output from the components stored in the multi-valued memory cell selected in accordance with the logical address inputted to the input means, and the multi-level memory designated by the control means. Output means for outputting the data of the component of the value memory cell, wherein there is a determination value that specifies the data of at least one of the components in one determination. When the logical address input to the input means is included in a partial space corresponding one-to-one with the address space spanned by the physical address, the control means controls the multi-level memory cell designated by the control means. The component data is specified by the determination value, and the data is output from the output unit.

In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel memory cell is represented by n-dimensional (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ). holding the stored state of the 2 ⁿ values, the data of at least the X ₁ component 1
There is a judgment value specified in the judgment of the time, and the data of the logical address included in the subspace is the X ₁
When the logical address stored in the component and included in the subspace is input to the input unit, the storage state of the corresponding multi-level memory cell is specified by the determination value by the control unit. the data of the X ₁ component output from said output means that.

In one embodiment of the multi-value semiconductor memory device of the present invention, each judgment value for specifying the data of the X ₂ ,..., X _n components exists, and is close to the address space A ₁ which is the partial space. the address space a ₂ to, ..., data of the logical address included in a _n is the address space a ₁
Wherein X _2, in order of proximity to ... are sequentially stored in the X _n components, depending on the address space of the logical address inputted to said input means, said control means X _k (where, k =
The (1, 2,..., N) component is specified by k determinations based on the respective determination values, and the data of the X _k component is output from the output means.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the charge storage layer is a floating gate.

A method of reading a multi-level semiconductor memory device according to the present invention includes a multi-level memory cell having a control gate and a charge storage layer, which is arranged corresponding to a physical address calculated from an input logical address. A method of reading a multi-valued semiconductor memory device, wherein the multi-valued memory cell holds three or more storage states each represented by a two-dimensional or more component, and at least one of the components When there is a determination value for specifying component data and the logical address input to the input means is included in a partial space corresponding to the address space spanned by the physical address on a one-to-one basis, a selection is made based on the physical address. Applying the voltage of the determination value to the control gate of the multi-valued memory cell and determining whether a current flows between the source and the drain of the multi-valued memory cell To the component data identified by the output of said multilevel memory cell by.

In one embodiment of the method of reading a multi-level semiconductor memory device according to the present invention, the multi-level memory cell includes n
The storage state of 2 ⁿ values represented by the components (X ₁ , X ₂ ,..., X _n ) of the dimension (n ≧ 2) is held, and at least a judgment value for specifying the data of the X ₁ component exists. as well as, the and the logical address of the data is contained in the subspace is stored in the X ₁ component, when the logical address included in the partial space is input to said input means, said corresponding multilevel memory among the storage state of the cell, and it outputs the data of the X ₁ components identified by said value from said output means.

[0057] In an exemplary aspect of the method of reading the multi-level semiconductor memory device of the present invention, X _2, ..., with each judgment value identifying the data of X _n component is present, the partial space in which the address space A Address space A ₂ close to ₁ ,
..., the data of the logical address included in A _n is the order of closeness to the address space A ₁ X _2, ..., are sequentially stored in the X _n components, the address space of the logical address inputted to said input means X _k (where k =
The data of the (1, 2,..., N) components is represented by k
The X _k component is output by specifying the number of times of determination.

The storage medium of the present invention stores a program for causing a computer to execute the procedure of the above-described reading method.

The multi-value semiconductor memory device of the present invention has three
A plurality of multi-valued memory cells that hold one of a plurality of different predetermined storage states, and a first storage information having a first number of at least two digits by an arbitrary encoding method. And a second encoding means for converting the second stored information into a second code value having at least two or more digits by an arbitrary encoding method. And reordering means for creating two or more sets of code value information of the same digit of the first and second code values as one set so as to be stored in the corresponding multi-level memory cell.

In one embodiment of the multilevel semiconductor memory device of the present invention, the first and second code values have the same number of digits.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the arbitrary coding method is a coding method using a binary method.

[0062] In one embodiment of the multilevel semiconductor memory device of the present invention, the multilevel memory cell has a control gate and a floating gate.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the multi-level memory cell comprises an MNOS, a mask R
It is at least one of OM, EEPROM, EPROM, PROM, and flash nonvolatile memory.

In one embodiment of the multilevel semiconductor memory device according to the present invention, a correcting means for detecting and correcting an error in the first and second storage information from the first and second code values. Is further provided.

The multilevel semiconductor memory device of the present invention has three
A plurality of multi-valued memory cells holding one of a plurality of different predetermined storage states, and input storage information,
Encoding means for converting into a code value having at least two or more digits by an arbitrary encoding method, and dividing the code value obtained by the encoding means by an arbitrary number of digits,
Divided storage means for creating at least two encoded information blocks and storing the encoded information of the same digit of each encoded information block as a set in the multi-level memory cell.

In one embodiment of the multi-level semiconductor memory device of the present invention, the coded information stored in each of the multi-level memory cells is read out, and the coded information is read from the coded information in accordance with the error correction capability of the coding method. And reading means for correcting and outputting the code string.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the read-out means reads out bit information of at least a predetermined position from each of the multi-level memory cells, creates and outputs the code string.

In one embodiment of the multi-valued semiconductor memory device according to the present invention, the multi-valued memory cell is capable of holding one of four different predetermined storage states, The division storage unit divides the code value into two coded information blocks having the same number of digits, and stores two sets of coded information of the same digit in each of the coded information blocks as a set in the multilevel memory cell. Remember.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the reading means outputs each of the two encoded information blocks as information bits to which redundant bits are added.

In one embodiment of the multi-valued semiconductor memory device of the present invention, the multi-valued memory cell can hold one of eight different predetermined storage states, The division storage unit divides the code value into three coded information blocks having the same number of digits, and sets the three coded information of the same digit of each coded information block as one set in the multi-valued memory cell. Remember.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the reading means outputs each of the three coded information blocks as information bits to which redundant bits are added.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the read means includes an information block formed by combining one encoded information block and two encoded information blocks. The information bits are output as redundant bits added to the information bits.

In one embodiment of the multi-valued semiconductor memory device of the present invention, the multi-valued memory cell is capable of holding one of 16 different predetermined storage states, The division storage unit divides the code value into four coded information blocks having the same number of digits, and sets the four coded information of the same digit of each coded information block as one set in the multi-valued memory cell. Remember.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the reading means outputs each of the four encoded information blocks as information bits to which redundant bits are added.

In one embodiment of the multi-level semiconductor memory device according to the present invention, each of the information blocks, each of which is obtained by combining two of the encoded information blocks, has a redundant bit as an information bit. Output as added.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the multilevel memory cell has a control gate and a floating gate.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the multi-level memory cell includes an MNOS, a mask R
It is at least one of OM, EEPROM, EPROM, PROM, and flash nonvolatile memory.

In one embodiment of the multi-level semiconductor memory device according to the present invention, the redundant bits are generated based on the two encoded information blocks in correspondence with each of the two encoded information blocks. The number of redundant bits is such that the sum of the information bits of each coded information block and the corresponding redundant bits is the number of bits of the coded sequence.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the redundant bits are generated based on the three encoded information blocks in correspondence with each of the three encoded information blocks. The number of redundant bits corresponding to the information bits of each coded information block is the number of bits of the coded sequence.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the redundant bits correspond to each of the three encoded information blocks by Hamming encoding based on the three encoded information blocks. A first redundant bit is generated, a code string is generated by adding the first redundant bit corresponding to each of the three encoded information blocks, and an exclusive OR of all bits included in each code string is generated. And a second redundant bit is generated corresponding to each of the code strings,
The redundant bits are such that the sum of the bits of each code string and the corresponding second redundant bits is the number of bits of the code string.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the redundant bits are based on the three encoded information blocks and the one encoded information block and the two encoded information blocks.
The sum of the information bits of the one encoded information block and the corresponding redundant bits is generated corresponding to each of the information blocks obtained by combining the two encoded information blocks, and the two encoded information blocks are combined. When the resulting information block is divided, each of the information bits of each of the divided blocks and the sum of the corresponding redundant bits are redundant bits that are the number of bits of the coded sequence.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the redundant bits are generated on the basis of the four encoded information blocks in correspondence with each of the four encoded information blocks. The number of redundant bits corresponding to the information bits of each coded information block is the number of bits of the coded sequence.

In one embodiment of the multilevel semiconductor memory device according to the present invention, the redundant bits correspond to each of the four coded information blocks by Hamming coding based on the four coded information blocks. A first redundant bit is generated, a code string is generated by adding the first redundant bit corresponding to each of the four encoded information blocks, and exclusive OR of all bits included in each code string is generated. And a second redundant bit is generated corresponding to each of the code strings,
The redundant bits are such that the sum of the bits of each code string and the corresponding second redundant bits is the number of bits of the code string.

In one embodiment of the multi-valued semiconductor memory device according to the present invention, the redundant bit is provided in each of the information blocks obtained by combining the two encoded information blocks based on the four encoded information blocks. When each of the information blocks generated correspondingly and obtained by combining the two encoded information blocks is divided into two, the sum of the information bits and the corresponding redundant bits of each of the divided blocks is It is a redundant bit that is the number of bits in the coded sequence.

[0085]

In the multi-level semiconductor memory device of the present invention, even if an error occurs in the multi-level information stored in one memory cell, the information of the minimum number of bits that can be corrected for one code is lost. Error correction can be performed efficiently.

According to another feature of the present invention, logical addresses are hierarchized into an address space having a high access speed and an address space having a relatively low access speed, and the logical address has an address space to which a physical address extends. A one-to-one corresponding partial space is defined as an address space having a high access speed. And a specific component of the storage state of the multi-level memory cell,
For example, data in an address space with a high access speed is stored in the most significant bit. The data of the specific component is determined by one determination value.

When the input logical address is included in the partial space, the logical address specifies the data of the specific component, and the specific component is immediately determined by one determination based on the determination value. The data will be understood and output. Therefore, by storing the data with the highest access frequency in this specific component and storing the data with a relatively low access frequency in the other components, it is possible to read the semiconductor memory device extremely efficiently.

[0088]

[0089]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a multi-value semiconductor memory device according to the present invention;

FIG. 1 shows the main configuration of the multi-value storage EEPROM of this embodiment. In FIG. 1, a memory cell array 1
Has a plurality of memory cells arranged in a matrix. As shown in FIG. 2, each memory cell constituting the memory cell array 1 is a floating gate type memory cell, and a drain 12 and a source 13 each composed of an n-type impurity diffusion layer are formed on a surface region of a p-type silicon substrate 11 respectively. A channel region 14 is formed between them.

The bit line 15 is connected to the drain 12, and the source line 16 is connected to the source 13. Then, a tunnel insulating film 20 made of a SiO ₂ film having a thickness of about 10 nm is formed on the channel region 14, and a floating gate 1 made of low-resistance polysilicon is formed thereon.
7, an interlayer insulating film 18 and a control gate (word line) 19 made of low-resistance polysilicon are sequentially formed.

The word lines 19 are connected to the decoder 2 side by side in the column direction of the memory cell array 1, while the bit lines 15 are connected to the multiplexer 4 side by side in the row direction. The source line 16 is grounded.

When writing data to the multi-value storage EEPROM of the present embodiment configured as described above, the operation mode is set to the program mode. Then, write information is input via the input / output interface I / F8, and an address is input via the input interface I / F7. Since the input address is a logical address, the address is converted by the conversion circuit 9 into a physical address.

The information input via the input / output interface I / F 8 is supplied to the signal control circuit 6, and the information bit dispersing means 6a provided here, as will be described later in detail, converts the information bits. Sorting is performed.

The input information on which the information bits have been rearranged is then supplied to a voltage generation and voltage control circuit 3, where a voltage corresponding to the information bits is generated. And
The generated voltage is applied to memory cell array 1 via decoder 2, and a predetermined threshold voltage is set for each memory cell.

(First Embodiment of Writing Method)
The first embodiment of the writing method of the present invention will be specifically described with reference to FIG.

The multi-valued memory EE targeted in this embodiment
In the PROM, the threshold voltage of each memory cell is set to four values (0, 2, 4, 6 V) corresponding to the stored 2-bit information (00, 01, 10, 11). A value memory, and a code length n,
A crossover method is used in which the code C of the burst error correction capability L is crossed m times.

In rewriting by this device, first,
Each time 8 bits of storage contents are received, this is converted into 4 × 2 information bits (m11, m21, m31, m41)
(M12, m22, m32, m42), and 3 × 2 redundant check bits (p1
1, p21, p31) (p12, p22, p32).

Then, these information bits (m11, m
21, m31, m41) (m12, m22, m32, m
42) and redundant bits (p11, p21, p31) (p
12, p22, p32) and two codewords (m11, m
21, m31, m41, p11, p21, p31),
(M12, m22, m32, m42, p12, p22,
p32).

The two codewords generated in this way are given to the information bit dispersing means 6a, and as shown in FIG.
Arrange them in each row of the 7 arrays. Then, m11 and m12, m21 and m2 are respectively stored in the seven memory cells.
2, m31 and m32, m41 and m42, p11 and p1
2, sequentially stored in combination of p21 and p22 and p31 and p32.

That is, in FIG. 3, the upper bit of the memory cell 1 is m11 and the lower bit is m12. Similarly, the memory cell 2 is m21 and m22, the memory cell 3 is m31 and m32, the memory cell 4 is m41 and m42, Memory cell 5
P11 and p12, memory cell 6 contains p21 and p22, and memory cell 7 contains p31 and p32.

As will be described later in detail, each code word can be corrected even if one error occurs.
As described above, even if the threshold voltage of the third memory cell changes and a burst error of length 2 occurs, only one error is generated for each code word, so that correction is possible. That is, the threshold voltage of one of the seven memory cells changes, and for example, the storage content of “01” is “1”.
Even if a burst error that changes to "0" occurs, it can be corrected.

(Second Embodiment of Writing Method)
A second embodiment of the writing method according to the present invention will be described.

In the device targeted by the writing method of the present embodiment, the threshold voltage of each memory cell is such that the stored 3-bit information (000, 001, 010, 011, 100,
101, 110, 111), eight values (0, 1,
2, 3, 4, 5, 6, 7V).

In rewriting by this device, first,
Each time 12 bits of storage contents are received, this is 4 × 3
Bit information bits (m11, m21, m31, m4
1) (m12, m22, m32, m42) (m13, m
23, m33, m43), and 3 × 3 redundant bits (p11, p21, p31) are obtained from the information bits.
(P12, p22, p32) (p13, p23, p3
Obtain 3).

Then, the three code words (m11, m21,
m31, m41, p11, p21, p31) (m12,
m22, m32, m42, p12, p22, p32)
(M13, m23, m33, m43, p13, p23,
p33) are arranged in each row of a 3 × 7 array, and as shown in FIG. 4, m11, m12, and m are stored in seven memory cells, respectively.
13, m21, m22, and m23, m31, m32, and m3
3, m41, m42 and m43, p11, p12 and p1
3, p21, p22 and p23, p31, p32 and p33
Is stored.

That is, in FIG. 4, the upper bit of the memory cell 1 is m11 and the lower bit is m12. Similarly, the memory cell 2 is m21 and m22, the memory cell 3 is m31 and m32, the memory cell 4 is m41 and m42, Memory cell 5
M51 and m52, m61 and m62 in the memory cell 6, and m71 and m72 in the memory cell 7.

Each code word can be corrected even if one error occurs. Therefore, as shown in FIG. 4, even if a burst error of length 3 occurs in the third memory cell, each code word can be corrected. Since one error is caused for the code word, it can be corrected. That is, of the seven memory cells, the threshold voltage of one memory cell changes to, for example, "10
Even if a burst error in which the storage content of "0" changes to "011" occurs, it can be corrected.

Next, several modifications of the second embodiment of the writing method will be described.

-Variation 1- In a device targeted by the writing method of this embodiment, the threshold voltage of each memory cell is such that the 3-bit information (0
00, 001, 010, 011, 100, 101, 11
8 values (0, 1, 2, 3, 4,
5, 6 and 7 V). In the first modification, of the bits forming the codeword,
An example will be described in which up to two errors follow a predetermined linear coding rule that allows error correction.

In rewriting by this device, first,
Each time the storage content receives a predetermined bit, for example, k bits, it is divided into three (k / 3) information bits. Then, a redundant bit is obtained from each information bit, and a 14-bit code word (m11, m21, m31, m
41, m51, m61, m71, m12, m22, m3
2, m42, m52, m62, m72) and a 7-bit codeword (m13, m23, m33, m43, m53, m
63, m73). That is, in each of the 14-bit and 7-bit code words, a predetermined number of bits are information bits, and the rest are redundant bits for error correction.

Next, a 14-bit code word (m11, m2
1, m31, m41, m51, m61, m71, m1
2, m22, m32, m42, m52, m62, m7
2) is converted into a 7-bit code string (m11, m21, m3).
1, m41, m51, m61, m71) (m12, m2
2, m32, m42, m52, m62, m72). Then, the code string a (m11, m21, m31, m
41, m51, m61, m71) and the code string b (m1
2, m22, m32, m42, m52, m62, m7
2) and one codeword c (m13, m23, m33, m4
3, m53, m63, m73) are arranged in each row of the 3 × 7 array, and as shown in FIG. 5, seven memory cells are respectively m11, m12, and m13, m21, m22, and m2.
3, m31, m32, and m33, m41, m42, and m4
3, m51, m52 and m53, m61, m62 and m6
3. Store m71, m72 and m73.

That is, in FIG. 5A, the memory cell 1
The upper bit is m11, the middle bit is m12, and the lower bit is m13. Similarly, m21 and m2 are stored in the memory cell 2.
2 and m23, and m31, m32 and m33 in the memory cell 3,
M41, m42 and m43 in memory cell 4, memory cell 5
M51, m52 and m53 in the memory cell 6 and m61 and m in the memory cell 6.
62 and m63, and m71, m72 and m73 in the memory cell 7
Is stored.

The code strings a and b and the code word c can be corrected even if one error occurs, and therefore, for example, as shown in FIG. Even if a burst error occurs, one error is generated for each of the codewords a and b and the code sequence c.
Since the code word composed of b has two errors, it can be corrected. In other words, even if the threshold voltage of one of the seven memory cells changes and a burst error occurs in which the storage content of “100” changes to “011”, correction is possible. It is.

-Variation 2- In the device targeted by the writing method of this embodiment, the threshold voltage of each memory cell is such that the 3-bit information (0
00, 001, 010, 011, 100, 101, 11
8 values (0, 1, 2, 3, 4,
5, 6 and 7 V). In the second modification, of the bits forming the codeword,
An example in which an error correction is possible for up to one error and an encoding rule that allows error detection for up to two errors will be described.

In rewriting by this device, first,
Each time 12 bits of storage contents are received, this is 4 × 3
Bit information bits (m11, m21, m31, m4
1) (m12, m22, m32, m42) (m13, m
23, m33, m43), and 3 × 3 redundant bits (p1) from the information bits by Hamming coding.
1, p21, p31) (p12, p22, p32) (p
13, p23, p33).

Subsequently, three code strings (m11, m21,
m31, m41, p11, p21, p31) (m12,
m22, m32, m42, p12, p22, p32)
(M13, m23, m33, m43, p13, p23,
p33), the EX-
OR, and the resulting redundant bits q
1, q2, and q3 are added to each code string, and three code words (m11, m21, m31, m41, p11, p21,
p31, q1) (m12, m22, m32, m42, p
12, p22, p32, q2) (m13, m23, m3
3, m43, p13, p23, p33, q3).

Then, these three codewords are arranged in each row of a 3 × 8 array, and as shown in FIG. 5B, m11, m12 and m13, m21 and m13 are stored in eight memory cells, respectively.
22 and m23, m31 and m32 and m33, m41 and m4
2 and m43, p11 and p12 and p13, p21 and p22
And p23, p31 and p32 and p33, q1 and q2 and q3
Is stored.

That is, in FIG. 5B, the memory cell 1
The upper bit is m11, the middle bit is m12, and the lower bit is m13. Similarly, m21 and m2 are stored in the memory cell 2.
2 and m23, and m31, m32 and m33 in the memory cell 3,
M41, m42 and m43 in memory cell 4, memory cell 5
P11, p12 and p13, and p21 and p in the memory cell 6.
22 and p23, and p31, p32 and p3 in the memory cell 7
3. q1, q2, and q3 are stored in the memory cell 8.

Each code word can be corrected even if one error occurs. Therefore, as shown in FIG. 5B, for example, a burst error of length 3 occurs in the third memory cell. Can be corrected because each codeword has one error. That is, even if the threshold voltage of one of the eight memory cells changes and a burst error occurs in which the storage content of “100” changes to “011”, correction is possible. It is. Further, although it seems to be extremely rare, for example, if another memory cell has a burst error of length 1-3, at least one codeword will have two errors. At this time, the two errors can be detected.
One can be corrected.

(Third Embodiment of Writing Method)
A third embodiment of the writing method according to the present invention will be described.

In the device targeted by the writing method of this embodiment, the threshold voltage of each memory cell is such that 4-bit information (0000, 0001, 0010, 0011,
0100, 0101, 0110, 0111, 1000,
1001, 1010, 1011, 1100, 1101,
1110, corresponding to 16 values, for example, (0, 1, 1.25, 1.5, 1.75, 2, 2.2)
5, 2.5, 2.75, 3, 3.25, 3.5, 3.7
5, 4, 4.25, 4.5 V).

In rewriting by this device, first,
Each time 16 bits of storage contents are received, this is 4 × 4
Bit information bits (m11, m21, m31, m4
1) (m12, m22, m32, m42) (m13, m
23, m33, m43) (m14, m24, m34, m
44), and 3 × 4 redundant bits (p11, p21, p31) (p12, p2)
2, p32) (p13, p23, p33) (p14, p
24, p34).

Then, the four codewords (m11, m21,
m31, m41, p11, p21, p31) (m12,
m22, m32, m42, p12, p22, p32)
(M13, m23, m33, m43, p13, p23,
p33) (m14, m24, m34, m44, p14,
p24, p34) are arranged in each row of the 4 × 7 array, and as shown in FIG.
12, m13 and m14, m21, m22, m23 and m2
4, m31, m32, m33 and m34, m41 and m42
And m43 and m44, p11 and p12, p13 and p14,
p21, p22, p23 and p24, p31, p32 and p
33 and p34 are stored.

That is, in FIG. 6, the first bit of the memory cell 1 is m11, the second bit is m12, and the third bit is m11.
The 13th and 4th bits become m14. Similarly, the memory cell 2
M21, m22, m23, and m24, and m in the memory cell 3.
31 and m32, m33 and m34, and m41 in the memory cell 4
, M42, m43, and m44, and p11 and p in the memory cell 5.
12, p13 and p14, and p21 and p22 in the memory cell 6.
And p23 and p24, and p31, p32 and p in the memory cell 7.
33 and p34 are stored.

Each code string can be corrected even if one error occurs. Therefore, as shown in FIG. 6, even if a burst error of length 4 occurs in the third memory cell, for example, Since a single error occurs in the code string, it can be corrected. That is, of the seven memory cells, the threshold voltage of one memory cell changes to, for example, "10
Even if a burst error in which the stored content of "00" changes to "0111" occurs, it can be corrected.

Next, some modifications of the third embodiment of the writing method will be described.

-Modification 1- In the device targeted by the writing method of the present embodiment, the threshold voltage of each memory cell is such that the 4-bit information (0
000, 0001, 0010, 0011, 0100, 0
101, 0110, 0111, 1000, 1001, 1
010, 1011, 1100, 1101, 1110, 1
111), 16 values, for example, (0, 1, 1.2)
5, 1.5, 1.75, 2, 2.25, 2.5, 2.7
5, 3, 3.25, 3.5, 3.75, 4, 4.25,
It is a 16-valued memory set to 4.5 V). In this modified example, a case will be described in which, according to a predetermined linear coding rule capable of correcting up to two errors among bits constituting a code word, error correction is possible.

In rewriting by this device, first,
Each time the storage content receives a predetermined bit, for example, p bits, it is divided into four (p / 3) information bits. Then, redundant bits are obtained from each information bit, and two 14-bit code words (m11, m21, m3) are obtained.
1, m41, m51, m61, m71, m12, m2
2, m32, m42, m52, m62, m72) (m1
3, m23, m33, m43, m53, m63, m7
3, m14, m24, m34, m44, m54, m6
4, m74). That is, in each of these 14-bit code words, a predetermined number of bits are information bits, and the rest are redundant bits for error correction.

Next, each of the 14-bit code words (m11, m
21, m31, m41, m51, m61, m71, m1
2, m22, m32, m42, m52, m62, m7
2) (m13, m23, m33, m43, m53, m6
3, m73, m14, m24, m34, m44, m5
, M64, m74) are converted into code strings (m11, m21, m31, m41, m51, m61,
m71) (m12, m22, m32, m42, m52,
m62, m72) and (m13, m23, m33, m4
3, m53, m63, m73) (m14, m24, m3
4, m44, m54, m64, m74). Then, each code string is arranged in each row of the 4 × 7 array, and FIG.
As shown in (a), each of the seven memory cells has m
11, m12, m13, and m14, m21, m22, and m2
3, m24, m31, m32, m33, m34, m41
M42, m43, m44, m51, m52, m53, m54, m61, m62, m63, m64, m71, m
72, m73 and m74 are stored.

That is, in FIG. 7A, the memory cell 1
The first bit is m11, the second bit is m12, the third bit is m13, and the fourth bit is m14. Similarly, m21, m22, m23, and m24 are stored in the memory cell 2, and m31, m32, and m33 are stored in the memory cell 3. m34, m41, m42, m43, and m44 in the memory cell 4, and m5 in the memory cell 5
1, m52, m53, and m54, m61, m62, m63, and m64 in the memory cell 6, and m71 and m7 in the memory cell 7.
2, m73 and m74 are stored.

Each code string can be corrected even if one error occurs. Therefore, as shown in FIG. 7, even if a burst error of length 4 occurs in the third memory cell, for example, One error occurs in the code string, and at this time, two errors occur in each code word composed of the two code strings, so that correction is possible. In other words, the threshold voltage of one of the seven memory cells changes, and for example, the storage content of “1000” becomes “0111”.
Can be corrected even if a burst error that changes to

-Variation 2-In the device targeted by the writing method of the present embodiment, the threshold voltage of each memory cell is the 4-bit information (0
000, 0001, 0010, 0011, 0100, 0
101, 0110, 0111, 1000, 1001, 1
010, 1011, 1100, 1101, 1110, 1
111), 16 values, for example, (0, 1, 1.2)
5, 1.5, 1.75, 2, 2.25, 2.5, 2.7
5, 3, 3.25, 3.5, 3.75, 4, 4.25,
It is a 16-valued memory set to 4.5 V). In this modified example, a case will be exemplified where, according to a coding rule in which up to one error can be corrected and up to two errors can be detected in each bit constituting a codeword. .

In rewriting by this device, first,
Each time 16 bits of storage contents are received, this is 4 × 4
Bit information bits (m11, m21, m31, m4
1) (m12, m22, m32, m42) (m13, m
23, m33, m43) (m14, m24, m34, m
44), and 3 × 4 redundant bits (p11, p21, p3) are converted from the information bits by Hamming coding.
1) (p12, p22, p32) (p13, p23, p
33) (p14, p24, p34) is obtained.

Subsequently, four code strings (m11, m21,
m31, m41, p11, p21, p31) (m12,
m22, m32, m42, p12, p22, p32)
(M13, m23, m33, m43, p13, p23,
p33) (m14, m24, m34, m44, p14,
p24, p34), calculate the EX-OR of all 7 bits, and add the resulting redundant bits q1, q2, q3, q4 to each code string,
Four codewords (m11, m21, m31, m41, p1
1, p21, p31, q1) (m12, m22, m3
2, m42, p12, p22, p32, q2) (m1
3, m23, m33, m43, p13, p23, p3
3, q3) (m14, m24, m34, m44, p1
4, p24, p34, q4).

Then, these four code words are arranged in each row of a 4 × 8 array, and as shown in FIG. 7B, the eight memory cells have m11, m12, m13, m14, m14 respectively.
21, m22, m23, and m24, m31, m32, and m3
3 and m34, m41 and m42, m43 and m44, p11
And p12 and p13 and p14, p21 and p22 and p23 and p24, p31 and p32, p33 and p34, and q1 and q2.
And q3 and q4.

That is, in FIG. 7B, the memory cell 1
The first bit is m11, the second bit is m12, the third bit is m13, and the fourth bit is m14. Similarly, m21, m22, m13, and m14 are stored in the memory cell 2, and m31, m32, and m33 are stored in the memory cell 3. m34, m41, m42, m43, and m44 in the memory cell 4, and m5 in the memory cell 5
1, m52, p13, and p14, m61, m62, p23, and p24 in the memory cell 6, and m71 and m7 in the memory cell 7.
2, p33 and p34, and q1, q2 and q3 in the memory cell 8.
And q4.

Each code word can be corrected even if one error occurs. Therefore, as shown in FIG. 7B, for example, a burst error of length 4 occurs in the third memory cell. Can be corrected because each codeword has one error. In other words, even if the threshold voltage of one of the eight memory cells changes and a burst error occurs in which the storage content of “1000” changes to “0111”, correction is possible. It is. Furthermore, it seems very unlikely that, for example, if another memory cell has a burst error of length 1-4,
There will be two errors for at least one codeword,
At this time, the two errors can be detected, and one of them can be corrected.

It should be noted that other than the encoding method shown in each modification of the second and third embodiments of the writing method, there are other methods which are considered to be useful. For example, first, 56 bits of “0” data are added to 64 pieces of original data to make a total of 12 bits.
Obtain 0-bit information bits. Subsequently, a 127-bit length Hamming code is created from the 120 information bits. Subsequently, EX-OR of all 127 bits is calculated, and the result is used to obtain an additional 128-bit length code. Then, the previously added 56-bit “0” is removed, and 7
Obtain a 2-bit long codeword. In this encoding method, error correction is performed up to one error of each bit constituting a codeword, and error detection is possible up to two errors.
SEC / DED code (single-error-cor
recting / double-error-detecting code).

Next, a specific example will be described in which even if one error occurs for one code word, correction can be made. Table 1 below
Indicates a Hamming code obtained by adding three redundant bits to four information bits.

[0141]

[Table 1]

In this code, the first, second and fourth digits are redundant bits, and are (1, 3, 5, 7), (2, 3, 6, 7) and (4, 5, 6, 7). Redundant bits are determined so that each set of digits has an even parity. For example, when the code “0111100” corresponding to the decimal number “12” is written and an error occurs and is read as “0101100”, as shown in Table 1, the digit having the error is set to 2 Since the error can be obtained in a base number (011 in this case), even if an error occurs, it can be easily and reliably corrected.

Note that this code can be extended to a case where the number of information bits is even larger, and the number m of redundant bits required for n information bits is expressed by the following equation. 2 ^m = n + m + 1 (1 formula)

In the above description, the case where the present invention is applied to a nonvolatile memory device having a floating gate type memory cell has been described as an example. It is not limited to the MNOS type, but may be the MNOS type. In addition, the present invention provides not only an EEPROM but also an EPROM and a PROM, and further, for example, a mask that obtains a storage state by changing a threshold value by controlling the amount of impurities implanted into a channel region of a field effect transistor. It is also possible to apply to a ROM. Also, the case of four values and eight values has been described as an example, but the present invention is not limited to these values.

Although the method of obtaining an error correcting code has been described by taking the crossing method as an example, any error correcting code that can correct an error having a burst length corresponding to the amount of information stored in a memory cell will be described. The method may be, for example, a cyclic code or a shortened cyclic code.

Next, a preferred embodiment of the reading method of the present invention will be described in detail with reference to the drawings.

(First Embodiment of Reading Method) First,
A first embodiment of the reading method of the present invention will be described. In the first embodiment, a multi-value storage EEPROM and a reading method therefor will be exemplified as a semiconductor storage device.

At the time of reading operation, first, a logical address signal is externally input to the conversion circuit 9 via the input I / F 7, and a physical address signal corresponding to a real memory cell is calculated from the logical address signal. Subsequently, the physical address signal is input to the signal control circuit 6. Signal control circuit 6
Determines the word line 19 and bit line 15 to be selected in accordance with the input physical address signal, and instructs the decoder 2 and the multiplexer 4 on the result. In response to this instruction, the decoder 2 sets the word line 19 to the multiplexer 4
Select the bit lines 15 respectively.

The signal control circuit 6 determines the magnitude of the voltage to be applied to the control gate 19 of the selected memory cell, and instructs the voltage control circuit 3 on the result. The voltage control circuit 3 is connected to the selected word line 1 via the decoder 2.
9 is applied with a predetermined voltage. On the other hand, a predetermined voltage is applied to the selected bit line 15 by the multiplexer 4. Then, whether or not a current flows through the selected bit line 15 is determined by the state of the threshold value of the selected memory cell.

The current state of the selected bit line 15 is transmitted from the multiplexer 4 to the sense amplifier 5. The sense amplifier 5 detects the presence or absence of a current on the selected bit line 15 and transmits the result to the signal control circuit 6. The signal control circuit 6 determines the next voltage to be applied to the control gate 19 of the selected memory cell based on the detection result of the sense amplifier 5, and instructs the voltage control circuit 3 of the result. Further, the signal control circuit 6 repeats the above procedure and outputs the storage data of the selected memory cell finally obtained via the output I / F 8.

FIG. 8 shows a flowchart of the reading method according to the first embodiment. In the first embodiment,
4-valued multi-valued storage EEPR with 8 megabit storage capacity
An example of OM will be described. This 4-valued multi-value storage EEPROM
M has a logical address space of [00 0000] to [7F FFFF] and a physical address space of [00 0000] to [3F FFFF] in hexadecimal notation. Also, each memory cell is
2-bit (= 4 values) data (00, 01, 10, 1)
1), and a threshold voltage of (0 V, 2 V, 4 V, 6 V) is set for each memory cell in accordance with these data.

When the physical address of a predetermined memory cell is Ap, the memory cell stores the data of the logical address Ap in the upper bits of the two-bit components.
The data of the logical address (Ap + [40 0000]) is stored in the lower bits.

In other words, at the time of the data rewriting operation, the logical addresses Al of [00 0000] to [3F FFFF]
When the data to be stored (0 or 1) is specified, the upper bits of the memory cell at the physical address Al are rewritten to the specified data.

On the other hand, during the data rewriting operation,
When the logical address Al of [40 0000] to [7F FFFF] and the data to be stored (0 or 1) are specified, the lower bit of the memory cell existing in the physical address (Al- [40 0000]) is specified. Rewritten with data.

First, when a read command is received from the outside (step S1) and a logical address signal is input to the input I / F 7 (step S2), the signal control circuit 6 sets the logical address signal to [00 0000]. ] To [3F FFFF] (step S3).

Here, the logical address signal is [00 0000].
If [3F FFFF], the logical address matches the physical address, and the data requested to be read is 2
It can be seen that this is the upper bit of the bits (step S4). In this case, the control gate 19 of the selected memory cell
To the drain 12-source 13
It is detected through the selected bit line 15 and the sense amplifier 5 whether or not a current flows between them (step S5).

In step S5, when a current flows between the drain 12 and the source 13 of the selected memory cell, that is, when the selected memory cell is turned on, the threshold voltages of the selected memory cell are 0V and 2V. Therefore, among the components in the storage state of this memory cell, the upper bit is determined to be “0”, and this data is immediately output from the output I / F 8 (step S6).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S5, the threshold voltage of this memory cell is either 4V or 6V. Among the components of the state, it is determined that the upper bit is "1", and this data is immediately output from the output I / F 8 (step S7).

In step S3, input I / F
7 is [40 0000]-[7FF
FFF], the logical address does not match the physical address, and the physical address = (logical address− [40 0000
]), Indicating that the data requested to be read is the lower bit of the two bits (step S8). In this case, a determination voltage of 3 V is applied to the control gate 19 of the selected memory cell, and whether or not a current flows between the drain 12 and the source 13 is detected through the selected bit line 15 and the sense amplifier 5 (Step S9).

In step S9, when a current flows between the drain 12 and the source 13 of the selected memory cell,
Since the threshold voltage of the memory cell is either 0 V or 2 V, the signal control circuit 6 instructs the voltage control circuit 3 to apply a 1 V determination voltage to the control gate 19 of the selected memory cell. (Step S10).

In step S10, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold voltage of the memory cell is 0 V, and the component of the storage state of this memory cell is The lower bit is determined to be "0", and this data is output to the output I / F.
8 (step S11).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S10, the threshold voltage of that memory cell is 2 V, and the component of the storage state of this memory cell is , The lower bit is determined to be “1”, and this data is output to I / O
Output from F8 (step S12).

When no current flows between the drain 12 and the source 13 of the selected memory cell in step S9, the threshold voltage of the selected memory cell is 4V or 6V.
Therefore, the signal control circuit 6 instructs the voltage control circuit 3 to apply a 5V determination voltage to the control gate 19 of the selected memory cell (step S1).
3).

If a current flows between the drain 12 and the source 13 of the selected memory cell in step S13, the threshold voltage of the memory cell is 4 V, and the component of the storage state of this memory cell is The lower bit is determined to be "0", and this data is output to the output I / F.
8 (step S12).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S13, the threshold voltage of that memory cell is 6 V, and the component of the storage state of this memory cell is , The lower bit is determined to be “1”, and this data is output to I / O
Output from F8 (step S13).

Here, referring to FIG. 1 and FIG. 9, a decision voltage of 1, 3 or 5 V in the above-mentioned reading method is applied to the control gate 19 of the selected memory cell, and a current flows between the drain 12 and the source 13. A method of determining whether or not the determination is made will be described.

For example, in step 4 of FIG. 8, when the signal control circuit 6 receives the physical address from the conversion circuit 9 and finds that the data requested to be read is the upper bit, the signal control circuit 6 It is determined that the voltage to be applied to the control gate 19 is 3 V, and the result is transmitted to the voltage control circuit 3. As shown in FIG. 9, the voltage control circuit 3 includes a 1V reference voltage generation circuit 3a, a 3V reference voltage generation circuit 3b, and a 5V reference voltage generation circuit 3c.
In this example, the reference voltage generation circuit 3b generates a voltage of 3V and outputs it to the switch circuit 55.

Further, the signal control circuit 6 determines a word line to be selected according to the input physical address signal, and transmits the result to the decoder 2. In response, the decoder 2
Outputs a decode signal to the switch circuit 55.

The switch circuit 55 receiving the 3V reference voltage and the decode signal applies a 3V reference voltage to the word line to be selected. Memory cell 1a to be selected in cell array 1
Is determined by the sense amplifier 5 as to whether or not a current flows between the drain 12 and the source 13. Sense amplifier 5
Is the voltage from the memory cell 1a and the reference voltage generation circuit 56
, And the result is transmitted to the signal control circuit 6.

On the basis of the detection result of the sense amplifier 5, the signal control circuit 6 applies a voltage of 1 V to the memory cell 1a.
Alternatively, 5 V is determined and transmitted to the voltage control circuit 3. And
The signal control circuit 6 outputs the finally obtained storage data of the memory cell 1a via the output I / F8.

As described above, in the first embodiment, the logical addresses [00 0000] to [7F FFFF] are stored in the address space A ₁ (logical address [00 0
000] to [3F FFFF]) and the address space A _{2 with} relatively slow access speed (logical address [40 0000] to [7F FFF]
F])) and logical addresses [00 0000] to [7F
FFFF], physical addresses [00 0000] to [3F FFF
F] is the address space and one-to-one corresponding subspace (logical address [00 0000] to [3F FFFF]) fast address space A ₁ access speed of tensioning. The specific components of the memory state of the memory cell, wherein the store data of the address space A ₁ to the upper bits.

In the case where the input logical address is included in the partial space (logical address [00 0000] to [3F FFFF]
]), The logical address designates the data of the upper bit, and the data of the upper bit is immediately recognized and output by one determination based on the determination voltage of 3V. In this case, the reading speed is about twice as fast as when each threshold voltage is checked based on all the judgment voltages. Therefore, by storing the data with the highest access frequency in the upper bits and the data with a relatively low access frequency in the lower bits, the operator (programmer) has a single high-speed storage device. Multi-value storage EEPROM that looks as if it is very efficient
Can be read.

The data and the program preferably stored in the multi-value storage EEPROM include, for example, a BIOS of an arithmetic device having a high access frequency, and a document file having a relatively low access frequency. . In this case, the former may be stored in the upper bits having a higher access speed, and the latter may be stored in the lower bits having a relatively slow access speed.

(Second Embodiment of Reading Method) Next,
A second embodiment of the reading method according to the present invention will be described. In this embodiment, as in the first embodiment, a multi-valued storage EEPROM and a method for reading out the same will be exemplified as a semiconductor memory device. The main configuration of the multi-value storage EEPROM is the same as that of the first embodiment, but differs from the first embodiment in that the multi-value storage EEPROM is an eight-valued memory having a storage capacity of 12 megabits. Note that the same components as those of the multi-value storage EEPROM of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 10 is a flowchart of a reading method according to the second embodiment. In the second embodiment, an eight-valued multivalued storage E having a storage capacity of 12 megabits is used.
An example of an EPROM will be described. This 8-valued multi-valued memory EE
PROM is expressed in hexadecimal notation from [00 0000] to [BF FFFF
] And the address space of [00 0000]-[3F FFFF
] Physical address space. In addition, each memory cell stores 3-bit (= 8 values) data (00000, 000).
1,010,011,100,101,110,11
1), and (0V, 1V, 2V, 3V, 4V, 5V, 6V) are stored in each memory cell in accordance with these data.
V, 7V).

When the physical address of a predetermined memory cell is Ap, this memory cell stores the data of the logical address Ap in the most significant bit of the three-bit components, and stores the logical address Ap in the middle bit. (Ap + [40 0000
]), And the data of the logical address (Ap + [80 0000]) is stored in the least significant bit.

In other words, in the data rewriting operation, when the logical address Al of [00 0000] to [3F FFFF] and the data (0 or 1) to be stored are specified, the memory cell existing at the physical address Al The most significant bit is rewritten with the specified data.

In the data rewriting operation,
When the logical address Al of [40 0000] to [7F FFFF] and the data to be stored (0 or 1) are specified, the middle bit of the memory cell existing at the physical address (Al- [40 0000]) is specified. Is rewritten to the data.

Further, in the data rewriting operation,
When the logical address Al of [80 0000] to [BF FFFF] and the data to be stored (0 or 1) are specified, the least significant bit of the memory cell existing at the physical address (Al- [80 0000]) is specified. Is rewritten to the data.

First, when a read command is received from the outside (step S21) and a logical address signal is input to the input I / F 7 (step S22), the signal control circuit 6 sets the logical address signal to [00 0000]. ] To [3F FFFF] (step S23).

Here, the logical address signal is [00 0000].
If [3F FFFF], the logical address matches the physical address, and the data requested to be read is 3
It can be seen that this is the most significant bit of the bits (step S24). In this case, a determination voltage of 3.5 V is applied to the control gate 19 of the selected memory cell, and whether or not a current flows between the drain 12 and the source 13 is determined by the selection bit line 15.
And through the sense amplifier 5 (step S2
5).

In step S25, when a current flows between the drain 12 and the source 13 of the selected memory cell, that is, when the selected memory cell becomes conductive,
The threshold voltage of this memory cell is 0 V, 1 V, 2 V, 3
V, and 3-bit data specified by these threshold voltages are “000” and “00”, respectively.
1 ”,“ 010 ”, and“ 011 ”, it is determined that the most significant bit of the storage state component of this memory cell is“ 0 ”, and this data is immediately output to the output I / F 8.
(Step S26).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S25, the threshold voltage of this memory cell is 4V, 5V, 6
V, 7V, and the 3-bit data specified by these threshold voltages are “100”,
Since they are “101”, “110”, and “111”, it is determined that the most significant bit of the storage state component of this memory cell is “1”, and this data is immediately output from the output I / F 8. Output (Step S27).

In step S23, the input I /
The logical address signal input to F7 is [00 0000]-[3F
If not, it is determined whether or not the input logical address signal is [400000] to [7F FFFF] (step S28).

Here, the logical address signal is [40 0000]
When [7F FFFF], the logical address does not match the physical address, and the physical address = (logical address−
[40 0000]), indicating that the data requested to be read is the middle-order bit of the three bits (step S29). In this case, a determination voltage of 3.5 V is applied to the control gate 19 of the selected memory cell and the drain 1
Whether or not a current flows between the source 2 and the source 13 is detected through the selected bit line 15 and the sense amplifier 5 (step S30).

In step S30, if a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is 0V, 1V, 2V, 3
V. Here, 3-bit data specified by threshold voltages of 0 V and 1 V are “000”, “00”
1 ”, the middle bits are both“ 0 ”, and 2
The 3-bit data specified by the threshold voltages V and 3V are "010" and "011", and the middle bits are both "1". Therefore, in order to determine the middle bit, the signal control circuit 6 controls the control gate 1 of the selected memory cell.
9 is instructed to apply a determination voltage of 1.5 V to the voltage control circuit 3 (step S31).

If a current flows between the drain 12 and the source 13 of the selected memory cell in step S31, the threshold voltage of the memory cell is 0 V or 1 V, and Of the ingredients,
The middle bit is determined to be "0", and this data is output from the output I / F 8 (step S32).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S31, the threshold voltage of that memory cell is 2 V or 3 V, and the storage state of this memory cell is , The middle bit is determined to be “1”, and this data is output from the output I / F 8 (step S33).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S30, the threshold voltage of the selected memory cell is 4V.
5V, 6V, or 7V. Here, 4V, 5
The 3-bit data specified by the threshold voltage of V is "1"
00 "and" 101 ", the middle bits are both" 0 ", and the 3-bit data specified by the threshold voltages of 6V and 7V are" 010 "and" 011 " Therefore, in order to determine the middle bit, the signal control circuit 6 applies a determination voltage of 5.5 V to the control gate 19 of the selected memory cell. (Step S34).

When a current flows between the drain 12 and the source 13 of the selected memory cell in step S34, the threshold voltage of the memory cell is 4V or 5V, and Of the ingredients,
The middle bit is determined to be "0", and this data is output from the output I / F 8 (step S32).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S34, the threshold voltage of that memory cell is 6 V or 7 V, and the storage state of this memory cell is , The middle bit is determined to be “1”, and this data is output from the output I / F 8 (step S33).

In step S28, the input I /
The logical address signal input to F7 is [40 0000]-[7F
FFFF], the logical address signal is [80 000
0] to [BF FFFF], that is, physical address = (logical address− [80 0000]), and it can be seen that the data requested to be read is the least significant bit of the three bits (step S35). . In this case, a determination voltage of 3.5 V is applied to the control gate 19 of the selected memory cell,
It is determined whether a current flows between the drain 12 and the source 13 or not.
Detection is performed through the selected bit line 15 and the sense amplifier 5 (step S36).

In step S36, if a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is 0V, 1V, 2V, 3
V, and the 3-bit data specified by each of these threshold voltages is “000”, “00”, respectively.
1 ”,“ 010 ”, and“ 011 ”, it is not possible to specify the least significant bit at this stage yet, so to specify the least significant bit, the signal control circuit 6
First, the voltage control circuit 3 is instructed to apply a determination voltage of 1.5 V to the control gate 19 of the selected memory cell (step S37).

In step S37, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is 0 V or 1 V, and is specified by each of these threshold voltages. The 3-bit data is “000” or “001”. Therefore,
In order to specify the least significant bit, the signal control circuit 6 instructs the voltage control circuit 3 to apply a determination voltage of 0.5 V to the control gate 19 of the selected memory cell (step S3).
8).

If a current flows between the drain 12 and the source 13 of the selected memory cell in step S38, the threshold voltage of the memory cell is 0 V, and the component of the storage state of this memory cell is Of these, the least significant bit is determined to be “0”, and this data is output to I / O
Output from F8 (step S39).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S38, the threshold voltage of that memory cell is 1 V, and the component of the storage state of this memory cell is Is determined that the least significant bit is "1", and this data is output to I
/ F8 (step S40).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S37, the threshold value of the memory cell is 2 V or 3 V, and each of these threshold voltages Is 3-bit data "010" or "011".
Therefore, to specify the least significant bit, the signal control circuit 6
Commands the voltage control circuit 3 to apply a determination voltage of 2.5 V to the control gate 19 of the selected memory cell (step S41).

When a current flows between the drain 12 and the source 13 of the selected memory cell in step S41, the threshold voltage of the memory cell is 2 V, and the component of the storage state of this memory cell is Of these, the least significant bit is determined to be “0”, and this data is output to I / O
Output from F8 (step S39).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S41, the threshold voltage of the memory cell is 3 V, and the component of the storage state of this memory cell is , The lowest bit is determined to be “1”, and this data is output to I / O
Output from F8 (step S40).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S36, the threshold value of the selected memory cell is 4V, 5.
V, 6V, or 7V, and the 3-bit data specified by each of these threshold voltages is "10
Since the bits are 0, 101, 110, and 111, the least significant bit cannot be specified at this stage, so the signal control circuit 6 first selects the least significant bit to specify the least significant bit. The voltage control circuit 3 is instructed to apply a determination voltage of 5.5 V to the control gate 19 of the memory cell (step S42).

In step S42, when a current flows between the drain 12 and the source 13 of the selected memory cell, the threshold value of the memory cell is 4 V or 5 V, and is specified by each of these threshold voltages. The 3-bit data is “100” or “101”. Therefore,
In order to specify the least significant bit, the signal control circuit 6 instructs the voltage control circuit 3 to apply a determination voltage of 4.5 V to the control gate 19 of the selected memory cell (step S4).
3).

When a current flows between the drain 12 and the source 13 of the selected memory cell in step S43, the threshold voltage of the memory cell is 4 V, and the component of the storage state of this memory cell is Of these, the least significant bit is determined to be “0”, and this data is output to I / O
Output from F8 (step S39).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S43, the threshold voltage of that memory cell is 5 V, and the component of the storage state of this memory cell is Is determined that the least significant bit is "1", and this data is output to I
/ F8 (step S40).

If no current flows between the drain 12 and the source 13 of the selected memory cell in step S42, the threshold value of the memory cell is 6V or 7V. The 3-bit data designated by “1” is “110” or “111”.
Therefore, to specify the least significant bit, the signal control circuit 6
Commands the voltage control circuit 3 to apply a determination voltage of 6.5 V to the control gate 19 of the selected memory cell (step S44).

When a current flows between the drain 12 and the source 13 of the selected memory cell in step S44, the threshold voltage of the memory cell is 6 V, and the component of the storage state of the memory cell is Of these, the least significant bit is determined to be “0”, and this data is output to I / O
Output from F8 (step S39).

On the other hand, if no current flows between the drain 12 and the source 13 of the selected memory cell in step S44, the threshold voltage of that memory cell is 7 V, and the component of the storage state of this memory cell is Is determined that the least significant bit is "1", and this data is output to I
/ F8 (step S40).

As described above, in the second embodiment, the logical addresses [00 0000] to [BF FFFF] are hierarchized into an address space having a high access speed and an address space having a relatively low access speed. Here, an address space having a high access speed is referred to as an address space A ₁ (logical address [00 0000] to [3F FFFF]), and an address space having a relatively low access speed is further subdivided to access the address space A _1. The high-speed address space is defined as address space A ₂ (logical addresses [40 0000] to [BFFFFF
]), And stratified as the address space A ₂ in then in address fast address space access speed space A ₃ (logical address [40 0000] to [BF FFFF]).

[0208] Logical address [00 0000]-[7F FFFF]
Among them, the physical address [00 0000] to address space and one-to-one corresponding subspace (logical address [00 0000] to [3F FFFF]) fast address space A ₁ access speed of the [3F FFFF] spanned the . The specific components of the memory state of the memory cell, wherein the store data of the address space A ₁ to the most significant bit. Then, the address space A having the next highest access speed after the address space A ₁ is set in the middle bit.
The _second data, and stores each access speed faster address space A ₃ of data next to the least significant bit in the address space A _2.

[0209] Input logical addresses included in the partial space (logical addresses [00 0000] to [3F FFFF]
]), This logical address specifies the data of the most significant bit, and the data of the most significant bit is immediately recognized and output by one determination with the determination voltage of 3.5 V. Become. The input logical address is not included in the partial space, but is included in an address space close to this partial space (logical address [400 0
000]-[7F FFFF]), this logical address specifies the middle-order bit data, and
And the two determinations of 1.5 V or 5.5 V determine the middle bit data and output it.

That is, when reading the data of the most significant bit, the reading speed becomes about three times as compared with the case where each threshold voltage is checked by all the judgment values, and the data of the middle bit is read. In this case, the reading speed is about 1.5 times that in the case where each threshold voltage is checked by using all the judgment voltages. Therefore, by storing the most frequently accessed data in the most significant bit, storing the most frequently accessed data next to the most significant bit in the middle bit, and storing the relatively infrequently accessed data in the least significant bit, respectively. The operator (programmer) looks as if there is a single (or two-stage) high-speed storage device, and can read the multi-value storage EEPROM extremely efficiently.

Although the present invention has been described with reference to an example in which an EEPROM having a floating gate type memory cell performs multi-level storage, a floating gate type memory cell is used as a memory cell for performing multi-level storage. However, the present invention is not limited to this and may be an MNOS type.

[0212] Further, the present invention is not limited to the EEPROM.
A reading method in a case where an EPROM or a PROM performs multi-value storage, and further, for example, changing a threshold by controlling the amount of impurities implanted into a channel region of a field-effect transistor to change a storage state. Obtained mask RO
The present invention can also be applied to a reading method when M is made to perform multi-value storage.

Furthermore, the read method of the present invention can be applied to a DRAM. In this case, it goes without saying that a furnace fresh is performed.

Further, in the first and second embodiments described above,
Although one memory cell has a storage capacity of 2 bits or 3 bits, the present invention can be applied to all cases where one memory cell has a storage capacity of four values (2 bits) or more. In particular, the larger the storage capacity, the more effective.

In the first and second embodiments described above,
A method for detecting whether or not a current flows between a drain and a source of a memory cell by applying a predetermined determination voltage to a control gate of a memory cell in which a threshold voltage of each value is set after determining an address Although described, the data may be determined by comparing the output voltage from the memory cell with a predetermined determination voltage. This method will be described with reference to the circuit diagram of FIG.

The determination circuit of FIG. 7 is provided between the cell array 1 and the multiplexer 4 of FIG. The threshold voltage Vth1 corresponding to the lower bit set in the memory cell 1a of the cell array 1 is determined by the inverter 40 and the transistor 4
Sense amplifier 4 via an output buffer comprising
3 inverting input terminal. The judgment voltage V47 set in the transistor 47 is supplied to the non-inverting input terminal of the sense amplifier 43 by the inverter 46 and the transistors 44 and 45.
Via an output buffer consisting of

When the threshold voltage Vth1 is smaller than the judgment voltage V47, the output of the sense amplifier 43 becomes High, so that the lower bit D0 stored in the memory cell 1a is set to "
1 ". The output of the sense amplifier 43 is High.
Therefore, while the transistor 52 is turned on, the transistor 54 is turned off by the inverter 53. Therefore, the determination voltage V52 set for the transistor 52 is supplied to the non-inverting input terminal of the sense amplifier 48 via the output buffer including the inverter 51 and the transistors 49 and 50. Then, the threshold voltage Vth2 corresponding to the upper bit set in the memory cell 1a is applied to the inverting input terminal of the sense amplifier 48 via the output buffer.

When the threshold voltage Vth2 is smaller than the judgment voltage V52, the output of the sense amplifier 48 becomes High, so that the upper bit D1 stored in the memory cell 1a becomes "1".
On the other hand, when the threshold voltage Vth2 is higher than the determination voltage V52, the output of the sense amplifier 48 is L
Therefore, the upper bit D1 stored in the memory cell 1a is determined to be "0".

Next, the threshold voltage Vth1 becomes equal to the judgment voltage V4.
7, the output of the sense amplifier 43 becomes Low, and the lower bit D0 stored in the memory cell 1a is output.
Is determined to be “0”. When the output of the sense amplifier 43 is Lo
Since it is w, the transistor 52 is turned off while the transistor 54 is turned on by the inverter 53. Therefore, the determination voltage V54 set in the transistor 54 is supplied to the non-inverting input terminal of the sense amplifier 48 via the output buffer. Then, the threshold voltage Vth2 corresponding to the upper bit set in the memory cell 1a is applied to the inverting input terminal of the sense amplifier 48 via the output buffer.

When the threshold voltage Vth2 is smaller than the determination voltage V54, the output of the sense amplifier 48 becomes High, so that the upper bit D1 stored in the memory cell 1a is set to "
On the other hand, when the threshold voltage Vth2 is higher than the determination voltage V54, the output of the sense amplifier 48 is L
Therefore, the upper bit D1 stored in the memory cell 1a is determined to be "0".

In this way, 2-bit (quaternary) data (00, 01, 10, 11) is determined. This method can be applied to multi-valued memory cells having four or more values by increasing the number of sense amplifiers and determination voltage supply circuits according to the number of bits.

Note that, in order to realize various functions so as to realize the functions of the above-described embodiments, an apparatus connected to the various devices or a computer in a system is required to realize the functions of the above-described embodiments. The present invention also includes a program that is implemented by supplying the program code of the software described above and operating the various devices according to a program stored in a computer (CPU or MPU) of the system or apparatus.

In this case, the program code of the software implements the functions of the above-described embodiment, and the program code itself and means for supplying the program code to the computer are provided.
For example, a storage medium 31 storing such a program code
Constitute the present invention.

The storage medium 31 is stored in the storage / reproduction device 30 connected to the signal control circuit 6 via the input / output I / F 8.
The program code stored there is read out,
The computer constituting the signal control circuit 6 is operated.
The storage medium 31 for storing the program code
For example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, magnetic tape, nonvolatile memory card, ROM, or the like can be used.

[0225]

As described above, according to the present invention, even if multi-valued information stored in one memory cell is lost, error correction can be performed efficiently.

Further, according to another feature of the present invention, it is possible to read out frequently accessed data at high speed in accordance with an input logical address, thereby greatly reducing the access time at the time of reading. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of a floating gate type memory cell of an EEPROM according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating a first embodiment of a writing method according to the present invention.

FIG. 4 is a schematic diagram illustrating a second embodiment of the writing method of the present invention.

FIG. 5 is a schematic diagram for explaining a modification of the second embodiment of the writing method of the present invention.

FIG. 6 is a schematic diagram illustrating a third embodiment of the writing method according to the present invention.

FIG. 7 is a schematic diagram illustrating a modification of the third embodiment of the writing method of the present invention.

FIG. 8 is a flowchart of a reading method according to a first embodiment of the reading method of the present invention.

9 is a block diagram illustrating a method for determining a threshold voltage in the flowchart of FIG.

FIG. 10 is a flowchart of a reading method according to a second embodiment of the reading method of the present invention.

FIG. 11 is a block diagram illustrating another method for determining a threshold voltage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Decoder 3 Voltage generation and voltage control circuit 4 Multiplexer 5 Sense amplifier 6 Signal control circuit 6a Information bit distribution means 7 Input I / F 8 Output I / F 9 Conversion circuit 11 Silicon substrate 12 Drain 13 Source 17 Floating gate 19 Control gate 30 Storage / reproduction device 31 Storage medium 40, 46, 51, 53 Inverter 41, 42, 44, 45, 47, 49, 50, 52, 5
4 Transistor 43, 48 Sense amplifier 55 Switch circuit 56 Reference voltage generation circuit

Claims (66)

[Claims] A plurality of multi-level memory cells each holding one of three or more different predetermined storage states; and at least a first memory cell encoded by an arbitrary encoding method.
And a second code, the information bits of the same digit among the plurality of first information bits forming the first code and the plurality of second information bits forming the second code Rearranging means for rearranging the first and second information bits such that the first and second information bits are stored in the corresponding multi-valued memory cell as one set; and a predetermined voltage corresponding to the rearranged information bits. And a voltage application means for receiving the address information and applying the predetermined voltage to the multi-valued memory cell corresponding to the address information. 2. The multi-valued memory according to claim 1, wherein said rearranging means controls the number of bits stored in each of said multi-valued memory cells according to an error correction capability of said encoding method. Semiconductor storage device. 3. The reordering means, wherein when the number of bits stored in one of the plurality of multi-level memory cells is m,
3. The multi-level memory according to claim 1, wherein m codes of code length n are rearranged as respective rows of an m.times.n array so that m information bits are stored in said one multi-level memory cell. Value semiconductor storage device. 4. The multi-level memory cell according to claim 1, wherein said multi-level memory cell is a nonvolatile semiconductor memory.
13. The multi-valued semiconductor memory device according to item 1. 5. A method for writing information bits to a multi-level semiconductor memory device comprising a plurality of multi-level memory cells each holding one of three or more different predetermined storage states. At least the first encoded by any encoding method
And a second code, the information bits of the same digit among the plurality of first information bits forming the first code and the plurality of second information bits forming the second code A first step of rearranging the first and second information bits so that the information bits are stored as a set in the corresponding multi-valued memory cell; A writing method, comprising: a second step of generating a predetermined voltage; and a third step of receiving address information and applying the predetermined voltage to the multi-level memory cell corresponding to the address information. 6. A program for writing information bits to a multilevel semiconductor memory device having a plurality of multilevel memory cells each holding one of three or more different predetermined storage states by a computer. A stored storage medium, comprising at least a first encoded by an arbitrary encoding method.
And the second code, the information bit of the same digit among the plurality of first information bits forming the first code and the plurality of second information bits forming the second code A storage medium storing a program for rearranging the first and second information bits such that the first and second information bits are stored in one of the plurality of multi-valued memory cells as one set. 7. A predetermined voltage corresponding to the rearranged first and second information bits is generated, the address information is received, and the predetermined voltage is applied to the multi-level memory cell corresponding to the address information. The storage medium according to claim 6, wherein a program for performing the operation is stored. 8. A conversion means which receives a logical address and converts the physical address into a physical address; and n (n ≧ 2) components (X ₁ , X ₂ ) arranged corresponding to a physical address space including the physical address. ,…,
X _n ), a plurality of multi-valued memory cells that hold a 2 ⁿ -valued storage state represented by X _n ), and a determination unit that determines whether a logical address space including the logical address matches the physical address space. if the logical address space is determined to match said physical address space, the plurality specifying means for specifying the component X ₁ of the uppermost once the predetermined determination value, the component X ₁ identified Output means for outputting from the multi-valued memory cell corresponding to the physical address among the multi-valued memory cells. 9. Each of the multi-valued memory cells includes at least one transistor, the specifying means includes first means for generating a voltage corresponding to the determination value, and an address signal given the physical address. A second means for outputting the voltage; a third means for applying the voltage to the multi-level memory cell corresponding to the physical address in response to the address signal; and a source-drain between the transistor to which the voltage is applied. And a fourth means for determining whether or not a current flows through the _first means, and a fifth means for specifying the highest-order component X1 based on a result of the determination in the fourth means. 9. The multilevel semiconductor memory device according to item 8. 10. The comparator according to claim 1, wherein one of the input terminals is connected to an output portion of each of the multi-valued memory cells, and a comparator is supplied with a voltage corresponding to the uppermost component X _1. It is connected to the other input terminal of the vessel, and a voltage supply circuit for supplying a voltage corresponding to the predetermined determination value to the input terminal of the other, the said uppermost by the determination result of the comparator component X ₁
The multilevel semiconductor memory device according to claim 8, wherein 11. When it is determined that the logical address space does not coincide with the physical address space, the specifying means sets the component (X ₁ , X ₂ ,..., X _n ) to a predetermined maximum n
9. The multi-valued semiconductor memory device according to claim 8, wherein the identification is performed at a maximum of n times by the plurality of different judgment values. 12. Each of the multi-level memory cells has at least one
A first means for generating n voltages corresponding to the n determination values, a second means for receiving the physical address and outputting an address signal, Third means for applying the voltage to the multi-valued memory cell corresponding to the physical address in response to the address signal; and n kinds of the maximum until a current flows between the source and the drain of the transistor to which the voltage is applied. A fourth means for applying a voltage to the gate of the transistor in a predetermined order; and detecting the current to detect the components (X ₁ , X ₂ ,
, X _n ), and a fifth means for specifying X _n ). The multi-value semiconductor memory device according to claim 11, further comprising: 13. The identification means, wherein one input terminal is connected to an output portion of each of the multi-valued memory cells, and a voltage corresponding to each of the components (X ₁ , X ₂ ,..., X _n ) is supplied. And a voltage supply circuit connected to the other input terminal of the comparator and supplying a voltage corresponding to the maximum n determination values to the other input terminal. According to the result, the component (X
12. The multi-value semiconductor memory device according to claim 11, wherein ( ₁ , X ₂ ,..., X _n ) are specified. 14. A plurality of storage units which are arranged corresponding to a physical address space and hold a storage state of 2 ⁿ values represented by _n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ) A first step of converting a logical address into a physical address included in the physical address space, wherein the logical address space including the logical address is the same as the physical address space. a second step of determining whether or not matching, if the logical address space is determined to match said physical address space, specifying once the components X ₁ the uppermost by a predetermined judgment value a third step, and characterized in that it comprises a fourth step of outputting the components X ₁ identified from the multilevel memory cell corresponding to the physical address of the plurality of multilevel memory cells Read how. 15. In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,...,
The method according to claim 14, further comprising a fifth step of specifying X _n ) at a maximum of n times by a predetermined maximum of n different determination values. 16. A storage state of 2 ⁿ values arranged corresponding to a physical address space and represented by n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ), A method of reading said components from a plurality of multi-level memory cells each comprising at least one transistor, comprising: a first step of translating a logical address to a physical address included in said physical address space; A second step of determining whether a logical address space matches the physical address space; and determining that the logical address space matches the physical address space, a predetermined determination voltage is applied to the gate of the transistor. To the source of the transistor.
Multi corresponding a third step of identifying the components X ₁ the uppermost by whether current flows between the drain, the components X ₁ identified in the physical address of the plurality of multilevel memory cells Reading from the value memory cell. 17. In the second step, if it is determined that the logical address space does not match the physical address space, after the second step, n different determination voltages are applied to the gate of the transistor. Is applied in a predetermined order up to n times until a current flows between the source and the drain of the transistor to specify the component (X ₁ , X ₂ ,..., X _n ). 17. The reading method according to claim 16, wherein: 18. A storage state of 2 ⁿ values arranged corresponding to a physical address space and represented by n (n ≧ 2) components (X ₁ , X ₂ ,..., X _n ), A method of reading said components from a plurality of multi-level memory cells each comprising at least one transistor, comprising: a first step of translating a logical address to a physical address included in said physical address space; A second step of determining whether a logical address space coincides with the physical address space; and, if it is determined that the logical address space coincides with the physical address space, corresponding to the component X ₁ at the highest level compares the voltage with a predetermined determination voltage, the comparison result by the third step of identifying the components X _1, wherein the said component X ₁ identified among the plurality of multilevel memory cells A fourth step of outputting from the multi-valued memory cell corresponding to the physical address. 19. In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,.
X _n ) and the components (X ₁ , X ₂ ,..., X
compares the voltage corresponding to each of the components of _n), the comparison result by the component _{(X 1, X 2, ...} , claim, characterized in X _n) further comprises a fifth step of identifying 18 Reading method described in 1. 20. A computer which is arranged corresponding to a physical address space and has n (n ≧ 2) components (X
_1, X _2, ..., a storage medium storing a program for the X _n) a plurality of multilevel memory cells for holding a storage state of the 2 ⁿ value represented by reading out the components, the logical address A first step of translating to a physical address included in the physical address space; a second step of determining whether a logical address space including the logical address matches the physical address space; If but it is determined that matches the physical address space, a third step of identifying at once the components X ₁ the uppermost by a predetermined judgment value, the component X ₁ identified the plurality of multi A fourth step of outputting from a multi-valued memory cell corresponding to the physical address among the valued memory cells. 21. In the second step, when it is determined that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,.
21. The storage medium according to claim 20, wherein a program further comprising a fifth step of specifying X _n ) at a maximum of n times by a predetermined maximum of n different determination values is stored. 22. A computer which is arranged in correspondence with a physical address space and has n (n ≧ 2) components (X
_1, X _2, ..., holds the storage state of the 2 ⁿ value represented by X _n), each program for reading the component from the plurality of multilevel memory cells comprises at least one transistor is stored A storage medium, comprising: a first step of converting a logical address into a physical address included in the physical address space; and a step of determining whether a logical address space including the logical address matches the physical address space. And if a determination is made that the logical address space matches the physical address space, a predetermined determination voltage is applied to the gate of the transistor,
Multi corresponding a third step of identifying the components X ₁ the uppermost by whether current flows between the drain, the components X ₁ identified in the physical address of the plurality of multilevel memory cells A program having a fourth step of outputting from a value memory cell. 23. When it is determined in the second step that the logical address space does not match the physical address space, after the second step, n different determination voltages are applied to the gate of the transistor. Are applied in a predetermined order at a maximum of n times until a current flows between the source and the drain of the transistor to specify the components (X ₁ , X ₂ ,..., X _n ). 23. The storage medium according to claim 22, wherein the storage medium is stored. 24. A computer which is arranged corresponding to a physical address space and has n (n ≧ 2) components (X
_1, X _2, ..., holds the storage state of the 2 ⁿ value represented by X _n), each program for reading the component from the plurality of multilevel memory cells comprises at least one transistor is stored A storage medium, comprising: a first step of converting a logical address into a physical address included in the physical address space; and a step of determining whether a logical address space including the logical address matches the physical address space. Step 2, and when it is determined that the logical address space coincides with the physical address space, a voltage corresponding to the highest-order component X ₁ is compared with a predetermined determination voltage. exits from the third step and the multilevel memory cell corresponding to the physical address of the component X ₁ identified the plurality of multilevel memory cells to identify the ₁ Storage medium in which a program and a fourth step of is characterized in that it is stored. 25. If it is determined in the second step that the logical address space does not match the physical address space, after the second step, the components (X ₁ , X ₂ ,...
X _n ) and the components (X ₁ , X ₂ ,..., X
_n ) is compared with a voltage corresponding to each component, and a program further including a fifth step of specifying the component (X ₁ , X ₂ ,..., X _n ) based on the comparison result is stored. 25. The storage medium according to claim 24, wherein: 26. A multi-valued semiconductor memory device comprising a plurality of multi-valued memory cells, wherein each of said multi-valued memory cells holds one of three or more different predetermined storage states. A multi-level semiconductor memory device comprising information bit dispersing means for distributing and storing each bit constituting one code encoded by the conversion method in the plurality of multi-level memory cells. 27. The information bit dispersing means controls the number of bits in the same code stored in one multi-level memory cell according to the error correction capability of the one code. 2. The multi-value semiconductor memory device according to claim 1. 28. The multi-level memory cell according to claim 28, wherein the information bit dispersing unit arranges the codes distributed and stored in the plurality of multi-level memory cells, as m rows having a code length of n as m × n arrays. 28. The multi-level semiconductor according to claim 27, wherein when the number of bits stored in the multi-level memory is m, m pieces of information arranged in each column of the array are stored in one of the multi-level memories. Storage device. 29. The multi-level semiconductor memory device according to claim 26, wherein said multi-level memory cell is a nonvolatile semiconductor memory. 30. A storage medium storing a program for causing a computer to function as the information bit dispersing means according to claim 26. 31. A method of writing a code string coded by an arbitrary coding method into a multi-level semiconductor memory device having a plurality of multi-level memory cells holding three or more storage states, A method of writing a multi-level semiconductor memory device, wherein each bit constituting one code encoded by the arbitrary encoding method is dispersed and stored in a plurality of multi-level memory cells. 32. A storage medium in which the writing method for a multi-level semiconductor storage device according to claim 31 is stored so as to be readable by a computer. 33. An input unit for inputting a logical address, a conversion unit for calculating a physical address from the logical address, a control gate and a charge storage layer, wherein the input unit is arranged corresponding to the physical address. Selecting a multi-valued memory cell, each of which holds a storage state of three or more values represented by components of two or more dimensions, and the multi-valued memory cell corresponding to the physical address, and inputting the data to the input means Control means for specifying a component to be output from the components stored in the multi-valued memory cell selected according to the logical address; data of the component of the multi-valued memory cell specified by the control means Output means for outputting the data of at least one of the components, wherein there is a determination value for specifying data of at least one of the components in one determination, and When the logical address is included in a partial space corresponding one-to-one with the address space spanned by the physical address, the control means determines the data of the component of the multi-level memory cell designated by the control means. A multivalued semiconductor memory device characterized by specifying a value and outputting the data from the output means. 34. The multi-valued memory cell has n dimensions (n ≧ n).
Component of _{2) (X 1, X 2} , ..., 2 n represented by X _n)
Holding the stored state values, along with the determination value that identifies the data of at least the X ₁ component in the determination of one is present, the data of the logical address included in the partial space is stored in the X ₁ component cage, when the logical address included in the partial space is input to said input means, out of the storage state of the corresponding multi-level memory cell, the X ₁ components identified by the determination value by the control means 34. The multi-value semiconductor memory device according to claim 33, wherein said data is output from said output means. 35. X _2, ..., with each judgment value identifying the data of X _n component is present, the address space A ₂ in proximity to the address space A ₁ is the partial space, ..., A _n
, _Xn components are sequentially stored in the X ₂ ,..., X _n components in the order of proximity to the address space A ₁ according to the address space of the logical address input to the input means. The control means is X _k (where k = 1,
35. The multilevel semiconductor memory device according to claim 34, wherein the component (2,..., N) is specified by k determinations based on the respective determination values, and the data of the X _k component is output from the output unit. . 36. The multi-value semiconductor memory device according to claim 33, wherein said charge storage layer is a floating gate. 37. A reading method of a multi-level semiconductor memory device having a multi-level memory cell including a control gate and a charge storage layer and arranged corresponding to a physical address calculated from an input logical address, The multi-valued memory cell holds a storage state of three or more values each represented by a component of two or more dimensions, and has a determination value for specifying data of at least one of the components. When the logical address inputted to the input means is included in a partial space corresponding to the address space spanned by the physical address, the control gate of the multi-valued memory cell selected by the physical address is transmitted to the control gate. A voltage of a judgment value is applied, and whether or not a current flows between the source / drain of the multi-level memory cell depends on whether the component of the multi-level memory cell is Method of reading multi-level semiconductor memory device and outputs to identify the over data. 38. The multi-valued memory cell has n dimensions (n
≧ 2) represented by components (X ₁ , X ₂ ,..., X _n )
storage state of ⁿ values are held, along with the determination value that identifies the data of at least the X ₁ component is present, the data of the logical address included in the partial space is stored in the X ₁ component, When the logical address included in the subspace is input to the input means, the X specified by the value in the storage state of the corresponding multi-level memory cell
38. The method according to claim 37, wherein _one component data is output from the output unit. 39. X _2, ..., with each judgment value identifying the data of X _n component is present, the address space A ₂ in proximity to the address space A ₁ is the partial space, ..., A _n
, _Xn components are sequentially stored in the X ₂ ,..., X _n components in the order of proximity to the address space A ₁ according to the address space of the logical address input to the input means. 39. The data according to claim 38, wherein data of an X _k (where k = 1, 2,..., N) component is specified by k determinations based on the respective determination values, and the X _k component is output. A reading method of a multilevel semiconductor memory device. 40. A storage medium storing a program for causing a computer to execute the procedure of the reading method according to any one of claims 37 to 39. 41. A plurality of multi-valued memory cells each holding one of three or more different predetermined storage states, and storing first storage information by at least two digits by an arbitrary encoding method. First encoding means for converting the first code value into the first code value having the above number of digits, and converting the second storage information into a second code value having at least two or more digits by an arbitrary encoding method. Second encoding means for converting, and code value information of the same digit of the first and second code values is set to 1
A multi-level semiconductor memory device, comprising: as a set, rearrangement means for creating two or more sets so as to be stored in the corresponding multi-level memory cells. 42. The multi-value semiconductor memory device according to claim 41, wherein said first and second code values have the same number of digits. 43. An encoding method according to claim 41, wherein said arbitrary encoding method is an encoding method based on a binary system.
3. The multilevel semiconductor memory device according to 2. 44. The multi-valued memory cell has a control gate and a floating gate.
4. The multi-valued semiconductor memory device according to any one of 3. 45. The multi-valued memory cell according to claim 41, wherein the multi-valued memory cell is at least one of an MNOS, a mask ROM, an EEPROM, an EPROM, a PROM, and a flash nonvolatile memory. 2. The multi-value semiconductor memory device according to claim 1. 46. The apparatus according to claim 41, further comprising a correcting unit configured to detect and correct an error occurring in the first and second storage information from the first and second code values.
The multi-value semiconductor memory device according to any one of the above items. 47. A plurality of multi-valued memory cells each holding one of three or more different predetermined storage states, and input storage information is converted into at least two digits by an arbitrary encoding method. Encoding means for converting to a code value having the above number of digits, the code value obtained by the encoding means is divided by an arbitrary number of digits, to create at least two encoded information blocks, A multi-level semiconductor memory device comprising: a divided storage unit for storing, as a set, the same digit of encoded information of each encoded information block in the multi-level memory cell. 48. A reading means for reading out the coded information stored in each of the multi-valued memory cells, correcting a code string composed of the coded information in accordance with an error correction capability of the coding method, and outputting the corrected code string. 48. The multi-valued semiconductor memory device according to claim 47, comprising: 49. The multi-level semiconductor according to claim 48, wherein said read-out means reads out bit information of at least a predetermined position from each of said multi-level memory cells, creates and outputs said code string. Storage device. 50. The multi-valued memory cell is capable of holding one of four different predetermined storage states, and the divided storage means stores the code value by the number of digits. 50. The multi-level memory cell according to claim 49, wherein the multi-level memory cell is divided into two coded information blocks having the same value, and two sets of coded information of the same digit of each coded information block are stored as one set. Multi-value semiconductor memory device. 51. The multi-valued semiconductor memory according to claim 50, wherein said read means outputs each of said two encoded information blocks as information bits obtained by adding redundant bits to information bits. apparatus. 52. The multi-valued memory cell is capable of holding one of eight different predetermined storage states, and the divided storage means stores the code value by the number of digits. 50. The multi-valued memory cell according to claim 49, wherein the encoded information block is divided into three encoded information blocks having the same value, and three encoded information items of the same digit of each encoded information block are stored as a set in the multi-valued memory cell. Multi-value semiconductor memory device. 53. The multi-valued semiconductor memory according to claim 52, wherein said reading means outputs each of the three encoded information blocks as information bits obtained by adding redundant bits to information bits. apparatus. 54. The reading means outputs each of the information blocks formed by combining one of the encoded information blocks and two of the encoded information blocks as redundant information bits added to information bits. 53. The multi-value semiconductor memory device according to claim 52, wherein: 55. The multi-valued memory cell is capable of holding one of 16 different predetermined storage states, and the divided storage means stores the code value by the number of digits. 50. The multi-level memory cell according to claim 49, wherein the encoded information blocks are divided into four encoded information blocks having the same value, and four encoded information items of the same digit of each encoded information block are stored as a set in the multi-level memory cell. Multi-value semiconductor memory device. 56. The multi-level semiconductor memory according to claim 55, wherein said read means outputs each of said four encoded information blocks as information bits obtained by adding redundant bits to information bits. apparatus. 57. The reading means, wherein each of the information blocks formed by combining the two coded information blocks is output as information bits to which redundant bits are added. 56. A multi-valued semiconductor memory device according to item 55. 58. The multi-valued memory cell has a control gate and a floating gate.
8. The multi-valued semiconductor memory device according to any one of items 7 to 7. 59. The multi-valued memory cell according to claim 47, wherein the multi-valued memory cell is at least one of an MNOS, a mask ROM, an EEPROM, an EPROM, a PROM, and a flash nonvolatile memory. 2. The multi-value semiconductor memory device according to claim 1. 60. The redundant bit is generated corresponding to each of the two encoded information blocks based on the two encoded information blocks, and the redundant bit corresponding to the information bit of each encoded information block is generated. 52. The multi-level semiconductor memory device according to claim 51, wherein the number of redundant bits is a number of redundant bits that is equal to the number of bits of the coded sequence. 61. The redundant bit is generated corresponding to each of the three encoded information blocks based on the three encoded information blocks, and the redundant bit corresponding to the information bit of each encoded information block is generated. 54. The multi-level semiconductor memory device according to claim 53, wherein the total number of redundant bits is a redundant bit that is equal to the number of bits of the coded sequence. 62. A first redundant bit corresponding to each of the three coded information blocks is generated by Hamming coding based on the three coded information blocks based on the three coded information blocks. A code string is generated by adding the first redundant bits corresponding to each of the coded information blocks, and exclusive OR of all the bits included in each of the code strings is calculated, and a code string corresponding to each of the code strings is calculated. 54. The redundant bits according to claim 53, wherein two redundant bits are generated, and the sum of the bits of each code string and the corresponding second redundant bits is the number of bits of the code string. The multivalued semiconductor memory device according to the above. 63. The redundant bits correspond to each information block formed by combining the one encoded information block and the two encoded information blocks based on the three encoded information blocks. The sum of the generated redundant bits corresponding to the information bits of the one encoded information block and each of the divided blocks when the information block formed by combining the two encoded information blocks is divided. 54. The multi-level semiconductor memory device according to claim 53, wherein the information bits and the sum of the corresponding redundant bits are redundant bits that are the number of bits of the coded sequence. 64. The redundant bit is generated corresponding to each of the four encoded information blocks based on the four encoded information blocks, and the redundant bit corresponding to the information bit of each encoded information block is generated. 57. The multi-level semiconductor memory device according to claim 56, wherein the total number of redundant bits is a redundant bit whose number is equal to the number of bits of said coded sequence. 65. A first redundant bit corresponding to each of the four encoded information blocks is generated by Hamming encoding based on the four encoded information blocks, based on the four encoded information blocks. A code string is generated by adding the first redundant bits corresponding to each of the coded information blocks, and exclusive OR of all the bits included in each of the code strings is calculated, and a code string corresponding to each of the code strings is calculated. 57. The method according to claim 56, wherein two redundant bits are generated, and the sum of the bits of each code string and the corresponding second redundant bits is the number of bits of the code string. The multivalued semiconductor memory device according to the above. 66. The redundant bits are generated based on the four encoded information blocks in correspondence with each of the information blocks obtained by combining the two encoded information blocks, and Are redundant bits such that when each of the information blocks obtained by combining is divided into two, the sum of the information bits and the corresponding redundant bits of each of the divided blocks becomes the number of bits of the coded sequence. 58. The multi-valued semiconductor memory device according to claim 57, wherein: