KR20090048142A - Ecc processing unit of non volatile memory device - Google Patents

Ecc processing unit of non volatile memory device Download PDF

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Publication number
KR20090048142A
KR20090048142A KR1020070114373A KR20070114373A KR20090048142A KR 20090048142 A KR20090048142 A KR 20090048142A KR 1020070114373 A KR1020070114373 A KR 1020070114373A KR 20070114373 A KR20070114373 A KR 20070114373A KR 20090048142 A KR20090048142 A KR 20090048142A
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South Korea
Prior art keywords
ecc
data
transmission data
logical page
algorithm
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KR1020070114373A
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Korean (ko)
Inventor
김유성
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주식회사 하이닉스반도체
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Priority to KR1020070114373A priority Critical patent/KR20090048142A/en
Publication of KR20090048142A publication Critical patent/KR20090048142A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

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  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The ECC processing unit of the nonvolatile memory device of the present invention selects a different ECC (Error Correcting Code) algorithm according to the type of logical page to which the transmission data is to be programmed, and encodes the transmission data, and the read transmission data is programmed. And selecting an ECC algorithm according to the type of logical page to decode the transmission data.

ECC, Logical Page

Description

ECC processing unit of nonvolatile memory device

The present invention relates to an ECC processing unit used in a nonvolatile memory device, an ECC encoding method and a decoding method using the same.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

In the program and read operation of the nonvolatile memory device, an error correcting code (ECC) function is used to correct an error that may occur during data storage or reading.

As the ECC algorithm, a hamming code system capable of error correction of 1 bit per page data, a BCH code system capable of error correction of several bits, and the like are used.

In performing the ECC algorithm, a method of adding k spare data in addition to n data to be transmitted is used. When the BCH code method is used, the size of the spare data is allocated about 1 to 5%.

The spare data requires an addition of a spare cell to the basic memory cell, resulting in an increase in chip size.

Recently, non-volatile memory devices have widely used a multi-level cell program (MLC) method for programming a plurality of logical pages in one physical page. In the case of a multi-level cell program, since the distribution of threshold voltages is different for each logical page, the probability of an error is also different.

However, the same ECC processing is performed irrespective of the error occurrence probability of each logical page, resulting in a limitation in bandwidth or inferior data reliability.

In order to solve the above problems, an object of the present invention is to provide an ECC processing unit of a nonvolatile memory device capable of selectively controlling the ECC processing algorithm according to the probability of error occurrence for each logical page.

Another object of the present invention is to provide an ECC encoding method and an ECC decoding method of a nonvolatile memory device using the ECC processor.

The ECC processing unit of the nonvolatile memory device of the present invention for achieving the above object is an ECC encoder for encoding the transmission data by selecting a different error correction code (ECC) algorithm according to the type of logical page to be transmitted data; And an ECC decoder which selects a different ECC algorithm according to the type of logical page in which the read transmission data has been programmed and decodes the transmission data.

In addition, the ECC encoding method of the nonvolatile memory device of the present invention comprises the steps of receiving a transmission data to be programmed into a memory cell, determining a logical page to program the transmission data, and a single read voltage of the transmission data Encoding with a first ECC algorithm when programming to an applied first logical page, and ECC data larger than the first ECC algorithm when programming the transmission data to a second logical page to which two or more read voltages are applied. And encoding with the outputting second ECC algorithm.

In addition, the ECC decoding method of the nonvolatile memory device of the present invention comprises the steps of receiving the transmission data programmed in the memory cell and the ECC data output and stored when encoding the transmission data, and determining the logical page in which the transmission data is programmed Decoding the transmission data if the transmission data is programmed in a first logical page to which one read voltage is applied; and decoding the transmission data in the second logic page to which two or more read voltages are applied. And decoding the second ECC algorithm using ECC data larger than the first ECC algorithm.

According to the above-described configuration of the present invention, when encoding data to be programmed into a logical page having a low probability of error occurrence, an ECC algorithm having a relatively lower ECC processing capability may be used to reduce resources used for ECC processing.

In addition, when encoding data to be programmed in a logical page having a high probability of error occurrence, an error occurrence probability may be lowered by using an ECC algorithm having a relatively higher ECC processing capability. The same is true of the decoding process.

As such, by applying an ECC algorithm having different ECC processing capability for each logical page, the ECC processing of the nonvolatile memory device may be optimized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and fully scope the scope of the invention to those skilled in the art. It is provided to inform you. Like numbers refer to like elements in the figures.

1 illustrates a threshold voltage state of each logical page according to a multi-level cell program of a nonvolatile memory device.

In a memory cell of a nonvolatile memory device, cells connected to one word line are defined as pages. When a single level cell program is executed for one physical page, only one logical page is formed. However, in the case of a multi-level cell program, two or more logical pages are formed.

In the case of a 2-bit multi-level cell program, two logical pages are formed. In the case of a 3-bit multi-level cell program, three logical pages are formed. In general, n logical pages are formed in an n-bit multi-level cell program.

At this time, the distribution of threshold voltages of each logical page formed on the same physical page is different as shown.

Since only two cell states exist in the first logical page of FIG. 1 to which one read voltage is applied, a margin for each distribution is sufficient. However, in a state in which an additional program is applied to the first logical page, four cell states exist in a second logical page to which two or more read voltages are applied, and a margin is narrowed compared to the distribution of the first logical page. to be. In the third logic page to which four or more read voltages are applied while additionally programming the second logical page, there are eight cell states in total, and the margin is higher than the distribution of the first and second logical pages. This is a much narrower state.

As such, since the cell distribution state of each page is different, the probability of an error occurring for each page is also different. In other words, if there is a margin in each distribution, the probability of an error occurring in the program / read process is much reduced.

In the present invention, a new ECC processing method is proposed by using the fact that the error occurrence probability of each page in the program / read process is different.

2 is a diagram illustrating a nonvolatile memory device used in the present invention.

The nonvolatile memory device may include a memory cell 210 in which external input data is stored, a controller 220 performing a program / read / erase operation on the memory cell, data input to the memory cell and the memory cell. An ECC processing unit 230 for performing error correction processing on the output data.

The memory cell 210 may include a main memory cell in which external input data is stored, and a spare cell in which various types of operation information of the nonvolatile memory device are stored.

The spare cell area includes an ECC data storage unit 212 that stores the ECC processing result.

The ECC data is data that can be used to determine whether an error occurs during the transmission of the binary data (hereinafter, referred to as 'transmission data') to be transmitted.

For example, when the transmission data includes an odd number of '1', the ECC data is set to '1', and when the transmission data includes an even number of '1', the ECC data is '0'. Assume that it is set to.

Subsequently, specific data in which transmission data and ECC data are combined is received. If the ECC data is '1' and the transmission data includes an odd number of '1', it is considered that there was no error in the data transmission process.

However, in the state where the ECC data is '1', if the transmission data includes an even number '1', it is regarded that there is an error in the data transmission process and requests retransmission of the data.

In this case, retransmission of data may be required according to an ECC processing algorithm, or a process of directly correcting an error may be performed.

In general, error detection by a known parity bit is an algorithm that requires retransmission of data because there is no error correction function, and a processing method using a hamming code can correct errors after error detection. On the other hand, in addition to the Hamming code system capable of error correction of 1 bit per page data, a BCH code system capable of error correction of several bits is also used.

However, as each algorithm has a powerful processing capability, the processing capacity of the processor increases. In other words, the ECC processing method using the parity bit has no error correction function, but the processing capacity is the smallest.

The processing power of each algorithm is mainly represented by the size of ECC data. In other words, the larger the size of the ECC data added to the transmission data, the larger the processing capacity. However, the processing burden becomes larger.

The controller 220 performs a program / erase / read operation on all memory cells. The memory cells that are subjected to the program / erase / read operations are addressed, and the voltage applied to the word line or the like during each operation is controlled.

In addition, the control unit transmits the externally transmitted data to pass through the ECC processing unit 230 and controls the data read out after being programmed in the memory cell to be output to the outside via the ECC processing unit 230.

In addition, a page information signal indicating to which logical page the transmission data will be programmed is transmitted.

The ECC processing unit 230 performs ECC processing on the externally input transmission data and generates ECC data. In addition, the transmission data and the ECC data read from the memory cell are received, the ECC processing is performed on the transmission data, and error correction is performed by comparing with the received ECC data.

To this end, the ECC processing unit 230 compares the ECC encoder 232 for generating ECC data by encoding the transmission data according to a specific ECC algorithm, and compares the ECC data with the transmission data stored in the memory cell and ECC data. An ECC decoder 234 that corrects for the error.

The ECC encoder 232 encodes the transmission data by selecting a different ECC algorithm according to the type of logical page in which the transmission data is to be programmed. As a result of the encoding, ECC data of different sizes are output according to the ECC algorithm used in the encoding process, which is stored in the ECC data storage unit 212 of the memory cell.

The logical page to which the transmission data is to be programmed can be distinguished by the number of read voltages to be applied in the reading process of the corresponding page. As the number of read voltages is larger, an ECC algorithm having a larger ECC data is selected.

In addition, the ECC decoder 234 decodes the transmission data by selecting a different ECC algorithm according to the type of the logical page in which the read transmission data has been programmed. In this case, the type of the page on which the transmission data is programmed may be determined according to the size of the ECC data stored in the ECC data storage unit 212, and an ECC algorithm for decoding the transmission data may be selected based on the size of the page.

As described above, the ECC encoder and the ECC decoder select different ECC algorithms according to types of logical pages to perform ECC processing.

In other words, when the transmission data is to be programmed in the first logical page or read from the first logical page in the multi-level cell program, the first ECC algorithm (1 bit / lower) that the processor is less likely to generate an error is considered to be low. 512B) to process. The first ECC algorithm uses one bit of ECC data in processing page data of 512 bytes.

In addition, when the transmission data is to be programmed in the second logical page or read from the second logical page, the probability of error occurrence is regarded as relatively higher, and a second ECC algorithm having higher processing burden of the processor (2bit / 512B). Select) to process. The second ECC algorithm uses two bits of ECC data in processing page data of 512 bytes.

In addition, when the transmission data is to be programmed in the third logical page or read out from the second logical page, the probability of error occurrence is regarded as relatively higher, and a third ECC algorithm having higher processing burden of the processor (3bit / 512B). Select) to process. The third ECC algorithm uses three bits of ECC data in processing page data of 512 bytes.

In this case, the numerical values representing the processing performance of each algorithm are merely examples for comparing the performance of each algorithm, and the scope of the present invention is not limited to the numerical values. Depending on the designer's intention, the values can be changed sufficiently.

Now, the ECC process according to the present invention will be described in more detail.

3 is a flowchart illustrating an ECC encoding process according to an embodiment of the present invention.

First, transmission data in units of pages to be programmed into a main memory cell is input to the ECC encoder 232 (step 310).

Next, it is determined in which logical page the transmission data is to be stored (step 320).

This may be determined through a page information signal transmitted from the controller 220 or by a flag signal indicating an MLC program step included in a spare cell.

Next, an ECC algorithm corresponding to each of the determined logical pages is selected to perform ECC encoding (step 330).

That is, as mentioned above, when the transmission data is to be programmed in the first logical page in the multi-level cell program, the probability of error occurrence is regarded as low, and the first ECC algorithm (1bit / 512B) having a low processing burden of the processor is selected. To be treated.

When the transmission data is to be programmed in the second logical page, the error occurrence probability is considered to be relatively higher, and the second ECC algorithm (2bit / 512B) having a higher processing burden is selected and processed.

When the transmission data is to be programmed in the third logical page, the error occurrence probability is regarded as relatively higher, and the third ECC algorithm (3bit / 512B) having a higher processing burden is selected and processed.

If more logical pages are set, the appropriate ECC algorithm is selected and processed.

Next, transmission data and ECC data are output after the ECC encoding process (step 340).

When the first ECC algorithm is selected, one bit of first ECC data will be output. When the second ECC algorithm is selected, two bits of second ECC data will be output. When the third ECC algorithm is selected, 3 will be output. The third ECC data of the bit will be output.

In other words, the ECC data that is output depends on which ECC algorithm is selected.

The processed transmission data will then be programmed into a specific page of the main memory cell, and the ECC data is stored in the ECC data storage 212 to be associated with the specific page.

4 is a flowchart illustrating an ECC decoding process according to an embodiment of the present invention.

First, the transmission data programmed in the main memory cell and the ECC data stored in the ECC data storage unit 212 are received (step 410).

Next, it is determined in what logical page the transmission data is stored (step 320).

This may be determined through a page information signal transmitted from the controller 220 or by a flag signal indicating an MLC program step included in a spare cell.

Alternatively, it may be determined through the ECC data. That is, since the capacity of the ECC data output for each logical page is different as a result of the encoding process, the logical page can be determined according to the capacity of the ECC data.

For example, when the input ECC data is the first ECC data of 1 bit, it is determined to be the first logical page, and when the second ECC data of the 2 bits is determined to be the second logical page.

Next, an ECC algorithm corresponding to each of the determined logical pages is selected to perform ECC decoding (step 430).

That is, when the transmission data is data programmed in the first logical page, it is determined that the error occurrence probability is low, and the first ECC algorithm (1bit / 512B) having a low processing burden of the processor is selected and processed.

When the transmission data is data programmed in the second logical page, the error occurrence probability is considered to be relatively higher, and the second ECC algorithm (2bit / 512B) having a higher processing burden is selected and processed.

When the transmission data is data programmed in the second logical page, the probability of error occurrence is regarded as relatively higher, and a third ECC algorithm (3bit / 512B) having a higher processing burden is selected and processed.

If more logical pages are set, the appropriate ECC algorithm is selected and processed.

On the other hand, if it is determined that no error has occurred as a result of the ECC processing, the transmission data is output as it is. However, if an error occurs, the error of the transmission data is corrected using ECC data.

Next, transmission data is output after the ECC decoding process (step 440).

As such, different ECC processing algorithms may be used depending on the probability of an error occurring during ECC encoding or decoding.

1 illustrates a threshold voltage state of each logical page according to a multi-level cell program of a nonvolatile memory device.

2 is a diagram illustrating a nonvolatile memory device used in the present invention.

3 is a flowchart illustrating an ECC encoding process according to an embodiment of the present invention.

4 is a flowchart illustrating an ECC decoding process according to an embodiment of the present invention.

Description of the main parts of the drawing

200: nonvolatile memory device

210: memory cell

212: ECC data storage

220: control unit

230: ECC processing unit

232: ECC encoder

234: ECC decoder

Claims (11)

An ECC encoder for encoding the transmission data by selecting different error correction code (ECC) algorithms according to the type of the logical page to which the transmission data is to be programmed; And an ECC decoder for selecting the different ECC algorithm according to the type of the logical page to which the read transmission data has been programmed and decoding the transmission data. The ECC processor of claim 1, wherein the ECC encoder outputs ECC data having different sizes according to an ECC algorithm and stores the ECC data in an ECC data storage unit of a memory cell. The ECC processor of claim 1, wherein the ECC encoder selects an ECC algorithm having larger ECC data as the number of read voltages applied to each logical page increases. The ECC encoder of claim 1, wherein the ECC encoder encodes transmission data to be programmed in a first logical page to which one read voltage is applied, using a first ECC algorithm. And a second ECC algorithm for outputting ECC data larger than the first ECC algorithm, to be transmitted to a second logical page to which two or more read voltages are applied. The ECC processing unit of claim 1, wherein the ECC decoder selects an ECC algorithm to decode the transmission data according to the size of ECC data stored in an ECC data storage unit of a memory cell. The method of claim 1, wherein the ECC decoder decodes transmission data programmed in a first logical page to which one read voltage is applied, using a first ECC algorithm. ECC processing unit of the nonvolatile memory device, characterized in that the transmission data programmed in the second logical page to which two or more read voltages are applied to the second ECC algorithm using ECC data larger than the first ECC algorithm. Receiving transmission data to be programmed into a memory cell; Determining a logical page to program the transmission data; Encoding the transmission data with a first ECC algorithm when programming the first logical page to which one read voltage is applied; And encoding the transmission data with a second ECC algorithm that outputs larger ECC data than the first ECC algorithm when programming the second logical page to which two or more read voltages are applied. ECC encoding method of the device. 8. The method of claim 7, further comprising encoding the transmission data with a third ECC algorithm that outputs larger ECC data than the second ECC algorithm when programming the third logical page to which more than four read voltages are applied. ECC encoding method of a nonvolatile memory device, characterized in that. Receiving transmission data programmed in a memory cell and ECC data output and stored when encoding the transmission data; Determining a logical page in which the transmission data is programmed; Decoding the transmission data with a first ECC algorithm when the transmission data is programmed in a first logical page to which one read voltage is applied; Non-volatile memory, characterized in that the transmission data is decoded with a second ECC algorithm using larger ECC data than the first ECC algorithm when programmed in a second logical page to which at least two read voltages are applied. ECC decoding method of the device. The ECC decoding method of claim 9, wherein the determining of the logical page comprises determining a logical page in which the transmission data is programmed according to the size of the received ECC data. . 10. The method of claim 9, comprising decoding with a third ECC algorithm using greater ECC data than the second ECC algorithm when the transmission data is programmed in a third logical page to which more than four read voltages are applied. An ECC decoding method of a nonvolatile memory device.
KR1020070114373A 2007-11-09 2007-11-09 Ecc processing unit of non volatile memory device KR20090048142A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8615702B2 (en) 2010-12-09 2013-12-24 Samsung Electronics Co., Ltd. Method and apparatus for correcting errors in memory device
US11249848B2 (en) 2020-06-18 2022-02-15 Samsung Electronics Co., Ltd. Error check code (ECC) decoder and memory system including ECC decoder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8615702B2 (en) 2010-12-09 2013-12-24 Samsung Electronics Co., Ltd. Method and apparatus for correcting errors in memory device
US11249848B2 (en) 2020-06-18 2022-02-15 Samsung Electronics Co., Ltd. Error check code (ECC) decoder and memory system including ECC decoder

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