JP4206745B2 - Multilayer chip inductor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer chip inductor in which a coil is provided in a laminated body of magnetic layers so that the axial direction of the coil faces the surface direction of the magnetic layer.
[0002]
[Prior art]
Conventionally, as one form of the multilayer chip inductor, the ceramic magnetic layer is laminated, and the lamination is performed so that the axis of the coil faces the surface direction of the magnetic layer, that is, the direction perpendicular to the lamination direction. The structure which formed the coil inside the body is taken (for example, patent document 1). Examples are shown in FIGS. 12A and 12B. Here, (A) is an external perspective view, and (B) is a top view thereof. However, the outermost protective layer is omitted.
[0003]
In FIG. 12, reference numeral 30 denotes a conductor path extending in the stacking direction (longitudinal direction) of the multilayer body, and two rows of a plurality of substantially parallel conductor paths 30 that conduct the magnetic layers in the stacking direction are provided. A plurality of strip-like wiring patterns 20 are formed on the upper and lower layers of the magnetic layer. The plurality of wiring patterns 20 connect between two rows of conductor paths to form a coil as a whole. These conductor paths 30 are configured by filling a through hole opened in each magnetic layer with a conductive paste and conducting in the stacking direction.
[0004]
The wiring pattern 20 is formed by screen printing a conductive paste on the magnetic layer.
[0005]
Normally, a coil having a closed magnetic circuit structure as shown in FIG. 12 has a DC superposition characteristic that the inductance is reduced when a DC current is passed. Therefore, in such a coil design, the inductance is reduced when a DC current is applied. The structure is determined so as not to decrease as much as possible.
[0006]
In general, the DC superposition characteristics are related to the shortest magnetic path length (coil length), and the DC superposition characteristics become better as the coil length is increased. Therefore, in order to increase the coil length, the coil pitch is increased from the state shown in FIGS. 12A and 12B as shown in FIGS. 12C and 12D to increase the coil length. ing. Here, (C) is a perspective view of the multilayer chip inductor, and (D) is a top view thereof. FIG. 11 is an exploded perspective view of the multilayer chip inductor shown in FIGS. Here, wiring patterns 20a and 20b are formed on 10a and 10b. 10c is a magnetic material layer laminated between the two magnetic material layers 10a and 10b, and constitutes a conductor path 30 that conducts in the lamination direction. Reference numeral 11 denotes a protective layer.
[0007]
In general, in order to obtain various inductance constants in an inductor component, the number of turns, the magnetic permeability of the magnetic material, the winding diameter of the coil, etc. are determined, but the method of changing the number of turns is the simplest and most common. The multilayer chip inductor having the structure shown in FIG. 12 is also designed to obtain a desired inductance value by changing the number of turns. For example, the relationship between the number of turns in a 4.5 × 3.2 mm size multilayer chip inductor and the inductance obtained thereby is as shown in Table 1 below.
[0008]
[Table 1]
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Number of turns 8.5 12.5 17.5 25.5
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Inductance 10μH 22μH 47μH 100μH
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[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-102218
[Problems to be solved by the invention]
However, in a multilayer chip inductor having a conventional structure, the coil length is restricted by the longitudinal dimension of the multilayer body, that is, the longitudinal dimension of the chip, even when the DC superimposition characteristics are optimized. Therefore, there is a limit to the optimization of the DC superimposition characteristics.
[0011]
In addition, when changing the number of turns in order to obtain various inductance values, it is necessary to change the number of through holes opened in each magnetic layer. Such through-hole processing includes a method of punching with a mold and a method of burning out by irradiating with a laser beam. However, in order to improve the processing efficiency, these are generally performed collectively. Therefore, a die for batch processing, a laser irradiation device, etc. are prepared for exclusive use. Therefore, in order to make a series of various inductance values by changing the number of through holes, it has been necessary to prepare a dedicated die and a laser irradiation device for each inductance value. Or, it was necessary to process by a method with extremely low processing efficiency such as processing through holes one by one, ignoring mass productivity.
[0012]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and easily manufacture a multilayer chip inductor having a desired number of turns, and to obtain a good DC superposition characteristic even when the number of turns is small. Is to provide.
[0013]
[Means for Solving the Problems]
In the present invention, a plurality of magnetic layers are laminated, and two rows of substantially parallel conductor paths that conduct between the magnetic layers in the laminating direction are provided, and the first row of conductor tracks and the second row of conductor tracks are provided. In a multilayer chip inductor in which a plurality of wiring patterns arranged in a predetermined magnetic layer are made conductive and a coil is formed by the conductor path and the wiring pattern,
Between adjacent conductive paths between the plurality of conductive paths forming the column or outside the column by the conductor path, to form a magnetic adjustment unit,
Before Ki磁 adjustment unit is characterized by comprising the said consisting cavity through hole through a plurality of the magnetic layers in the stacking direction, or filled with non-magnetic material within the through-hole structure.
Thus, even if the coil pitch is widened by forming the magnetic adjustment portion, the increase of the leakage magnetic flux is suppressed, and the deterioration of the DC superimposition characteristic is suppressed.
[0014]
Moreover, the magnetic adjustment portion, more and child a plurality of magnetic layers to the cavity through-hole passing through in the stacking direction, or filled with the said through hole further non-magnetic material structure, as the conductor path Simultaneously with the step of forming the through-hole, a non-magnetic material or a low permeability magnetic adjustment portion can be easily formed between adjacent conductor paths of the plurality of conductor paths.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
The multilayer chip inductor according to the first embodiment will be described with reference to FIGS.
FIG. 1 is a perspective view and a top view showing the structure of the main part of the multilayer chip inductor. 2 is an exploded perspective view of the whole, and FIG. 3 is an external perspective view of the multilayer chip inductor. In FIG. 2, reference numerals 10a and 10b denote magnetic layers formed with wiring patterns 20a and 20b and dummy patterns 21a and 21b, respectively. Reference numeral 10c denotes a plurality of magnetic layers laminated between the two magnetic layers 10a-10b. Reference numeral 11 denotes an outermost protective layer.
[0019]
Band-shaped wiring patterns 20a and 20b are arranged on the magnetic layers 10a and 10b. Further, dummy patterns 21a and 21b are arranged between adjacent wiring patterns of these wiring patterns 20a and 20b.
[0020]
In the magnetic layers 10a and 10b in which these wiring patterns are formed and the magnetic layer 10c stacked between them, a plurality of substantially parallel conductor paths 30 and dummy holes 31 that conduct the layers in the stacking direction are alternately arranged. Two rows are provided. Eight conductor paths and eight dummy holes are provided in both the first row (for example, the front row in the drawing) and the second row (for example, the rear row in the drawing). Further, the wiring patterns 20a and 20b are electrically connected between the first row of conductor paths 30 and the second row of conductor paths 30. With this structure, the conductor path 30 and the wiring patterns 20a and 20b constitute a coil as a whole. As will be described later, since the conductivity is also imparted to the dummy hole, the dummy hole is also a “conductor path”. However, in this example, both ends of the dummy patterns 21 a and 21 b do not reach the dummy hole 31.
[0021]
The magnetic layer 10a is formed with a lead pattern 22 that is electrically connected to the wiring patterns at both ends of the plurality of wiring patterns 20a arranged.
[0022]
A manufacturing method of the multilayer chip inductor shown in FIGS. 1 to 3 is as follows.
First, a plurality of through holes are linearly arranged in two rows at an equal pitch on the ferrite green sheet for the magnetic layer 10c. Here, 16 through-holes with a diameter of 80 μm are processed in a row at a pitch of 200 μm. All of these through holes are filled with a conductive paste by a method such as screen printing. The printed pattern at this time is 100 μm wider than the diameter of the through hole. A predetermined number of magnetic material layers 10c filled with the conductive paste are stacked and pressed. As a result, the conductor path 30 and the dummy hole 31 are formed which conduct the magnetic layers between the through holes in the laminating direction.
[0023]
Next, the wiring pattern 20 and the dummy pattern 21 are formed by screen-printing a conductive paste on the ferrite green sheets for the magnetic layers 10a and 10b.
[0024]
After that, the magnetic layers 10a and 10b and the protective layer 11 are further stacked on the upper and lower sides of the laminate made of the magnetic layer 10c, and the layers are pressure bonded by pressing. Thereafter, it is fired in the same manner as the conventional processing method for multilayer chip inductors to form a ferrite sintered body. Further, a conductive paste serving as an external electrode is applied and baked on both ends of the sintered body, followed by plating to obtain a finished product.
[0025]
In the example shown in FIGS. 1 to 3, an eight-turn coil is configured. However, even if the number of turns of the coil changes, the formation position and the number of through holes do not change. For example, when the number of turns is 16, all the patterns provided on the magnetic layers 10a and 10b act as wiring patterns, and all the through holes are used as the conductor paths 30. As the number of turns is less than 16 turns, the number used as dummy patterns among the patterns formed in the magnetic layers 10a and 10b is increased, and the number of through-holes acting as dummy holes is increased. In the case of 8 turns, as shown in FIGS. 1 and 2, the number of dummy patterns is equal to the number of wiring patterns, and the number of dummy holes is equal to the number of conductor paths. When the number of turns is less than 8, the dummy patterns are larger than the wiring patterns, and the dummy holes are larger than the conductor paths. However, in any case, the outermost through hole of the through holes arranged in two rows is used for the conductor path 30 at the start and end of the coil.
[0026]
Thus, even coils having different numbers of turns can be manufactured using ferrite green sheets prepared using the same mold or the same laser irradiation apparatus.
[0027]
In this example, the conductive paste is filled in the dummy holes. However, nothing may be filled in the dummy holes, and a simple cavity may be used. Alternatively, for example, an organic material such as carbon may be filled in the through hole and burned out during firing to form a cavity. Further, a non-magnetic material such as glass may be filled in the through hole serving as the magnetic adjustment portion. Further, a magnetic material having a magnetic permeability lower than that of the magnetic layer may be filled.
[0028]
In this example, the conductive paste is printed as a dummy pattern. However, by opening a portion of the ferrite green sheet between the wiring patterns and laminating a plurality of ferrite green sheets, the hollow portion due to the continuous opening is formed into the magnetic adjustment portion. You may provide as. Further, a dummy pattern made of a magnetic material having a magnetic permeability lower than that of the magnetic layer may be printed.
[0029]
In this example, both ends of the dummy patterns 21a and 21b do not reach the dummy holes 31, but both the dummy patterns 21a and 21b and the dummy holes 31 have conductivity, and the dummy holes 31 and the first row in the first row The dummy patterns 21a and 21b may be electrically connected to the two rows of dummy holes 31.
[0030]
In the example shown in FIG. 2, the dummy patterns 21a and 21b are formed only on the same layer as the magnetic layers 10a and 10b on which the wiring patterns 20a and 20b are formed. However, the dummy pattern 21 is formed at the same position over a plurality of layers. May be. For example, the dummy pattern 21 may be formed in the intermediate magnetic layer 10c.
[0031]
Next, the effect of improving the DC superposition characteristics by the dummy pattern and the dummy hole will be described.
Here, the result of trial manufacture with a size of 3.2 × 1.6 mm and a height of 1.6 mm is shown. As described above, a ferrite green sheet obtained by processing 16 through-holes of 100 μm diameter lands at 200 μm pitch for two rows was used to produce a coil wired to have 8 turns. In this case, the gap between the through holes is 100 μm. Moreover, the thing which made the gap of the adjacent wiring pattern 300 micrometers and 100 micrometers was created. For comparison, a multilayer chip inductor having a conventional structure in which neither a dummy pattern nor a dummy hole is provided was also prepared.
[0032]
FIG. 5 shows the result of the direct current value when the inductance value L is reduced by 10% by superimposing the obtained inductance value and the direct current. 4A is the upper left column (conventional structure) of FIG. 5A, FIG. 4B is the upper right column, FIG. 4C is the lower left column, and FIG. 4D is the lower right column (first embodiment). The corresponding pattern of each of the structures is shown. FIG. 5B shows the result of the direct current value when the inductance value L is reduced by 10% due to the superposition of the direct current and the inductance value when the number of turns is changed in the conventional structure.
[0033]
Thus, in this embodiment, compared with the conventional structure, the DC energization current value when the inductance value is reduced by 10% is increased by about 80% (60 mA → 110 mA). Although the inductance value when the direct current is not superimposed tends to decrease, as shown in FIG. 5B, the direct current superimposition characteristic is also compared with the conventional 7-turn structure having the equivalent inductance value. Is improved by about 50% (75 mA → 110 mA).
[0034]
FIG. 6 schematically shows how the inductance value L decreases due to DC current superposition. According to the present invention, the characteristic as conventionally indicated by U can be improved like P.
In this way, the DC superposition characteristic is sufficiently improved by setting the distance between the conductor path and the dummy hole adjacent thereto or the distance between the wiring pattern and the dummy pattern adjacent thereto to 100 μm or less.
[0035]
Next, the structure of the main part of the multilayer chip inductor according to the second embodiment is shown in FIG. In FIG. 7, reference numerals 10a and 10b denote magnetic layers formed with wiring patterns 20a and 20b. The other magnetic layer 10c and protective layer 11 are the same as those shown in FIG. The formation positional relationship between the conductor path 30 and the dummy hole 31 is the same as that shown in FIG. 2, but in this example, the line widths of the wiring patterns 20a and 20b are increased to narrow the gap between the wiring patterns. With this structure, the gap between adjacent wiring patterns and the gap between adjacent conductor paths are reduced, the leakage magnetic flux is reduced, and the DC superposition characteristics can be improved.
[0036]
In the example of FIG. 7, the number of turns is eight. However, the position of the through hole used as the conductor path 30 is determined, and the patterns of the wiring patterns 20a and 20b connecting the two rows of conductor paths are determined to a maximum of 16 turns. You can increase the number of turns until the turn. However, when the number of turns is 16, it is the same as the conventional structure. Conversely, the number of turns can be reduced by reducing the number of wiring patterns 20a and 20b and further increasing the line width.
[0037]
Next, a multilayer chip inductor according to a third embodiment will be described with reference to FIGS. 8 is an exploded perspective view of the multilayer chip inductor, and FIG. 9 is an external perspective view thereof. In FIG. 8, 10a and 10b are magnetic layers formed with wiring patterns 20a and 20b and dummy patterns 21a and 21b, respectively. Reference numeral 10c denotes a plurality of magnetic layers laminated between the two magnetic layers 10a-10b. Reference numeral 11 denotes an outermost protective layer. Reference numeral 10d denotes a magnetic layer that is laminated at a substantially central position among the plurality of magnetic layers, and forms a lead pattern 22. In the first embodiment, a dummy pattern as a magnetic adjustment unit is provided between a plurality of wiring patterns. In the example shown in FIG. 8, dummy patterns 21a and 21b are arranged outside the arrayed portion of the wiring patterns 20a and 20b. Is forming. In addition, dummy holes 31 are arranged outside the row of conductor paths 30. For the multilayer chip inductor having such a structure, a magnetic layer similar to that shown in FIG. 2 is used. That is, through-holes with a diameter of 80 μm are formed in two rows with 16 rows at a pitch of 200 μm. In the example shown in FIG. 2, the plurality of through holes are used as conductor paths at intervals of 2 pitches to form an 8-turn coil. However, in the example of FIG. Is used as the conductor path 30 to form an 8-turn coil. The strip-like wiring patterns 20a and 20b are also formed accordingly. The dummy holes 31 are also provided in the middle magnetic layers 10c and 10d sandwiched between the magnetic layers 10a and 10b on which the wiring patterns 20a and 20b are formed, together with the conductor paths. With such a structure, the magnetic adjustment portions exist at both ends in the axial direction of the coil by the wiring patterns 20a and 20b and the conductor path 30. With this structure, even when the coil length is short, the magnetic adjustment unit suppresses the passage of magnetic flux generated by the coil, so that the magnetic flux draws a large loop passing near both ends of the multilayer chip inductor having a large magnetic path cross-sectional area. . Therefore, the shortest magnetic path length can be increased and the DC superposition characteristics can be improved. In addition, multilayer chip inductors having different numbers of turns can be manufactured using the same mold, the same laser irradiation apparatus, or the like.
[0038]
Further, in this embodiment, since the entire line length of the coil is shortened, the DC resistance can be reduced. In addition, since the pattern of the wiring portion can be simplified, it is possible to prevent the occurrence of problems such as erroneous wiring due to ferrite green sheet misalignment or printing misalignment, or shorting between patterns.
[0039]
Next, a multilayer chip inductor according to a fourth embodiment will be described with reference to FIG.
In this example, 16 through 2 through holes are all used as conductor paths, and line patterns 20a, 20a ′, 20b, and 20b ′ are formed in the magnetic layers 10a and 10b, respectively. Among these wiring patterns, the wiring patterns 20a and 20b are arranged so as to connect the conductor paths 30 between the pitches that are skipped at intervals of two pitches. Further, the wiring patterns 20a 'and 20b' are arranged so as to connect between the conductor paths 30 'between the pitches that are skipped at intervals of two pitches. Then, both ends of the two coils are commonly connected by the lead pattern 22. As a result, a structure in which two coils of eight turns are arranged in a double spiral shape and connected in parallel is obtained.
[0040]
With such a structure, the conductor path 30 'existing between adjacent conductor paths of the plurality of conductor paths 30 acts as a magnetic adjustment unit, and the wiring pattern 20a existing between the plurality of wiring patterns 20a, 20b. ', 20b' acts as a magnetic adjustment part. Therefore, the direct current superimposition characteristic is improved. In addition, the DC resistance can be reduced by parallel winding of the coils.
[0041]
In this example, by connecting two 8-turn coils in parallel, the series resistance was halved without lowering the inductance value. However, it is possible to freely select whether or not to use the magnetic adjustment unit as a coil for obtaining the inductance value. If the number of turns is 8 turns or less, a dummy pattern and a dummy hole as a magnetic adjustment part may be provided in addition to the wiring pattern and the conductor path acting as a parallel winding coil.
[0042]
Moreover, you may change the number of turns of the whole coil by providing both a parallel winding coil and a single winding coil. This also allows fine adjustment of the inductance value.
[0043]
Note that the number of coils to be wound in parallel is not limited to two. If the number of turns is small, a plurality of conductor paths and wiring patterns are formed between adjacent conductor paths and between adjacent wiring patterns. Then, three or more coils may be wound in parallel.
[0044]
In this way, the DC superposition characteristics can be improved, and coils with different numbers of turns can be manufactured using the same mold and the same laser irradiation apparatus.
[0045]
【The invention's effect】
According to the present invention, between adjacent conductor paths of a plurality of conductor paths forming a row, outside of the row by the conductor paths, between adjacent wiring patterns of the plurality of wiring patterns, outside of the arrangement portion by the wiring patterns, By forming a magnetic adjustment portion made of a nonmagnetic material or a member having a lower permeability than that of the magnetic material layer in any of the above, the increase in leakage flux is suppressed even when the coil pitch is widened, and the DC superimposition characteristics are Deterioration is suppressed.
[0046]
In addition, the magnetic adjustment part is a hollow through hole that passes through a plurality of magnetic layers in the stacking direction, or the inside of the through hole is further filled with a non-magnetic material, so that the magnetic adjustment is performed simultaneously with the formation of the conductor path. The portion can be formed, and the manufacturing cost does not increase.
[Brief description of the drawings]
1 is a perspective view and a plan view of a main part of the multilayer chip inductor according to the first embodiment. FIG. 2 is an exploded perspective view of the multilayer chip inductor. FIG. 3 is an external perspective view of the multilayer chip inductor. [Figure 5] Diagram showing the structure of several multilayer chip inductors for examining the effect of dummy patterns and dummy holes [Fig. 5] Diagram showing inductance values and DC superposition characteristics of four types of multilayer chip inductors [Figure 6] DC superposition characteristics FIG. 7 is a perspective view of the main part of the multilayer chip inductor according to the second embodiment. FIG. 8 is an exploded perspective view of the main part of the multilayer chip inductor according to the third embodiment. 9 is an external perspective view of the multilayer chip inductor. FIG. 10 is an exploded perspective view of the main part of the multilayer chip inductor according to the fourth embodiment. FIG. 11 is an exploded perspective view of a conventional multilayer chip inductor. Perspective view and a plan view of a main part showing a visual view [12] of a conventional laminated chip inductor structure EXPLANATION OF REFERENCE NUMERALS
10-magnetic material layer 11-protective layer 20-wiring pattern 21-dummy pattern 22-drawer pattern 30-conductor path 31-dummy hole

Claims (1)

A plurality of magnetic layers are laminated, and two rows of substantially parallel conductor paths that conduct the magnetic layers in the laminating direction are provided, and a predetermined gap is provided between the first row of conductor paths and the second row of conductor paths. In a multilayer chip inductor in which a plurality of wiring patterns arranged in a magnetic layer are made conductive, and a coil is formed by the conductor path and the wiring pattern,
Between adjacent conductive paths between the plurality of conductive paths forming the column or outside the column by the conductor path, to form a magnetic adjustment unit,
Before Ki磁 adjustment unit, multilayer chip inductor, characterized in that comprising the consisting cavity through hole through a plurality of the magnetic layers in the stacking direction, or filled with non-magnetic material within the through-hole structure.

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