JP4206727B2 - Self-scanning light emitting device array - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a self-scanning light-emitting element array, and more particularly to a structure in which a connection portion between a power supply line and a semiconductor element is not easily opened, or a structure in which operation reliability is not lowered even when the connection portion is opened. .
[0002]
[Prior art]
A light emitting element array in which a large number of light emitting elements are integrated on the same substrate is used as an optical writing head such as an optical printer head in combination with a driving IC. The inventors have paid attention to a three-terminal light-emitting thyristor having a PNPN structure as a constituent element of the light-emitting element array, and have already filed a patent application (see Patent Documents 1, 2, 3, and 4) that self-scanning of the light-emitting point can be realized. It has been shown that it is easy to mount as an optical printer head, that the light emitting element pitch can be made fine, and that a compact self-scanning light emitting element array can be produced.
[0003]
Furthermore, the present inventors have proposed a self-scanning light-emitting element array having a structure separated from a light-emitting element (light-emitting thyristor) array, which is a light-emitting part, using a switch element (light-emitting thyristor) array as a shift part (Patent Document 5). reference).
[0004]
[Patent Document 1]
JP-A-1-238996
[Patent Document 2]
Japanese Patent Laid-Open No. 2-14584
[Patent Document 3]
Japanese Patent Laid-Open No. 2-92650 [0007]
[Patent Document 4]
JP-A-2-92651
[Patent Document 5]
FIG. 1 shows an equivalent circuit diagram of a diode-coupled self-scanning light emitting element array chip 10 of a type in which a shift portion and a light emitting portion are separated. This self-scanning light emitting element array includes switch elements T ₁ , T ₂ , T ₃ ... And light emitting elements L ₁ , L ₂ , L ₃ . A three-terminal light-emitting thyristor is used for both the switch element and the light-emitting element. The configuration of the shift unit uses a diode connection. That is, the gate electrodes of the switch elements are coupled by the diodes D ₁ , D ₂ ,. _VGA is a power supply (usually −5 V), and is connected to the gate electrode of each switch element from the power supply line 13 via the load resistance R _L. The gate electrode of the switch element is also connected to the gate electrode of the light emitting element. The gate electrode of the switch element T ₁ is connected to the start pulse terminal φ _S. The cathode electrodes of the switch elements are connected to clock pulse terminals φ1 and φ2 via transfer clock pulse lines 11 and 12 alternately. The resistors R1 and R2 are current limiting resistors inserted in the lines 11 and 12, respectively. A cathode electrode of the light emitting element passes through the light-emitting signal line 14, is connected to the light emitting signal terminal phi _I. The resistor R _I is a current limiting resistor inserted in the line 14.
[0009]
The switch element array and light emitting element array are formed by forming a PNPN structure on a p-type semiconductor substrate, separating elements, providing electrodes, then covering the whole with an insulating film, opening a contact hole, and _VGA wiring , .phi.1 wiring, .phi.2 wiring, etc. phi _I wiring formed of Al wiring, are made by forming a protective film on the whole. The diode is formed using the uppermost n-type semiconductor layer of the PNPN structure and the next p-type semiconductor layer, and the load resistance is formed using the next p-type semiconductor layer of the PNPN structure.
[0010]
FIG. 2 is a plan view of the self-scanning light emitting element array of FIG. 1 formed on a chip. FIG. 3 is a cross-sectional view of a portion indicated by a dotted line 17 in FIG. 2, but shows a cross-section of a wiring portion on the p-type semiconductor layer 18 in order to simplify the drawing.
[0011]
In FIG. 2, L is a light emitting element, T is a switch element, D is a diode, C is a contact hole, R _L is a load resistance, 15 is a load resistance R _L , the diode D and the gate electrode of the switch element T are connected. Al wirings 20a and 20b indicate Au-based electrodes. 11, 12, 13, 14, .phi.1 line, .phi.2 line, V _GA line shown in FIG. 1, a phi _I lines. In FIG. 3, 22 is a SiO ₂ insulating film, and 24 is a SiO ₂ protective film.
[0012]
[Problems to be solved by the invention]
As can be seen from FIG. 3, the Al wiring of the _VGA line 13 made of Al wiring is connected to the Au-based electrode 20 a on the p-type semiconductor layer 18 through the contact C opened in the insulating film 22. In general, it is known that Al and Au form an alloy represented by a purple plug, and the resistance value of these alloys increases from several times to ten times the resistance value of Al and Au alone. It becomes an inhibition. Further, these alloys become brittle because the ductility of Al and Au is lost. There are Al and Au joints other than the _VGA line, but the _VGA line is a power supply line and is different from the other connection parts in that a voltage is constantly applied.
[0013]
In addition, the generation of batteries due to the joining of dissimilar metals, the promotion of electrochemical action such as electromigration by constant voltage application, the mechanical brittleness of joints, the action of moisture and salt in natural environment, etc., between Al and Au Bonding is poor. When the defective connection part is observed with an electron beam microscope, it is recognized that the contact hole part rises and a hole is formed inside the joint and is open. Such an open state reduces operational reliability.
[0014]
The present invention has been made paying attention to such a conventional problem, and the object thereof is a structure in which a connection portion for connecting a _VGA line and a semiconductor element is not easily opened in a self-scanning light emitting element array. Is to provide.
[0015]
Another object is to provide a structure capable of continuing the operation of the self-scanning light-emitting element array even when the connection portion connecting the _VGA line and the semiconductor element is opened.
[0016]
[Means for Solving the Problems]
The present invention provides a light-emitting element array in which a plurality of PNPN-structure three-terminal light-emitting thyristors are arranged one-dimensionally, and a power supply to each thyristor via a semiconductor resistance element formed by the PNPN-structure semiconductor layer. In a self-scanning light-emitting element array including at least a power supply line made of Al wiring to be supplied, an Au-based electrode provided on each of the semiconductor resistance elements and connected to the power supply line has a contact prevention film for Al on the surface. It is formed.
[0017]
The present invention is based on the following idea.
[0018]
It is not alloyed only by contacting Al and Au. Sputtering is used as a method for depositing Al on Au, and alloying proceeds due to the energy of the Al element when Al is deposited on the Au electrode. Therefore, in order to prevent alloying, a contact prevention film may be provided so that the Al element does not touch the Au electrode. Ni, Cr, Cu, etc. are effective for the contact prevention film, and the film thickness should just be 15 nm or more sufficient so that the Al element which has energy may not penetrate.
[0019]
Further, in the present invention, in the patterning process of the semiconductor resistance element that forms the load resistance of the self-scanning light emitting element array, the _VGA line side of the semiconductor resistance element is combined without element isolation.
[0020]
A typical structure is a light-emitting element array in which a plurality of PNPN-structure three-terminal light-emitting thyristors are arranged one-dimensionally, and a semiconductor resistance element formed by the PNPN-structure semiconductor layer in each thyristor, respectively. In a self-scanning light emitting element array having at least a power supply line made of Al wiring for supplying power, N (N is an integer of 2 or more) adjacent semiconductor resistance elements are coupled on the power supply line side. It is characterized by being.
[0021]
By adopting such a structure, even when one connection portion connecting the _VGA line and the semiconductor element is corroded and opened, the normal connection portion passes through the combined semiconductor resistance element. Then, voltage application to the semiconductor element in the open state can be continued.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
[0023]
[First embodiment]
The electrodes on the p-type semiconductor layer of the conventional self-scanning light-emitting element array were prepared by depositing AuSb at 75 nm and then AuZn at 150 nm and lifting off. The electrode structure is a two-layer structure of AuSb / AuZn from the semiconductor layer side. As a deposition source, AuSb (Sb content is 0.5 to 5% by weight), AuZn (Zn content is 1 to 10% by weight), and 10 ¹⁷ cm ⁻³ low-concentration p-type AlGaAs layers are used. 18, a good ohmic junction was obtained. In order to obtain a good ohmic junction with the low-concentration p-type AlGaAs layer of the 10 ¹⁷ cm ⁻³ level, it was necessary to anneal at 400 ° C. for about 10 minutes in a nitrogen atmosphere after electrode formation.
[0024]
In this embodiment, as shown in FIG. 4, during the conventional electrode deposition, a Ni layer 26 is additionally formed as a contact prevention film with Al by 200 nm, and the electrode structure is made of AuSb / AuZn / Ni 3 from the semiconductor layer side. A layer structure was adopted. In order to obtain a good ohmic junction with the low-concentration p-type AlGaAs layer 18 on the order of 10 ¹⁷ cm ⁻³ , it is necessary to anneal at 400 ° C. for about 10 minutes in a nitrogen atmosphere after electrode formation. The Ni layer 26 which is the prevention film diffuses into the AuZn layer, but it has been confirmed that a thickness of at least 200 nm is necessary to leave high concentration Ni on the outermost surface of the electrode.
[0025]
On the other hand, it has been clarified that when the Ni layer 26 is 500 nm or more, diffusion reaches the surface of the AlGaAs layer 18 at the time of annealing, and it reacts excessively with the layer material to deteriorate ohmic characteristics. Therefore, when the Ni layer is used as a contact preventive film with Al, the alloy reaction with Al can be suppressed while maintaining the function as an ohmic electrode in the range of 200 to 500 nm.
[0026]
A self-scanning light-emitting element array was fabricated under the same conditions and the same process as before except for adding the Ni film forming process. The contact hole morphology was clearly smoother than before, and alloying was suppressed. I found that it was achieved.
[0027]
A self-scanning light-emitting element array chip having a conventional structure and a self-scanning light-emitting element array chip according to the present embodiment are packaged in 100 chips, respectively, and the device is exposed to the environment at high temperature and high humidity of 60 ° C. and 90%. A continuous operation test was carried out, and the time Th until half of the operations became defective was investigated. As a result, in the conventional structure, there was a Th = 230 hours in operation failure due to open-circuit failure of the V _GA line, the structure of the present embodiment is Th = 880 hours, the reliability of the operation life was remarkably improved .
[0028]
In the above embodiment, Ni is used as the metal for the contact prevention film. However, in addition to Ni, a material that does not easily react with Au and Al, such as Cr and Cu, can be used as the barrier material.
[0029]
The Ni layer can also be formed by vapor deposition or lift-off immediately before Al sputtering.
[0030]
The Ni layer can also be formed by vapor deposition or sputtering film formation immediately before Al sputtering, and etching and forming a wiring simultaneously with the Al film formed immediately thereafter.
[0031]
[Second embodiment]
Next, an embodiment of a structure capable of continuing the operation of the self-scanning light emitting element array even when the connection portion connecting the _VGA line and the semiconductor element is in an open state will be described.
[0032]
As shown in FIG. 5, a structure in which two adjacent semiconductor resistance elements are coupled without fabricating the semiconductor resistance element R _L on the _VGA line 13 side was fabricated. Such a structure can be easily implemented by changing the patterning of a photomask that forms a p-type AlGaAs layer, which is the next layer of the PNPN structure, as a semiconductor resistance element. That is, the p-type AlGaAs layer forming the semiconductor resistance element and its lower layer are left, and the other portions are etched away to the substrate to form a semiconductor element isolation groove.
[0033]
In this case, on the V _GA line 13 side, the same number of ohmic electrodes 20a as the number of elements were formed by patterning on the p-type semiconductor layer and connected to the V _GA line 13 through the contact hole C. Thus, voltages are applied to the two connected semiconductor resistance elements from the two ohmic electrodes 20a, respectively. Therefore, even if one of these two ohmic electrodes 20a becomes open due to corrosion, for example, and becomes electrically non-conductive, voltage is applied to the two connected semiconductor resistance elements through the other ohmic electrode 20a. Since it can continue, the operation is not impaired.
[0034]
The self-scanning light-emitting element array chip having a conventional structure and the self-scanning light-emitting element array chip according to the present embodiment are packaged 100 chips each, and the device is continuously exposed to the environment at a high temperature and high humidity of 60 ° C. and 90%. An operation test was conducted, and the time Th until half of the operation became defective was investigated. As a result, in the conventional structure, was Th = 230 hours in operation failure due to open-circuit failure of the V _GA line, in the structure according to this embodiment, a Th = 1230 hours, greatly improving the reliability of operating life did.
[0035]
In this embodiment, the semiconductor resistance elements are coupled to two adjacent elements, but a structure in which three or more semiconductor resistance elements are coupled as shown in FIG. 6 may be employed. As the number to be coupled increases, the open-circuit failure becomes stronger, so that the operation reliability of the self-scanning light-emitting element array becomes higher.
[0036]
In this embodiment, the same number of ohmic electrodes 20a as the number of elements are patterned on the _VGA line side. However, the same effect can be obtained by forming more electrodes 20a as shown in FIG. It is done. As the number of electrodes increases, the open-circuit failure becomes stronger, so that the operation reliability of the self-scanning light-emitting element array becomes higher.
[0037]
Further, as shown in FIG. 8, it is also possible to adopt a structure in which an electrode 30 that spans several elements (three elements in the example in the figure) is formed and coupled by a plurality of contact holes C. Furthermore, as shown in FIG. 9, the electrode 30 may be stretched over all elements. By extending the electrodes, it is possible to couple with more contact holes without increasing the resistance, so that it is strong against open failures and at the same time, it is possible to ensure stable operation, etc. The operation reliability of the system becomes high.
[0038]
In this embodiment, as described in the first embodiment, if an electrode is provided with a contact prevention film with Al, the operation reliability of the self-scanning light emitting element array can be further improved.
[0039]
[Third embodiment]
Next, an optical printer head using the self-scanning light emitting element array chip described above and an optical printer using such an optical printer head will be described.
[0040]
FIG. 10 is a perspective view showing the main part of the optical printer head. The optical printer head includes a self-scanning light-emitting element array 134 configured by arranging a plurality of self-scanning light-emitting element array chips 132 in a staggered arrangement on a mounting substrate 130, and a plurality of erecting equal-magnification lenses (rods). Lens) 136 and an erecting equal-magnification lens array 138 configured by arranging the same. The light emitted from the light emitting element array 134 is collected by the lens array 138 and irradiated onto a photosensitive drum (not shown).
[0041]
FIG. 11 shows a configuration of an optical printer including such an optical printer head 140. A photoconductive material (photosensitive member) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 142. This drum rotates at the speed of printing. The surface of the photosensitive drum of the rotating drum is uniformly charged by the charger 144. Then, the optical printer head 140 irradiates the photosensitive member with light of a dot image to be printed, and neutralizes the charging where the light hits. Subsequently, the developing device 148 applies toner to the photoconductor in accordance with the charged state on the photoconductor. Then, the toner is transferred onto the paper 154 sent from the cassette 152 by the transfer device 150. The paper is heated and fixed by the fixing device 146 and sent to the stacker 158. On the other hand, the drum that has been transferred is neutralized by the erasing lamp 160 over the entire surface, and the remaining toner is removed by the cleaner 162.
[0042]
【The invention's effect】
According to the present invention, since the electrode provided with the contact prevention film with Al is used for the connection portion connecting the _VGA line and the semiconductor element, an alloy with Al is not formed, and this is due to the alloy formation. The problem can be solved.
[0043]
In addition, according to the present invention, even when the connection portion for connecting the _VGA line and the semiconductor element is opened, voltage application to the opened element is continued via the connected semiconductor resistance element. As a result, the long-term reliability of the operation of the self-scanning light emitting element array is improved.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a diode-coupled self-scanning light emitting element array chip in which a shift unit and a light emitting unit are separated.
2 is a plan view of the self-scanning light emitting element array of FIG. 1. FIG.
3 is a cross-sectional view of a portion indicated by a dotted line 17 in FIG.
FIG. 4 is a diagram showing an electrode structure of the present invention.
FIG. 5 is a view showing a coupling state of semiconductor resistance elements according to the present invention.
FIG. 6 is a diagram showing another coupling state of the semiconductor resistance element according to the present invention.
FIG. 7 is a diagram showing an arrangement of electrodes in a coupling portion of a semiconductor resistance element.
FIG. 8 is a diagram showing one electrode and an arrangement of contact holes in a coupling portion of a semiconductor resistance element.
FIG. 9 is a view showing still another coupling state of the semiconductor resistance element according to the present invention.
FIG. 10 is a perspective view showing a main part of the optical printer head.
FIG. 11 is a diagram illustrating a configuration of an optical printer including an optical printer head.
[Explanation of symbols]
11, 12 Transfer clock pulse line 13 Power supply line 14 Light emission signal line 15 Al wiring 18 p-type AlGaAs layers 20a, 20b Au-based electrode 22 SiO ₂ insulating film 24 SiO ₂ protective film 26 Ni layer

Claims (8)

A light-emitting element array in which a plurality of PNPN-structure three-terminal light-emitting thyristors are arranged one-dimensionally, and an Al wiring that supplies power to each thyristor via a semiconductor resistance element formed by the PNPN-structure semiconductor layer. In a self-scanning light emitting element array comprising at least a power line comprising:
Au-based electrodes provided on each of the semiconductor resistance elements,
A contact preventive film made of Ni, Cr or Cu, which is provided on the Au-based electrode and prevents direct contact between the Au-based electrode and the power line by being connected to the power line;
Self-scanning light-emitting element array comprising: a. A light-emitting element array in which a plurality of PNPN-structure three-terminal light-emitting thyristors are arranged one-dimensionally, and an Al wiring that supplies power to each thyristor via a semiconductor resistance element formed by the PNPN-structure semiconductor layer. In a self-scanning light emitting element array comprising at least a power line comprising:
The semiconductor resistance elements are coupled on the power supply line side for each of N (N is an integer of 2 or more) adjacent semiconductor resistance elements, and N provided on the coupled portion of the semiconductor resistance elements One or more Au-based electrodes;
A contact preventive film made of Ni, Cr or Cu, which is provided on the Au-based electrode and prevents direct contact between the Au-based electrode and the power line by being connected to the power line;
Self-scanning light-emitting element array comprising: a. A light-emitting element array in which a plurality of PNPN-structure three-terminal light-emitting thyristors are arranged one-dimensionally, and an Al wiring that supplies power to each thyristor via a semiconductor resistance element formed by the PNPN-structure semiconductor layer. In a self-scanning light emitting element array comprising at least a power line comprising:
The semiconductor resistance elements are coupled on the power line side for each of N (N is an integer of 2 or more) adjacent semiconductor resistance elements, and each of the semiconductor resistance elements is provided on the coupled portion of the semiconductor resistance elements. One Au-based electrode;
A contact preventing film made of Ni, Cr or Cu, which is provided on the Au-based electrode and prevents direct contact between the Au-based electrode and the power line by being connected to the power line;
An insulating film provided on the contact prevention film and having two or more contact holes for connection to the power line;
Self-scanning light-emitting element array comprising: a. The self-scanning light-emitting element array according to claim 1, wherein when the contact prevention film is Ni, the thickness of Ni is 200 to 500 nm. 5. The self-scanning light-emitting element array according to claim 1, wherein each of the semiconductor resistance elements is p-type AlGaAs. The impurity concentration of the p-type AlGaAs is 10 ¹⁷ cm ^―3 6. The self-scanning light-emitting element array according to claim 1, wherein the self-scanning light-emitting element array is a table. An optical printer head comprising the self-scanning light emitting element array according to any one of claims 1 to 6 . An optical printer comprising the optical printer head according to claim 7 .

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