JP4192330B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a drive circuit for controlling power on / off of a load and a logic circuit for control operation are formed on a single chip together with a constant voltage power supply circuit for supplying power to them.
[0002]
[Problems to be solved by the invention]
For example, an ECU (Electronic Control Unit) for an automobile is composed of a microcomputer, a drive circuit for driving a load, a logic circuit for controlling the drive circuit and monitoring a load operating state and temperature, a constant voltage power supply circuit, and the like. However, in recent years, in order to reduce the size and weight, a plurality of circuits are formed on the same semiconductor substrate to form a single chip. In this case, generally, a drive IC in which a drive circuit, a logic circuit, a constant voltage power supply circuit, etc. are made into one chip is provided, and a load is driven while data is exchanged between the drive IC and a microcomputer. Configuration is considered.
[0003]
However, in such a configuration, since the power of the logic circuit and the microcomputer is supplied from the constant voltage power circuit in the drive IC, when a failure occurs in the constant voltage power circuit, the logic circuit or The operation of the microcomputer becomes unstable, and there is a possibility that the control operation of the load becomes impossible. This is an unsolved problem.
[0004]
The present invention has been made in view of the above circumstances, and its purpose is to reduce the size and weight by integrating a drive circuit for controlling the operation of a load, a logic circuit for performing the control operation, a constant voltage power supply circuit, and the like into one chip. It is an object of the present invention to provide a semiconductor device that can improve fail-safe performance against a failure of a constant voltage power supply circuit even in the case shown.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the means described in claim 1 can be employed. According to this means, a drive circuit for controlling disconnection of the load, a logic circuit for performing a control operation including control of the drive circuit, and a constant voltage power supply circuit for supplying power to the whole are the same. Since the structure is formed on the semiconductor substrate, the overall size and weight can be reduced. In this case, a fail-safe circuit for forcibly disconnecting the load when the output voltage of the constant voltage power supply circuit rises to the voltage level of the output voltage of the external power supply is provided. Since it is configured to be powered from the power supply, even if the output voltage of the constant voltage power supply circuit becomes abnormal as described above, the load can be forcibly cut off reliably. The fail-safe performance can be improved.
[0006]
According to the means of claim 2, the drive circuit includes a switching element that cuts off the load, that is, the power switching element is also formed on the same semiconductor substrate. The overall size and weight can be further reduced.
[0007]
When the fail-safe circuit is formed in a predetermined element formation region provided in a state of being insulated from other circuit element formation regions on the semiconductor substrate, as in the means of claim 3, The risk of adverse effects due to the state of other circuit elements is reduced with respect to the function of the fail-safe circuit.
[0008]
When the SOI substrate is used and the element formation region for the fail-safe circuit is provided with the trench isolation structure as in the means described in claim 4, the function of the fail-safe circuit is Since the adverse effect caused by the state of the circuit element can be reliably prevented, the fail-safe function can be further enhanced.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
In FIG. 1 showing an electrical configuration, a drive IC 1 as a semiconductor device is for driving an external load 2 through a load connection terminal 1a, and power as a switching element for controlling the disconnection of the load 2 A MOSFET 3 is provided. The MOSFET 3 is an N-channel type, and has a drain connected to the power supply terminal VB and a source connected to the load connection terminal 1a. The power supply terminal VB is supplied with power from an unillustrated external power supply (output voltage is, for example, 12 V).
[0010]
In the drive IC 1, in addition to the MOSFET 3, a charge pump circuit 4 that generates a gate signal for the MOSFET 3 in a state where an ON command is given is provided. The drive circuit 5 referred to in the invention is configured. Incidentally, the power of the charge pump circuit 4 is supplied from the power supply terminal VB.
[0011]
In addition, a monitoring logic 6 (corresponding to a logic circuit in the present invention), a constant voltage power circuit 7 and a fail safe circuit 8 are provided in the drive IC 1.
The monitoring logic 6 is based on a state detection signal from a state detection circuit including a current mirror circuit (not shown) for detecting a load current flowing through the MOSFET 3 and a temperature detection circuit (not shown) for detecting the temperature of the MOSFET 3. A function of monitoring the load current, the temperature of the MOSFET 3 and the like is provided, and a signal indicating the monitoring result is transmitted to the microcomputer 9 outside the drive IC 1. The microcomputer 9 determines a driving method of the load 2 based on a signal from the monitoring logic 6 and a preset program, and transmits a signal for instructing the monitoring logic 6 to turn on / off the MOSFET 3. The monitoring logic 6 generates an on command and an off command for the MOSFET 3 based on a command signal from the microcomputer 8, and on / off control of the MOSFET 3 is performed through the charge pump circuit 4 based on these commands.
[0012]
The constant voltage power supply circuit 7 is supplied with power from an external power supply through a power supply terminal VB, and supplies a constant voltage (5 V) output to internal circuit elements such as the monitoring logic 6 and current mirror circuit and the microcomputer 9. It has a configuration.
[0013]
The fail safe circuit 8 is provided so that power is supplied from an external power source through the power terminal VB, and has the following configuration.
That is, in the fail-safe circuit 8, the voltage detection circuit 10 is obtained by connecting voltage dividing resistors 10a and 10b in series between the output terminal of the constant voltage circuit 7 and the ground terminal, and connecting these resistors 10a and 10b in common. A detection voltage Vd proportional to the output voltage of the constant voltage power supply circuit 7 is generated from the point. The reference voltage generation circuit 11 is formed by connecting voltage dividing resistors 11a and 11b in series between a power supply terminal VB and a ground terminal, and generates a reference voltage Vs of a certain level from a common connection point of the resistors 11a and 11b. The comparator 12 is supplied with power from an external power supply through the power supply terminal VB. The comparator 12 compares the levels of the detection voltage Vd and the reference voltage Vs, and when the relationship Vd> Vs is satisfied, the output signal is changed from the low level. The structure is inverted to high level. The comparator 12 is preferably connected with a feedback resistor to provide hysteresis.
[0014]
In the fail safe circuit 8, the output terminal of the comparator 12 is connected to the base of an NPN transistor 14 via a resistor 13, and a bias resistor 15 is connected between the base and emitter of the transistor 14. . In the transistor 14, the collector is connected to the gate of the MOSFET 3 through the resistor 16, and the emitter is connected to the ground terminal. Therefore, when the transistor 14 is turned on, the MOSFET 3 is forcibly turned off by lowering the gate-source voltage to near the ground potential level.
[0015]
FIG. 2 schematically shows a schematic cross-sectional structure of the drive IC 1. In FIG. 2, the drive IC 1 uses an SOI substrate 17 (corresponding to a semiconductor substrate in the present invention) in which an N-type silicon layer 17c is formed on a P-type base silicon substrate 17a via an insulating separation film 17b. It is a thing. In this case, circuit elements (not shown in FIG. 2) such as the MOSFET 3, the charge pump circuit 4, the monitoring logic 6, the constant voltage power circuit 7, and the fail safe circuit 8 are formed in the silicon layer 17c. The plurality of element formation regions 17d are formed in a state of being electrically insulated from each other by the insulating isolation trench 17e.
[0016]
According to the above configuration, when the constant voltage power supply circuit 7 is functioning normally, the relationship between the detection voltage Vd from the voltage detection circuit 10 and the reference voltage Vs from the reference voltage generation circuit 11 is Vd <Vs. Since it is in the state, the comparator 12 in the fail safe circuit 8 outputs a low level signal. Therefore, in this state, since the transistor 14 remains off, the MOSFET 3 is on / off controlled via the charge pump circuit 4 by a signal from the monitoring logic 6.
[0017]
On the other hand, when a failure occurs in the constant voltage power supply circuit 7 and the output voltage rises to the voltage level of the power supply terminal VB, the relationship between the detection voltage Vd and the reference voltage Vs is reversed to the state of Vd> Vs, and the comparator The output of 12 is inverted to a high level signal. Then, since the MOSFET 3 with the transistor 14 turned on is forcibly turned off, the load 2 is forcibly disconnected unconditionally. When a failure occurs in which the output voltage of the constant voltage power supply circuit 7 is reduced, the output of the on command from the monitoring logic 6 is stopped and the MOSFET 3 is turned off. Therefore, even if a failure occurs in the constant voltage power supply circuit 7 and the operations of the monitoring logic 6 and the microcomputer 9 become unstable, there is no possibility that the control operation (disconnection operation) of the load 2 becomes impossible.
[0018]
According to the embodiment described above, the drive circuit 5 including the MOSFET 3 for controlling the disconnection of the load 2, the monitoring logic 6 for performing the control operation of the drive circuit 5, and the power supply to the whole Since the constant voltage power supply circuit 7 is formed on the same SOI substrate 17 to form a single chip, the overall size and weight can be reduced.
[0019]
In this case, when the output voltage of the constant voltage power circuit 7 becomes abnormal, the load 2 is forcibly cut off by the fail safe circuit 8, but the fail safe circuit 8 is supplied with power from an external power source. Therefore, even if the output voltage of the constant voltage power supply circuit 7 becomes abnormal as described above, the forced power-off operation of the load 2 can be performed reliably, and the failure is prevented. The safe performance can be improved.
[0020]
In addition, the SOI substrate 17 is used as a semiconductor substrate for IC formation, and a plurality of element formation regions 17d that are electrically insulated from each other by the insulating isolation trench 17e are formed on the SOI substrate 17. In addition, since the circuit elements such as the fail safe circuit 8 are formed in the element forming region 17d, there is a possibility that the function of the fail safe circuit 8 may be adversely affected due to the state of other circuit elements. This can be surely prevented, the fail-safe function can be greatly enhanced, and the layout constraints of each circuit element can be reduced.
[0021]
The present invention is not limited to the above-described embodiment, and the following modifications or expansions are possible.
The switching element (MOSFET 3) may be connected to the outside. In this case, the charge pump circuit 4 corresponds to the drive circuit referred to in the present invention.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor substrate.
1 is a drive IC (semiconductor device), 2 is a load, 3 is a MOSFET (switching element), 4 is a charge pump circuit, 5 is a drive circuit, 6 is a monitoring logic (logic circuit), 7 is a constant voltage power supply circuit, 8 Is a fail safe circuit, 9 is a microcomputer, 10 is a voltage detection circuit, 11 is a reference voltage generation circuit, 12 is a comparator, 17 is an SOI substrate (semiconductor substrate), 17d is an element formation region, and 17e is an isolation trench.

Claims (4)

A drive circuit for controlling power on / off of the load, a logic circuit for performing a control operation including control of the drive circuit, and an output lower than an output voltage of the external power supply to an internal circuit element including the logic circuit that is fed from an external power supply In a semiconductor device formed on the same semiconductor substrate with a constant voltage power supply circuit for supplying voltage power,
The provided so as to be powered from an external power supply, fail to forcibly deenergized the load through the drive circuit when the output voltage of the constant voltage power supply circuit rises to the voltage level of the output voltage of the external power supply A semiconductor device including a safe circuit. The drive circuit includes a switching element that cuts off the load, and the fail-safe circuit forces the switching element when an output voltage of the constant voltage power supply circuit becomes an abnormal state. 2. The semiconductor device according to claim 1, wherein the semiconductor device is turned off. 3. The semiconductor device according to claim 1, wherein the fail-safe circuit is formed in a predetermined element formation region provided on the semiconductor substrate in a state of being isolated from other circuit element formation regions. . 4. The semiconductor device according to claim 3, wherein the semiconductor substrate is constituted by an SOI substrate, and an element forming region for the fail-safe circuit is electrically insulated by an insulating isolation trench.

Images