JP4190404B2 - Wiring board with heat sink - Google Patents

Wiring board with heat sink Download PDF

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JP4190404B2
JP4190404B2 JP2003418020A JP2003418020A JP4190404B2 JP 4190404 B2 JP4190404 B2 JP 4190404B2 JP 2003418020 A JP2003418020 A JP 2003418020A JP 2003418020 A JP2003418020 A JP 2003418020A JP 4190404 B2 JP4190404 B2 JP 4190404B2
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wiring board
heat sink
plating
mounting portion
adhesive layer
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JP2005183447A (en
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秀武 片桐
正典 鬼頭
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、放熱板の一方の主面に、配線基板が接着材層を介して接着され、且つ電子部品の搭載部が形成されてなる放熱板付配線基板に関する。   The present invention relates to a wiring board with a heat sink, in which a wiring board is bonded to one main surface of a heat sink via an adhesive layer, and an electronic component mounting portion is formed.

半導体装置において、半導体素子やチップコンデンサ等の電子部品は、電子部品用パッケージに設けられた搭載部に搭載されて実用に供されている。電子部品用パッケージ本体の材料としては、耐熱性、耐久性、熱伝導性等に優れるアルミナ等のセラミックスが適しており、セラミック製の電子部品用パッケージは現在盛んに使用されている。   In semiconductor devices, electronic components such as semiconductor elements and chip capacitors are put into practical use by being mounted on a mounting portion provided in a package for electronic components. As a material for the electronic component package body, ceramics such as alumina having excellent heat resistance, durability, thermal conductivity, and the like are suitable, and ceramic electronic component packages are actively used at present.

このようなセラミック製の電子部品用パッケージは、パッケージサイズを縮小し、搭載ボードへの搭載密度を向上させ、また電気特性を向上させるため、一般に複数枚のグリーンシートを積層および焼成してセラミックスパッケージ本体が製造される。また、パワーモジュールに代表されるような半導体素子からの発熱量が大きなものでは、半導体素子を通常の方法で搭載したのみでは、発熱により半導体装置が正常に作動しなくなる恐れがある。そこで、半導体素子の作動時に発生する熱を大気中に良好に放散させるようにした電子部品用パッケージとして、例えば熱伝導性に優れた金属から成る放熱板を備えた放熱板付配線基板が知られている。   In order to reduce the package size, improve the mounting density on the mounting board, and improve the electrical characteristics, such ceramic electronic component packages are generally laminated and fired by stacking and firing a plurality of green sheets. The body is manufactured. In addition, when the amount of heat generated from a semiconductor element as represented by a power module is large, the semiconductor device may not operate normally due to heat generation only by mounting the semiconductor element by a normal method. Therefore, as a package for an electronic component in which heat generated during operation of a semiconductor element is dissipated well into the atmosphere, for example, a wiring board with a heat sink having a heat sink made of a metal having excellent thermal conductivity is known. Yes.

特開平０９−１４３７５６号公報JP 09-143756 A

そのような放熱板付配線基板の搭載部に電子部品が設置される際には、例えば、放熱板付配線基板は放熱板側から加熱され、その搭載部に電子部品が電子部品接着用の接着剤を介して接着される。しかし、このようにして得られる半導体装置では、理由は定かではないが、電子部品と放熱板との間（例えば、電子部品接着用の接着剤中や搭載部表面下など）に空隙（ボイド）が生じてしまうことがある。そして、ボイドの発生により、電子部品から発生した熱が放熱板にうまく伝わらず、放熱が良好に行われないという問題があった。   When an electronic component is installed on the mounting portion of such a wiring board with a heat sink, for example, the wiring board with a heat sink is heated from the heat sink side, and the electronic component has an adhesive for bonding the electronic component to the mounting portion. Glued through. However, in the semiconductor device obtained in this way, the reason is not clear, but there is a void between the electronic component and the heat sink (for example, in the adhesive for bonding the electronic component or under the surface of the mounting portion). May occur. Then, due to the generation of voids, there is a problem that heat generated from the electronic component is not transmitted well to the heat radiating plate and heat is not radiated well.

そこで、本発明の課題は、電子部品と放熱板との間のボイドを低減させ、良好な放熱を行うことが可能な放熱板付配線基板を提供することにある。   Then, the subject of this invention is providing the wiring board with a heat sink which can reduce the void between an electronic component and a heat sink, and can perform favorable heat dissipation.

課題を解決するための手段・発明の効果Means for solving the problems / effects of the invention

上記課題を解決するため、本発明者が鋭意研究した結果、放熱板付配線基板において、電子部品の搭載部を、放熱板上に形成された銀ロウ材の層と、その表面に施された金属メッキとによって構成した場合、ボイドの低減が可能になるとの知見を得た。
つまり、本発明の放熱板付配線基板は、
一方の主面上に電子部品の搭載部が形成される放熱板の当該主面において、前記搭載部が形成される領域を取り囲む貫通孔を有する配線基板が、接着材層を介して接着されてなる放熱板付配線基板であって、
前記接着材層は、銀ロウ材からなり、且つ少なくとも前記配線基板及び前記貫通孔の前記主面側の端面を含むよう前記主面に形成されてなるとともに、
前記貫通孔の前記主面側の端面に形成された前記接着材層は、その表面に金属メッキが施されることにより前記搭載部を成すことを特徴とする。 In order to solve the above-mentioned problems, the present inventors have intensively studied. As a result, in the wiring board with a heat sink, the mounting part of the electronic component has a silver brazing material layer formed on the heat sink and a metal applied to the surface thereof. It has been found that voids can be reduced when configured by plating.
That is, the wiring board with a heat sink of the present invention is
A wiring board having a through-hole surrounding a region where the mounting portion is formed is bonded via an adhesive layer on the main surface of the heat sink where the mounting portion of the electronic component is formed on one main surface. A wiring board with a heat sink,
The adhesive layer is made of a silver brazing material, and is formed on the main surface so as to include at least the end surface on the main surface side of the wiring board and the through hole,
The adhesive layer formed on the end surface on the main surface side of the through-hole forms the mounting portion by performing metal plating on the surface thereof.

また、本発明の放熱板付配線基板では、金属メッキは、Ｎｉメッキ層上にＡｕメッキ層が形成されてなるＮｉ−Ａｕメッキとすることができる。   In the wiring board with a heat sink of the present invention, the metal plating can be Ni—Au plating in which an Au plating layer is formed on a Ni plating layer.

以下、本発明の放熱板付配線基板の実施形態を、図面を参照しつつ説明する。
図１は、本発明の放熱板付配線基板１の概略を示す斜視図であり、図２は断面図である。なお、図１及び２では、放熱板付配線基板１にＩＣチップ（電子部品）１００が搭載され、半導体装置を成している。図１及び２に示すように、放熱板付配線基板１は、平面視が長方形又は正方形で所定の厚みを有する放熱板２を備え、放熱板２の上側主面２１表面のほぼ中央には、配線基板本体４が接着材層３を介して接着されている。放熱板２は、上側主面２１及び下側主面２２を有し、且つ厚みが例えば１ｍｍ程度の金属板（具体的な材料については後述する）からなる。 Hereinafter, an embodiment of a wiring board with a heat sink of the present invention will be described with reference to the drawings.
FIG. 1 is a perspective view schematically showing a wiring board 1 with a heat sink of the present invention, and FIG. 2 is a cross-sectional view. In FIGS. 1 and 2, an IC chip (electronic component) 100 is mounted on the wiring board 1 with a heat sink to form a semiconductor device. As shown in FIGS. 1 and 2, the wiring board 1 with a heat radiating plate includes a heat radiating plate 2 that is rectangular or square in plan view and has a predetermined thickness. The substrate body 4 is bonded via the adhesive layer 3. The heat sink 2 is composed of a metal plate (specific materials will be described later) having an upper main surface 21 and a lower main surface 22 and a thickness of, for example, about 1 mm.

配線基板本体４は、平面視が長方形又は正方形を呈し、内側にほぼ相似形の貫通孔４１を有するとともに、例えばアルミナを主成分とするセラミックからなる複数の絶縁層７１と、これらの間に形成された例えば銅を主成分とする配線層７３、７４を含んでいる。図２に示すように、２つの配線層７３、７４の間は、ビア導体７５によって接続され、上層の配線層７４と配線基板本体４の上面４２に形成されたパッド７７との間は、ビア導体７６によって接続されている。   The wiring board body 4 has a rectangular or square shape in plan view, has a substantially similar through hole 41 on the inside, and is formed between a plurality of insulating layers 71 made of ceramic mainly composed of alumina, for example. For example, the wiring layers 73 and 74 mainly composed of copper are included. As shown in FIG. 2, the two wiring layers 73 and 74 are connected by a via conductor 75, and the upper wiring layer 74 and the pad 77 formed on the upper surface 42 of the wiring board body 4 are connected with vias. They are connected by conductors 76.

接着材層３は、銀ロウ材、詳しくは主成分（７０％以上を含むものとする）のＡｇと、Ｃｕとを含む合金から成り、また少なくとも配線基板本体４及び貫通孔４１の放熱板２の上側主面２１側の端面（配線基板本体４では下側表面４８、貫通孔４１では下側端面４４）を含むよう放熱板２の上側主面２１に形成されてなる。これにより、ＩＣチップ１００を搭載するための搭載部５の下側に接着材層３の層が存在することになる（詳細な構造については後述する）。なお、接着材層３の上側表面３１のうち、貫通孔４１の下側端面４４に対応する部分を貫通孔内表面３３とする。また、搭載部５付近では、配線基板本体４の貫通孔４１の下側端面４４と、接着材層３の上側表面３１とが、ほぼ平行となるように接着材層３が形成されている。即ち、接着材層３は、図２に示すように、放熱板２の上側表面２１上にほぼ均一な厚みで形成されている。また、接着材層３は、銀ロウ材以外に、銀メッキで形成してもよい。   The adhesive layer 3 is made of a silver brazing material, specifically an alloy containing Ag as a main component (including 70% or more) and Cu, and at least the upper side of the heat sink 2 of the wiring board main body 4 and the through hole 41. It is formed on the upper main surface 21 of the heat sink 2 so as to include the end surface on the main surface 21 side (the lower surface 48 in the wiring board body 4 and the lower end surface 44 in the through hole 41). Thereby, the layer of the adhesive material layer 3 exists under the mounting portion 5 for mounting the IC chip 100 (detailed structure will be described later). A portion of the upper surface 31 of the adhesive layer 3 corresponding to the lower end surface 44 of the through hole 41 is referred to as a through hole inner surface 33. In the vicinity of the mounting portion 5, the adhesive layer 3 is formed so that the lower end surface 44 of the through hole 41 of the wiring board body 4 and the upper surface 31 of the adhesive layer 3 are substantially parallel. That is, the adhesive layer 3 is formed with a substantially uniform thickness on the upper surface 21 of the heat sink 2 as shown in FIG. The adhesive layer 3 may be formed by silver plating in addition to the silver brazing material.

また、本発明の放熱板付配線基板１の搭載部５にＩＣチップ１００を搭載して半導体装置とする場合、搭載部５の露出した表面と、表面ＩＣチップ１００の下側表面１０２とが対向するよう、例えばＡｕ−Ｓｉ合金からなる接着剤１１０を介して固着させる。図２に示すように、ＩＣチップ１００の上側表面１０１に形成されたパッド１０３と、配線基板本体４の上側表面４２にあるパッド７７のうち内周側に形成されたものとの間には、端部１３１により両端を固着されたＡｕワイヤ１３０が接続される。また、配線基板本体４の上側表面４２にあるパッド７７のうち外周側に形成されたものには、銀ロウ１３２を介して接続され且つ外側に延びるリード１４０の一端が固着される。   Further, when the IC chip 100 is mounted on the mounting portion 5 of the wiring board 1 with a heat sink of the present invention to form a semiconductor device, the exposed surface of the mounting portion 5 and the lower surface 102 of the surface IC chip 100 face each other. For example, the adhesive 110 is made of an Au—Si alloy. As shown in FIG. 2, between the pad 103 formed on the upper surface 101 of the IC chip 100 and the pad 77 formed on the inner peripheral side of the pad 77 on the upper surface 42 of the wiring board body 4, The Au wire 130 having both ends fixed by the end 131 is connected. In addition, one end of a lead 140 that is connected via the silver solder 132 and extends outward is fixed to the pad 77 formed on the outer peripheral side of the upper surface 42 of the wiring board body 4.

図３は、本発明の放熱板付配線基板１の詳細な構造を表す図である。まず、放熱板２は、例えばＣｕ−Ｗ合金からなる厚みが１ｍｍ程度の金属板２５を主体とし、その表面には放熱板用メッキ２８が施されている。放熱板用メッキ２８は、金属板２５表面に形成され例えば厚さが０．５〜１．０μｍ程度のＮｉ−Ｂメッキからなる第１放熱板用メッキ層２６と、その表面に形成され例えば厚さが２．０〜２．５μｍ程度のＮｉ−Ｐメッキからなる第２放熱板用メッキ層２７とからなる。   FIG. 3 is a diagram showing a detailed structure of the wiring board 1 with a heat sink of the present invention. First, the heat radiating plate 2 is mainly composed of a metal plate 25 made of, for example, a Cu—W alloy and having a thickness of about 1 mm, and the surface thereof is provided with a heat radiating plate plating 28. The heat sink plate 28 is formed on the surface of the metal plate 25, for example, the first heat sink plate layer 26 made of Ni-B plating having a thickness of about 0.5 to 1.0 μm, and formed on the surface thereof. And a second heat radiation plate plating layer 27 made of Ni-P plating with a thickness of about 2.0 to 2.5 μm.

また、放熱板２の上側主面２１には、上述したように、接着材層３（例えば、厚さ４０μｍ程度）を介して配線基板本体４が接着されており、そしてそれらのうち、配線基板本体４の表面を除く表面（放熱板２及び接着材層３の露出面）には表面メッキ６が施されている。表面メッキ６は、例えばＮｉ−Ａｕメッキにより構成され、例えば厚さ３．０μｍ程度のＮｉメッキからなる第１表面メッキ層６１上に、例えば厚さ３．０μｍ程度のＡｕメッキからなる第２表面メッキ層６２が形成されてなる。したがって、搭載部５は、接着材層３の貫通孔内表面３３上に、表面メッキ層６が施されたものからなる。   Further, as described above, the wiring board body 4 is bonded to the upper main surface 21 of the heat radiating plate 2 via the adhesive layer 3 (for example, about 40 μm in thickness). A surface plating 6 is applied to the surface excluding the surface of the main body 4 (exposed surfaces of the heat sink 2 and the adhesive layer 3). The surface plating 6 is made of, for example, Ni—Au plating. For example, on the first surface plating layer 61 made of Ni plating with a thickness of about 3.0 μm, for example, a second surface made of Au plating with a thickness of about 3.0 μm. A plated layer 62 is formed. Therefore, the mounting portion 5 is formed by applying the surface plating layer 6 on the inner surface 33 of the through hole of the adhesive layer 3.

本発明の放熱板付配線基板の実施例及び比較例について、以下のような試験を行った。実施例は、図３に示すような搭載部５と放熱板２との間にＡｇロウからなる接着材層３が形成され、その上にはＡｕ−Ｎｉメッキが施された放熱板付配線基板１である。また、比較例は図４に示すように、Ａｇロウからなる接着材層３が、搭載部５と放熱板２との間に形成されず、配線基板本体４と放熱版２との間のみに形成された放熱板付配線基板１´である。なお、比較例では放熱板２上に直接Ａｕ−Ｎｉメッキが施されることにより搭載部５をなしている。   The following tests were conducted on Examples and Comparative Examples of the wiring board with a heat sink of the present invention. In the embodiment, an adhesive layer 3 made of Ag solder is formed between the mounting portion 5 and the heat radiating plate 2 as shown in FIG. 3, and a wiring board 1 with a heat radiating plate on which Au—Ni plating is applied. It is. Further, in the comparative example, as shown in FIG. 4, the adhesive layer 3 made of Ag solder is not formed between the mounting portion 5 and the heat radiating plate 2, but only between the wiring board body 4 and the heat radiating plate 2. It is the formed wiring board 1 ′ with a heat sink. In the comparative example, the mounting portion 5 is formed by directly performing Au—Ni plating on the heat sink 2.

搭載部５の表面から、Ｃｕ−Ｗ合金からなる金属板２５までの構成は、搭載部５の表面から順に、実施例では、Ａｕメッキ、Ｎｉメッキ、銀ロウ、Ｎｉ−Ｐメッキ、Ｎｉ−Ｂメッキであり、厚さはそれぞれ上記した通りである。一方、比較例では、Ａｕメッキ、Ｎｉメッキ、Ｎｉ−Ｐメッキ、Ｎｉ−Ｂメッキであり、それぞれの厚さは、銀ロウを除いた実施例（図３）の場合と同様である。   The structure from the surface of the mounting portion 5 to the metal plate 25 made of Cu—W alloy is, in the embodiment, in order from the surface of the mounting portion 5, Au plating, Ni plating, silver brazing, Ni—P plating, Ni—B. It is plating and the thickness is as described above. On the other hand, in a comparative example, it is Au plating, Ni plating, Ni-P plating, and Ni-B plating, and each thickness is the same as that of the example (FIG. 3) except silver solder.

以上のような実施例及び比較例の放熱板付配線基板に対して、ＩＣチップ付けを行い、その後ＩＣチップ下のボイド発生の評価を行った。ＩＣチップ付けは、放熱板付配線基板に対して、放熱板側から加熱を行い、チップ付用接着剤（Ａｕ−Ｓｉ合金からなる）により接着した。そして、ＩＣチップを剥がし、チップ付用接着剤内部にボイドが存在するかどうかを、超音波探傷装置を用いて調べた。具体的には、チップ付用接着剤の外表面から超音波を伝播させ、ボイドと衝突して反射した波を検出し、その検出信号に基づき画像処理（前記伝播方向に投影した投影図が得られる）を行うことで、内部に存在するボイドの位置、大きさ等の情報が特定できる。評価判定基準は、前記画像処理により得られた画像の視野面積のうち、ボイドの像が占める割合（以下、ボイド占有率という）が１０％以下である場合を合格とし、１０％を超える場合を不合格とした。評価結果によると、チップ付用接着剤内に発生するボイドの量は、実施例の場合の方が比較例の場合よりも少ないことがわかった。   An IC chip was attached to the wiring board with a heat sink of the examples and comparative examples as described above, and then evaluation of void generation under the IC chip was performed. For IC chip attachment, heat was applied from the heat dissipation plate side to the wiring substrate with heat dissipation plate, and was adhered by an adhesive for chip (made of Au-Si alloy). Then, the IC chip was peeled off, and it was examined using an ultrasonic flaw detector whether or not a void was present inside the adhesive for chip. Specifically, an ultrasonic wave is propagated from the outer surface of the adhesive with a chip, a wave that collides with a void and reflected is detected, and image processing is performed based on the detection signal (a projection view projected in the propagation direction is obtained). Information such as the position and size of voids existing inside can be specified. The evaluation criterion is a case where the proportion of void images occupied by the image (hereinafter referred to as void occupancy ratio) is 10% or less in the visual field area of the image obtained by the image processing, and the case where it exceeds 10%. It was rejected. According to the evaluation results, it was found that the amount of voids generated in the adhesive for chip was smaller in the example than in the comparative example.

以上のように、放熱板付配線基板において、電子部品の搭載部が、放熱板上に形成された銀ロウ材からなる層、及びその表面に施された金属メッキによって構成された結果、電子部品と放熱板との間のボイドを低減させ、良好な放熱を行うことが可能な放熱板付配線基板を得ることができた。   As described above, in the wiring board with a heat sink, as a result of the electronic component mounting portion being constituted by the layer made of the silver brazing material formed on the heat sink and the metal plating applied to the surface thereof, the electronic component and It was possible to obtain a wiring board with a heat sink that can reduce voids between the heat sink and perform good heat dissipation.

本発明の放熱板付配線基板の概略を示す斜視図（ＩＣチップ搭載）。The perspective view which shows the outline of the wiring board with a heat sink of this invention (IC chip mounting). 本発明の放熱板付配線基板の概略を示す断面図（ＩＣチップ搭載）。Sectional drawing (IC chip mounting) which shows the outline of the wiring board with a heat sink of this invention. 本発明の放熱板付配線基板の詳細な構造を表す図。The figure showing the detailed structure of the wiring board with a heat sink of this invention. 比較例の放熱板付配線基板の詳細な構造を表す図。The figure showing the detailed structure of the wiring board with a heat sink of a comparative example.

符号の説明Explanation of symbols

１ 放熱板付配線基板
２ 放熱板
２５ 金属板
２６ 第１放熱板メッキ層
２７ 第２放熱板メッキ層
３ 接着材層
４ 配線基板本体
４１ 配線基板本体４の貫通孔
５ 搭載部
６１ 第１表面メッキ層
６２ 第２表面メッキ層
１００ ＩＣチップ（電子部品）
１１０ ＩＣチップ１００接着用の接着剤 DESCRIPTION OF SYMBOLS 1 Wiring board with a heat sink 2 Heat sink 25 Metal plate 26 1st heat sink plating layer 27 2nd heat sink plating layer 3 Adhesive material layer 4 Wiring board main body 41 Through-hole of wiring board main body 5 Mounting part 61 1st surface plating layer 62 Second surface plating layer 100 IC chip (electronic component)
110 Adhesive for bonding IC chip 100

Claims (1)

一方の主面上に電子部品の搭載部が形成される放熱板の当該主面において、前記搭載部が形成される領域を取り囲む貫通孔を有する配線基板が、接着材層を介して接着されてなる放熱板付配線基板であって、
前記接着材層は、銀ロウ材からなり、且つ少なくとも前記配線基板及び前記貫通孔の前記主面側の端面を含むよう前記主面に形成されてなるとともに、
前記貫通孔の前記主面側の端面に形成された前記接着材層は、その表面に金属メッキが施されることにより前記搭載部を成すことを特徴とする放熱板付配線基板。 A wiring board having a through-hole surrounding a region where the mounting portion is formed is bonded via an adhesive layer on the main surface of the heat sink where the mounting portion of the electronic component is formed on one main surface. A wiring board with a heat sink,
The adhesive layer is made of a silver brazing material, and is formed on the main surface so as to include at least the end surface on the main surface side of the wiring board and the through hole,
The wiring board with a heat sink, wherein the adhesive layer formed on the end surface on the main surface side of the through hole forms the mounting portion by applying metal plating to the surface thereof.
JP2003418020A 2003-12-16 2003-12-16 Wiring board with heat sink Expired - Fee Related JP4190404B2 (en)

Priority Applications (1)

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JP2003418020A JP4190404B2 (en) 2003-12-16 2003-12-16 Wiring board with heat sink

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003418020A JP4190404B2 (en) 2003-12-16 2003-12-16 Wiring board with heat sink

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JP2005183447A JP2005183447A (en) 2005-07-07
JP4190404B2 true JP4190404B2 (en) 2008-12-03

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