JP4183920B2 - Packet data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pipelined packet data processing apparatus that processes input packet data.
[0002]
[Prior art]
In performing packet communication between terminals, an IP (Internet Protocol) network is currently most commonly used. In this IP network, a network node that performs relaying between networks performs packet processing such as header rewriting processing in a packet and search and routing of a destination table provided in the device for the relay device. With the recent increase in the speed of the Internet, network nodes that perform packet relays attempt to speed up packet processing by performing packet processing with dedicated hardware. Conventionally, there is a method of performing store-and-forward processing when a packet processing unit of a network node that relays packets processes a packet.
[0003]
FIG. 22 is a diagram showing a conventional configuration of the store-and-forward method. In this configuration, the packet processing unit 2 configured by a general processor or dedicated hardware and the memory 4 are connected by the bus 6, and the packet processing unit 2 stores the necessary data of the packet stored in the memory 4. On the other hand, processing necessary for packet relay is performed. In the conventional store-and-forward packet processing, the packet processing unit 2 processes the packet stored in the memory 4 in accordance with a software instruction prepared in advance. For this reason, in this packet processing, it is possible to easily change the processing to be performed on the packet later by rewriting a software instruction prepared in advance. Therefore, the processing content can be changed later for the purpose of revision of the protocol and improvement of the service function provided as a network.
[0004]
However, in this process, since the packet data is stored in the memory 4, a read / write operation to the memory 4 storing the packet data is required. The packet processing unit 2 gives the address of the memory to be read to the memory 4 and then reads the data from the memory 4, or the packet processing unit 2 gives the address of the memory to be written by the packet processing unit 2 to the memory 4 and then the memory The process of writing data to 4 is performed. At this time, the time for the packet processing unit 2 to read and write data from the memory 4 after the processor gives an address to the memory 4 is considerably longer than the cycle time of the processor. For this reason, the overhead of read / write processing to the memory 4 becomes a problem, and packet processing cannot be performed at high speed.
[0005]
Therefore, in recent years, a method has been devised for executing packet processing at high speed with a dedicated hardware circuit. In the dedicated hardware circuit, packet processing can be performed with a high-speed hardware clock, so that packets can be processed at high speed. However, there is a problem that it is not possible to easily change the function for improving the function, and it is necessary to develop new hardware each time. By the way, when the network node processes the IP and lower layer protocols, the processing is performed based on information in each protocol header, and information in the data portion of the IP is rarely required. Hardware that performs high-speed processing can be considered by paying attention to the locality that the processing target is only each protocol header.
[0006]
FIG. 23 is a diagram illustrating a packet data processing processor that focuses on locality of processing. The packet data processor 10 includes a general-purpose register 12, an arithmetic unit 14, and shift registers 16 and 18. The packet data processor 10 is a pipeline composed of shift registers 16 and 18 for shifting packet data and information synchronized with the packet such as the result of an operation to be temporarily stored to the next stage for each clock. To store. In the packet data processor 10, processing to be performed on the packet is described in advance by software. The packet data processor 10 is activated when the head of a packet is input, and performs processing according to a description of software prepared in advance. The data in the registers 16 and 18 constituting each pipeline is shifted by the clock, and the packet data processing processor 10 performs processing for the determined number of clocks. When the next packet is input after the processing is completed, the processing is similarly performed on the packet.
[0007]
FIG. 24 is a diagram illustrating a hardware configuration in which a plurality of packet processors are arranged. As shown in FIG. 24, in this hardware configuration, a plurality of packet processors 30 # i (i = 1 to n) are arranged. Each packet data processor arranged as shown in FIG. 24 performs each process and completes the packet processing required by the network node as a whole. Processing a packet in such a processing system means that if the packet processing has locality, such as the processing only reaches the IP layer, it can be processed at high speed by a pipelined register, and the software can be changed. Processing can be changed flexibly.
[0008]
[Problems to be solved by the invention]
On the other hand, there is an increasing need for multi-functional processing at network nodes, and some of such processing requires adding new headers to the packets and deleting unnecessary headers. is there. There is a tunneling process that requires such a process. The tunneling process is used when, for example, communication between two private networks is used via a shared network such as the Internet.
[0009]
FIG. 25 is a network configuration diagram in which two private networks are connected by a shared network. In FIG. 25, consider a case where communication is performed from the private network 40 # A to the private network 40 # B. A packet transmitted from the private network 40 # A is added with a header for the shared network 42 by the network node 44 # A connecting the private network 40 # A and the shared network 42 (capsule processing), and is sent to the shared network 42 such as the Internet. Sent. Then, when the network node 44 # B connecting the other private network 40 # B receiving the packet and the shared network 42 receives the packet sent from the private network 40 # A, it is added at the time of the capsule processing. The header is deleted (decapsulation processing), the packet is returned to the state before being encapsulated, and the packet is transmitted to another private network 40 # B. Therefore, in the network nodes 44 # A and 44 # B that need to perform the capsule process / decapsulation process, it is necessary to perform the header addition / deletion operation as described above.
[0010]
In the packet data processing method in which processing is performed by paying attention to the locality of packet processing, processing is performed by register access, so that packet processing can be performed at high speed. Since addition / deletion of the header is also performed by paying attention to the header, the processing can be performed at high speed by using this processing method.
[0011]
FIG. 26 is a diagram illustrating a state of the packet data processor before data addition / deletion. For example, consider a case where a packet is stored in the shift register 18 in the state shown in the figure. A hatched portion in FIG. 26 indicates a packet, and a packet header is stored in P2. At this time, in order to delete the data in P0, the data in P2 and P1 may be overwritten in P1 and P0, respectively. When it is desired to add data between P0 and P1, the data in P1 and P2 can be overwritten in P2 and P3, respectively, and the data to be added in P1 can be written. However, in the data addition processing, there is a problem because the total length of the packet after processing is longer than the packet before processing.
[0012]
FIG. 27 is a diagram illustrating the state of the shift register when packets are in close contact. In this packet data processing method, when packets are input continuously, the packets are input one after another as shown in FIG. If a packet is added in this state, data is written on the packet processed before the packet, and the data of the previously processed packet is destroyed. For example, when data of a previously processed packet is stored in P3, data in P2 is destroyed by data of a later packet. In order to avoid this, if the packet is input to the packet data processing group, if the control is performed so as to leave a certain interval between the packets, data will not be overwritten in the previously processed packet, Data can be added. However, if a certain interval is provided between all packets, an interval is also provided for packets that do not require data addition, and the throughput of the processing may be reduced.
[0013]
As described above, processing that shortens the total length of a packet, such as deleting a packet, can be handled without any problem by a conventional packet data processor. However, if a conventional packet data processing processor performs a process in which the total length of the packet is longer than the original total length, such as adding a packet, there is a problem that the processing efficiency decreases.
[0014]
The present invention has been made in view of the above, and an object of the present invention is to provide a packet data processing apparatus capable of adding packet data without lowering the processing efficiency.
[0015]
[Means for Solving the Problems]
FIG. 1 shows the principle of the present invention. As shown in FIG. 1, the bucket data processing apparatus processes a packet input to each of the packet data processing units 50 # i (i = 1, 2) configured in a pipeline configuration that outputs to the subsequent stage. ,...). The first packet data processing unit 50 # A in the packet data processing group 52 includes a data adding unit 54 that adds data to the input packet. While the data adding unit 54 is performing the data adding process, the packet data processing device instructs the preceding stage of the first packet data processing unit 50 # A to stop outputting the packet, and the data adding unit 54 performs the data adding process. After the completion, the control unit 56 is further provided in front of the first packet data processing unit 50 # A for instructing to resume the output of the packet.
[0016]
When a packet is input to the packet data processing device, each packet data processing unit 50 # i (i = 1, 2,...) Performs a predetermined process on the packet. The control unit 56 provided separately from the packet data processing group 52 or the packet data processing group 52, when it is necessary to add data to the packet, sets at least the data addition length between the data addition target packet and the previous packet. In order to secure a sufficient amount, the packet data processing unit 50 # i (i = 1, 2,..., B) preceding the first packet data processing unit 50 # A is instructed to stop outputting packet data. The data adding unit 54 adds data to the packet when the data adding length is secured. As described above, when the packet data processing group 52 processes a packet by pipeline processing and needs to add data to the packet, it simply stops output to the subsequent stage of the packet data. Packet data can be added without reducing efficiency.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 2 is a block diagram of the packet data processing apparatus according to the first embodiment of the present invention. The packet data processing apparatus shown in FIG. 2 includes, for example, network nodes 44 # A and 44 # that connect the private networks 40 # A and 40 # B of the network shown in FIG. 25 and the shared network 42 such as the Internet. This is applied to B. As shown in FIG. 2, the packet data processing device 60 includes a plurality of reception interface cards 62 # i (i = 1 to n), a switch fabric 64, and a plurality of transmission interface cards 66 # i (i = 1 to n). Have. The reception interface card 62 # i (i = 1 to n) has the following functions. (1) The packet is received from the corresponding private network, for example, a LAN or a shared network. {Circle around (2)} It is determined whether or not the received packet needs to be encapsulated / decapsulated from the packet header. (3) Capsule processing / decapsulation processing is performed when it is necessary to perform capsule processing / decapsulation processing. Note that data addition processing is performed in the capsule processing, and data deletion processing is performed in the decapsulation processing. (4) The packet subjected to the capsule processing or the like is output to the switch fabric 64.
[0018]
The reception interface card 62 # i includes a reception interface unit 70 # i, a pre-processing unit 72 # i, and a packet data processing processor group 74 # i. The reception interface unit 70 # i receives a packet according to the physical interface. The pre-processing unit 72 # i performs preprocessing such as detection of a packet header for the packet processor group 74 # i to add / delete data to / from the packet. The packet processing processor group 74 # i is configured such that a plurality of packet data processing processors are pipelined to perform processing on packets, and have the following functions, for example. (1) It is determined from the packet header whether or not it is necessary to add / delete data to / from the packet. (2) When it is determined that data needs to be added to the packet, the data to be added, the data length, and the position to be added on the packet are obtained. (3) When it is determined that it is necessary to delete data from the packet, the data length to be deleted and the position to be deleted on the packet are obtained. Data is added / deleted based on the data length obtained in (4), (2) and (3). (5) When adding data, in order to secure at least the additional data length interval between the addition target packet and the previous packet, the packet processing processor in the previous stage of the packet data processing processor that performs the data addition processing stops outputting the packet data. And the operation of the active packet data processor is stopped. {Circle around (6)} When an interval corresponding to the length of the previous packet and the additional data is secured, the previous packet processing processor resumes outputting the packet data and resumes the operation of the packet data processor that has stopped the operation. (7) The packet length after the change by adding / deleting data is set in the packet header.
[0019]
FIG. 3 is a configuration diagram of the packet data processor group 74 # i in FIG. As shown in FIG. 3, the packet processor group 74 # i includes a bus 88 that transfers intermediate data other than packets, a bus 89 that transfers packets, and a plurality of packet data processors that are pipeline-connected by the buses 88 and 89. 90 # i (i = 1 to n) and a back pressure signal line 92. Buses 88 and 89 are data buses for transferring intermediate data and packets. The packet data processor 90 # i (i = 1 to n) holds intermediate data and packet data input from the buses 88 and 89 in its own shift register and performs predetermined processing on the packet. . The number of stages is arbitrarily set according to the contents of the entire packet processing.
[0020]
The packet data processor 90 # A adds / deletes data in accordance with instructions from the preceding packet data processor group. Specifically, the following processing is performed. {Circle around (1)} Whether or not it is necessary to add / delete data to a packet is determined according to the instruction from the packet data processor group in the previous stage. {Circle around (2)} When data needs to be added to a packet, the additional data position and additional data are specified based on an instruction from the preceding packet processor group, and the data is added. {Circle around (3)} Based on the additional data length, the back pressure signal line 92 is asserted for a time corresponding to the number of clocks corresponding to the additional data length, and the operation of the packet data processing processor group preceding the packet data processing processor is stopped. . (4) When data deletion is necessary, the deletion data position and the deletion data length are specified based on the instruction of the packet processor group in the previous stage, and the data deletion processing is performed. Note that the operation stop / restart control for the packet data processor 90 # i (i = 1, 2, B,...) Preceding the packet data processor 90 # A of (3) and (4) is controlled by the packet data processor. You may make it carry out by the control part independent of the group. Further, during the period in which the back pressure signal line 92 is asserted and the operation of the packet data processor group is stopped, the preceding stage (the preceding stage processing unit 72 # i in the configuration of FIG. 2) temporarily transfers data according to the back pressure. Stop.
[0021]
FIG. 4 is a block diagram of the packet data processor 90 # A in FIG. As shown in FIG. 4, the packet data processor 90 # A includes a general-purpose register 93 # A, an arithmetic unit 94 # A, an intermediate data register 96 # A, and a packet access register 98 # A. The general purpose register 93 # A is, for example, eight 32-bit length registers r0 to r7. The arithmetic unit 94 # A is a processor that performs an operation in accordance with an instruction code described in a program. When data is added, the back pressure signal line 92 is asserted for a period corresponding to the additional data length. The intermediate data register 96 # A is, for example, 16 stages of 32-bit shift register registers e0 to e15 for holding and transmitting a processing result related to the packet data in synchronization with the packet data. The data held in the intermediate data register 96 # A includes, for example, data indicating the beginning of the packet, flag bits indicating whether data needs to be added / deleted, additional data, additional data position, additional data length, deleted data It is the position and deleted data length. The packet access register 98 # A is, for example, 16 stages of 32-bit shift register registers p0 to p15 for directly capturing packet data.
[0022]
The packet data processor 90 # B preceding the packet data processor 90 # A performs the following processing. (1) It is determined from the packet header whether it is necessary to perform processing for adding / deleting data to / from the packet. (2) When it is determined that data needs to be added to the packet, the data to be added, the data length, and the position to be added on the packet are obtained. (3) When it is determined that data is to be deleted from the packet, the data length to be deleted and the position to be deleted on the packet are obtained. (4) The intermediate data obtained by (1) to (3) is output on the data bus. (5) When the back pressure signal line 92 is asserted, the shifting operation of the packet data and the intermediate data is stopped and the processing is stopped if the packet processing is in progress. {Circle around (6)} When the back pressure signal line 92 is negated, the shifting operation of the packet data and the intermediate data is resumed and the suspended processing is resumed.
[0023]
FIG. 5 is a block diagram of the packet data processor 90 # B in FIG. When the back pressure signal line 92 is asserted, the packet data processor 90 # B, for example, stops the system clock based on the back pressure signal, whereby the arithmetic unit 94 # B, the intermediate data register 96 # B, The operation of the packet access register 98 # B is stopped. The general-purpose register 93 # B, the arithmetic unit 94 # B, the intermediate data register 96 # B, and the packet access register 98 # B are substantially the same as those in FIG. The configuration of the packet processor 90 # i (i = 1, 2,...) Upstream of the packet data processor 90 # A is substantially the same as that of the packet data processor 90 # B. The configuration of the packet processor 90 # C subsequent to the packet data processor 90 # A is substantially the same as that of the packet data processor 90 # B except that the operation does not need to be stopped according to the back pressure signal line 92. For example, when data addition / deletion is performed according to the intermediate data, the packet length information in the packet header is updated.
[0024]
The switch fabric 64 in FIG. 2 inputs a packet from the receiving interface card 62 # i (i = 1 to n), and refers to the routing table according to the IP address or MAC address set in the packet header. Routing to the corresponding transmission interface card 66 # k (k = 1 to n). However, the routing table reference processing may be performed by the packet processing processor group 74 # i, and the switch fabric 64 may be routed to the transmission interface card 66 # k (k = 1 to n) determined according to the processing result. The transmission interface card 66 # i has a transmission interface unit 80 # i. The transmission interface unit 80 # i inputs a packet from the switch fabric 64 and transmits the packet according to the physical interface of the transmission path. Hereinafter, the operation of the packet data processing device 50 of FIG. 2 will be described.
[0025]
(1) Operation of reception interface card 62 # i
The reception interface unit 70 # i in each reception interface card 62 # i receives the packet data from the transmission path according to a predetermined physical interface, and outputs the packet data to the upstream processing unit 72 # i. The pre-stage processing unit 72 # i performs serial / parallel conversion on the 32-bit parallel data of the packet data, and outputs it to the data bus connected to the packet access register 96 # 1. The packet header is detected and a flag indicating the header is output to the data bus connected to the intermediate data register 96 # 1 in synchronization with the packet. Each packet data processor 90 # j (j = 1, 2,...) In the packet data processor group 74 # i stores the packet in the intermediate data register 96 # j when the packet is stored in the packet access register 98 # j. Each process is performed on the packet in accordance with the stored intermediate data. Further, the data output is stopped during the period when the back pressure signal is notified from the packet processing processor group 74 # i by the back pressure signal.
[0026]
(A) Determination of data addition / deletion
The packet data processor 90 # B determines from the packet header whether or not to add / delete data to / from the packet. If it is determined that data is to be added to the packet, the data to be added, the data length, and the position to be added on the packet are obtained. When it is determined that data is deleted from the packet, the data length to be deleted and the position to be deleted on the packet are obtained. Flag bit indicating whether to perform addition / deletion. When adding data, data to be added, data length to be added, position of the data to be added on the packet, data length to be deleted, data to be deleted The position of the data on the packet is written in the intermediate data register 96 # B in synchronization with the packet. The packet data and the intermediate data are transferred by the packet access register, the intermediate data register, and the data bus in the packet processing processor group 74 # i in synchronization with the clock.
[0027]
(B) Operation of packet data processor 90 # A
The packet data processor 90 # A is activated when a packet is input to the packet access register 98 # A. When a packet is input to the packet access register 98 # A, whether or not data needs to be added to or deleted from the packet data processor in the previous stage input to the intermediate data register 96 # A in synchronization with the packet Is determined by the flag bit. When addition is required from the flag bit, the data to be added, the additional data length, and the addition position on the packet are obtained from the intermediate data register 96 # A. If deletion is necessary, the deletion data length and the deletion position on the packet are obtained from the intermediate data register 96 # A. Here, it is assumed that an instruction is given to add 64-bit data to the 32nd bit from the beginning of the packet.
[0028]
(B-1) Data addition
FIG. 6 is a diagram illustrating the packet data processor 90 # A after determination of data addition. Assume that the head data of a packet to which data is to be added is stored in the register P3 of the packet access register 98 # A. Further, it is assumed that the final data of the previous packet of this packet is stored in the register P4. The packet data processor 90 # A asserts the back pressure signal line 92 for a clock time corresponding to the additional data length so as not to shift the packet access register with respect to the packet data processor upstream of itself. The shift operation of the register of the packet access register 98 # A storing the data addition target packet is stopped. A shift operation is performed on the register of the packet access register 98 # A in which the previous packet of the data addition target packet is stored. Here, since the head of the data addition target packet is stored in the register P3 of the packet access register 98 # A, the shift operation of the registers P3-P0 is stopped. On the other hand, the shift operation of the registers P4 to P15 continues.
[0029]
On the other hand, when the back pressure signal line 92 is asserted, the packet data processor 90 # i (i = 1, 2, B,...) Prior to the packet data processor 90 # A In order to stop the operation of the intermediate data register, for example, the system clock is negated. Here, since the size of the additional data is 64 bits and the packet access register 98 # A is 32 bits, the data transfer of the data addition target packet and the subsequent packet data is stopped for 64 ÷ 32 = 2 clocks. However, the packet data before that must continue to be transferred. Therefore, the transfer of the packet data after the register P3 is stopped for two clocks, and the transfer of the packet data before the data of the register P4 is continuously performed.
[0030]
FIG. 7 shows the packet data processor 90 # A after two clocks. As shown in FIG. 7, after 2 clocks, a space is secured in the registers P4 and P3 of the 32nd bit from the beginning of the packet, which is the position where data is to be added. The packet data processor 90 # A, which has determined that it must be stopped for two clocks, can resume the shift of the packet after two clocks have elapsed. The pressure signal line 92 is negated to instruct the packet data processor prior to the packet data processor 90 # A to resume the shift. When the back pressure signal line 92 is negated, the packet data processing processor preceding the packet data processing processor 90 # A resumes the shift operation. The packet data processor that has suspended the instruction resumes the suspended instruction. The packet data processor 90 # A moves by the additional data length from the packet head data stored in the packet access register 98 # A to the data immediately before the position where the data is to be added. Thereafter, the data to be added stored in the intermediate data register 96 # A is stored in the register at the position to be added in the packet access register 98 # A. Then, the data in the intermediate data register 96 # A synchronized with the packet is moved as necessary.
[0031]
FIG. 8 is a diagram illustrating the state of the packet data processor 90 # A after data movement. Here, since it is added to the 32nd bit from the beginning of the packet, the data in the register P3 storing the 32bit data before the 32nd bit is moved by 64 bits. That is, the data hand of the register P3 is moved to the register P5. Thereafter, the additional data stored in the intermediate data register 96 # A is added to the 64-bit vacant place, the registers P3 and P4. The added packet is transferred to the subsequent packet data processor group by the shift operation of the packet access register 98 # A.
[0032]
(B-2) Data deletion
When deletion is necessary from the flag bit, the deletion data length and the deletion position on the packet are obtained from the intermediate data register 96 # A. For the packet to be deleted, the data before the deletion position stored in the packet access register 98 # A is moved behind the deletion data length. For example, when the deletion position on the packet is the 32nd bit from the beginning of the packet, the deletion data length is 64 bits, and the beginning of the packet is stored in the register P3, the 32-bit data stored in the register P3 is moved by 64 bits. That is, it moves to the register P1. At this time, the data in the intermediate data register 96 # A synchronized with the packet is moved as necessary. The deleted packet is transferred to the subsequent packet data processor group by the shift operation of the packet access register 98 # A.
[0033]
(C) Operation of packet data processor group in the subsequent stage of packet data processor 90 # A
The subsequent packet data processor group receives the packet data and intermediate data from the buses 88 and 89, and updates the packet header length when the packet processing, for example, the packet data processor 90 # A adds or deletes the data. Processing is performed, and a packet is output to the switch fabric 64 from the packet data processor 90 # C at the final stage.
[0034]
(2) Operation of switch fabric 64
The switch fabric 64 inputs a packet from the reception interface card 62 # i (i = 1 to n), refers to the routing table according to the IP address or MAC address set in the packet header, and corresponds to the transmission interface. Route to card 66 # k (k = 1 to n). However, the routing table reference processing may be performed for the packet processing processor group 74 # i, and the switch fabric 64 may be routed to the transmission interface card 66 # k (k = 1 to n) determined according to the processing result.
[0035]
(3) Operation of transmission interface card 66 # i
The transmission interface card 66 # i receives a packet from the switch fabric 64 and transmits the packet according to the physical interface of the transmission path.
[0036]
As described above, the packet data processor group determines whether it is necessary to add / delete data to the packet, and generates data necessary for addition / deletion. The packet data processor A receives such data, determines whether it is necessary to leave a packet interval by adding data, and if necessary, has the packet data processor group in the previous stage restrict the input of packets. As a result, it is possible to perform the data addition process without leaving a packet interval determined based on the size of the data to be added and reducing the packet processing throughput.
[0037]
Second embodiment
FIG. 9 is a block diagram of a packet data processing apparatus according to the second embodiment of the present invention. Components that are substantially the same as those in FIG. 2 are given the same reference numerals. In the packet data processing apparatus 100 shown in FIG. 9, the packet data processing processor group 104 # i in the reception interface card 104 # i is different from the packet data processing processor group 74 # i in FIG. The packet data processor group 104 # i can add / delete data even when the addition / deletion data length is not a multiple of the bit width of the packet access register of the packet data processor, and packet data to which data is added A buffer memory that holds packet data and intermediate data is provided in the processing processor, so that the shift operation is not stopped when data is added, but only when the buffer becomes insufficient due to data addition. Is different from the packet data processor group 74 # i in FIG.
[0038]
FIG. 10 is a block diagram of the packet data processor group 104 # i in FIG. 9, and components that are substantially the same as those in FIG. 3 are given the same reference numerals. In the buses 108 and 109 and the packet data processor 110 # i, the bit widths of the buses 108 and 109, the packet access register, and the intermediate data register are shown in FIG. In this example, the buses 88 and 89 and the packet data processor 90 # i are changed.
[0039]
FIG. 11 is a block diagram of the packet data processor 110 # i in FIG. 10, and components that are substantially the same as those in FIG. 5 are given the same reference numerals. The intermediate data register 120 # i is, for example, a four-stage 64-bit shift register register e0 to e3 for holding and transmitting a processing result related to the packet data in synchronization with the packet data. The packet access register 122 # i is, for example, four stages of 128-bit shift register registers p0 to p3 for directly capturing packet data. The data addition / deletion mechanism 112 adds / deletes data in the same manner as the packet data processor 90 # A in FIG. The data addition / deletion mechanism unit 112 is configured by dedicated hardware, for example.
[0040]
FIG. 12 is a configuration diagram of the data addition / deletion mechanism unit 112 in FIG. As shown in FIG. 12, the data addition / deletion mechanism unit 112 includes a data length check unit 120, an expansion / contraction buffer 122, a reorder unit 124, a write data extraction unit 126, and a data write unit 128. The data length check unit 120 obtains the total length of the data after data addition / deletion from the packet data and the intermediate data, and checks whether the maximum allowable packet length is exceeded. If it exceeds, an error is output.
[0041]
The expansion / contraction buffer 122 includes a packet data memory and intermediate data memory that store packet data and intermediate data, and a controller that controls these memories. Each memory is a FIFO (First In First Out) buffer. The packet data memory is a FIFO composed of a memory area having the same data bit width as that of the packet access register 122 # i, for example, 128 bits. The intermediate data buffer is a FIFO having the same data bit width as that of the intermediate data register 120 # i, for example, a 64-bit width.
[0042]
The controller has the following functions. (1) The flag bit is read from the intermediate data buffer to check whether it is necessary to add or delete data. (2) When it is necessary to delete data, delete data in units of bus width. When deletion is possible in units of bus width, deletion is performed in units of bus width. Data deletion can also be performed by moving the data on the packet data memory. However, from the viewpoint of speeding up the packet processing, the data to be deleted can be deleted in parallel with the process of writing the packet data to the packet data memory. It is desirable to achieve this by skipping data reading and reading data not subject to deletion. However, since data deletion is performed in units of bus width, when the data deletion length is not an integral multiple of the bus width of the bus 109, the data deletion position is the first on the bus 109 even if the data deletion length is an integer multiple of the bus width. Otherwise, data that cannot be deleted remains, but this data is deleted by the reorder unit 124. (3) When it is necessary to add data, (i) it is determined whether the packet data memory is sufficient from the size of the additional data in the intermediate data and the free capacity of the packet data memory. The back pressure signal line 92 is asserted for a clock time corresponding to an insufficient memory capacity. This is because, in the data addition processing, the same data is copied in units of the data bus width, and there is a possibility that the packet data memory will be insufficient. (ii) Data expansion is performed in units of bus width. Data decompression refers to securing an area to which data is added. Data decompression is performed multiple times in units of bus width (additional data size divided by data) at the additional position on the packet in parallel with the packet data memory write processing from the viewpoint of speeding up the packet processing. This is realized by reading the bus width (rounded up if there is a remainder). However, since data expansion is performed in units of bus width, when the data addition length is not an integral multiple of the bus width, and when the data addition position is not the head of the bus 109, an extra data area is secured beyond the data addition length. However, the reorder unit 124 deletes excess data.
[0043]
The reorder unit 124 has the following functions. (1) When data addition / deletion is not performed, the data read from the addition / deletion buffer 122 is output to the data write unit 128 as it is. (2) When adding / deleting data, data that has not been deleted by data deletion and extra data by data addition are deleted.
[0044]
FIG. 13 is a configuration diagram of the reorder unit 124 in FIG. The reorder unit 124 includes three stages of 128-bit shift registers 130 # 0, 130 # 1, and 130 # 2, a reorder control sequencer 132, and a selector 134 # i (i = 0 to 7). The shift register 130 # i is a register that shifts 128-bit packet data output from the buffer 122, and includes, for example, eight 16-bit registers 131 # ij (j = 0 to 7). The reason why the register 131 # ij is 16 bits is because the data unit for data addition / deletion is 16 bits here. The reason why the shift register 130 # i (i = 0 to 2) has three stages is that when 128-bit packet data is divided into 16 bits, it is expanded and contracted in units of 128 bits (k = 0 to 7). This is because the data overwritten on the 16th bit data is the 16th bit data after 14 at the maximum.
[0045]
The reorder control sequencer 132 has the following functions. (1) It is determined whether or not data addition / deletion is necessary from the flag bit of the intermediate data. (2) When there is no need to add / delete data, a selection signal = 0 is output to the selector 134 # i (i = 0 to 7) so as to select the 16-bit output of the register 131 # 0i. {Circle around (3)} When data needs to be added / deleted, (i) selector 134 # i (i = i = until the data required to delete unnecessary bits is output to the last shift register 130 # 0. The selection signal = 0 is output to 0-7). (ii) In a clock in which data that needs to delete unnecessary bits is output to the shift register 130 # 0 at the final stage, a selection signal = 0 is set to the selector 134 # i at the data position before the data to be deleted. Output. The data to be deleted means data to be deleted when data deletion is instructed and extra data by data decompression. When data is not deleted / added, the output data of the shift register 130 # 0i corresponds to the selector 134 # i. (iii) For the data after the deletion position, a selection signal is output to instruct the selection of data behind the deletion amount. For example, when 16 × k bits are deleted, the selection signal = k.
[0046]
The selector 134 # i receives the 16 × 15-bit output signal of the output signal of the shift register 131 # 0i and up to 14 shift registers, and the shift register 131 # when the selection signal = 0. When the output signal of 0i is selected and the selection signal = k (k ≠ 0), the signal output from the k-th subsequent register is selected. For example, the selector 134 # 0 receives the output signals of the register 131 # 0j (j = 0 to 7) and the register 131 # 1j (j = 0 to 6), and when 0 ≦ k ≦ 7, the register 131 # The output signal of 0k is selected, and when 8 ≦ k ≦ 14, the output signal of the shift register 131 # 1 (k−8) is selected.
[0047]
The write data extraction unit 126 in FIG. 12 determines whether or not data addition is necessary based on the flag bit. If data addition is necessary, the additional data is extracted from the intermediate buffer memory, and the data The data is output to the write unit 128. When data needs to be added, the data write unit 128 overwrites with the corresponding additional data when data requiring data addition is output from the reorder unit 124 in units of 128 bits. Hereinafter, the operation of the packet data processing apparatus 100 of FIG. 9 will be described.
[0048]
(1) Operation of receiving interface card 102 # i
The reception interface unit 70 # i and the pre-processing unit 72 # i in each reception interface card 102 # i operate in the same manner as in the first embodiment.
[0049]
(A) Determination of data addition / deletion
The packet data processors 110 # 1,..., 110 # B before the data addition / deletion mechanism unit 112 are packet processors 90 # 1,..., 110 before the packet data processor 90 # A in FIG. Processing similar to 90 # B is performed. Similar to the packet data processor 90 # B, the packet data processor 110 # B determines whether or not to perform processing for adding / deleting data to / from the packet based on the header of the packet. The related intermediate data is written to the intermediate data register 120 # B.
[0050]
(B) Operation of data addition / deletion mechanism unit 112
The data length check unit 120 obtains the total length of the data after data addition / deletion from the packet header and intermediate data, and checks whether the maximum length of the packet is exceeded. An error is output when the maximum packet length is exceeded. The decompression / deletion buffer 122 writes the packet data to the packet data memory and the intermediate data to the intermediate data memory. It is determined from the flag bit of the intermediate data whether it is necessary to add / delete data.
[0051]
(B-1) When there is no need to add or delete data
The expansion / contraction buffer 122 reads the packet data from the packet data memory and outputs it to the reorder unit 124. The shift register 130 # i (i = 2, 1, 0) in the reorder unit 124 shifts the packet data. The reorder control sequencer 132 outputs a selection signal = 0 to the selector 134 # i (i = 0 to 7). The selector 134 # i selects the data output from the shift register 131 # 0i and outputs it to the data write unit 128. The data write unit 128 outputs data output from the reorder unit 124.
[0052]
(B-2) When data needs to be added
The expansion / contraction buffer 122 determines whether the packet data memory is sufficient from the size of the additional data in the intermediate data and the free capacity of the packet memory. If the packet data memory is insufficient, the expansion / contraction buffer 122 sets the back pressure signal line 92 for the insufficient clock time. Assert. When the back pressure signal line 92 is asserted, the packet data processor group preceding the data addition / deletion mechanism unit 112 stops the shift operation and interrupts the instruction at the instruction position being executed. The expansion / contraction buffer 122 reads from the data memory up to data in units of bus width including the designated start position of the additional data. The data in the bus width unit including the additional data designation start position is copied the size of the additional data divided by the bus width (rounded up if there is a remainder) times.
[0053]
FIG. 14 is a diagram showing the decompression operation when the bus width is 128 bits, the size of the additional data is 64 bits, and the designated start position is 32 bits. In particular, FIG. 14 (a) shows the state before data decompression. FIG. 8B is a diagram showing a state after data expansion. As shown in FIG. 14A, when the data addition position is the 32nd bit, the expansion / contraction buffer 122 copies the 128-bit data included in the data addition position 64 ÷ 128 = 1 (rounding up the remainder) times. At this time, since 64 = (128−64) bits of extra data has been copied, this extra data is deleted from the reorder unit 124 as will be described later.
[0054]
The packet that has been expanded / contracted by the expansion / contraction buffer 122 is input to the reorder unit 124. The shift register 130 # i (i = 2, 1, 0) in the reorder unit 124 shifts the input packet data in synchronization with the clock. The reorder control sequencer 132 follows the designated start position indicated by the intermediate data until the data necessary to delete unnecessary bits is output to the shift register 130 # 0 at the final stage until the selector 134 # i (i = The selection signal = 0 is output to 0-7). In a clock in which data necessary to delete unnecessary bits is output to the last-stage shift register 130 # 0, the selection signal = 0 is output to the selector 134 # i at the data position before the deletion target data. For the back data including the data at the designated start position, a selection signal is output to instruct to select the back data by the deletion amount. Deletion bit number = (decompressed bit number−data addition bit number).
[0055]
FIG. 15 is a diagram showing the operation of the reorder unit 124 when data is added. In particular, FIG. 15A shows the input of the reorder unit 124 and FIG. 15B shows the output of the reorder unit 124. FIG. 15 shows the operation when the bus width is 128 bits, the size of the additional data is 64 bits, and the designated start position is 32 bits. Data length to be deleted = 128− (remainder of 64 ÷ 128) = 64 bits. Therefore, the deletion amount = 64 ÷ 16 = 4 words. The reorder unit 124 passes through the input data up to the data addition position data. Subsequent data including data at the data addition position selects and passes the data four words behind.
[0056]
The write data extraction unit 126 reads the additional data from the intermediate data and outputs it to the data write unit 128. The data write unit 128 overwrites the data from the data addition position with the additional data extracted from the intermediate data by the write data extraction unit 126.
[0057]
(B-3) When data needs to be deleted
The expansion / contraction buffer 122 contracts data in units of bus width. That is, first, data from the top data of a packet to data in a bus width unit including data at the deletion data start position is read from the bucket data memory. Next, the data in the bus width unit including the data at the deletion data final position is read from the packet data memory, and the data in the bus width unit before the data at the deletion data final position is read from the data in the bus width unit next to the data at the deletion data start position. By skipping the data, the data is contracted in units of bus width.
[0058]
FIG. 16 is a diagram showing data contraction in units of bus widths. In particular, FIG. 16A shows a state before data contraction, and FIG. 16B shows a state after data contraction. . The In FIG. 16, the bus width is 128 bits, the size of the deleted data is 160 bits, and the designated start position is 112 bits. When this packet data is shrunk in units of bus width, as shown in FIG. 16B, 128-bit data is deleted from the 128th bit.
[0059]
FIG. 17 is a diagram showing another case of data contraction in units of bus widths. In particular, FIG. 17A shows a state before data contraction, and FIG. 17B shows a state after data contraction. FIG. In FIG. 17, the bus width is 128 bits, the deleted data size is 160 bits, and the designated start position is 64 bits. As shown in FIG. 17A, even when the size of the deleted data exceeds 128 bits, the data may not be shrunk in units of bus width.
[0060]
The packet reduced in the bus width unit by the expansion / contraction buffer 122 is input to the reorder unit 124. The shift register 130 # i (i = 2, 1, 0) in the reorder unit 124 shifts the input packet data in synchronization with the clock. The reorder control sequencer 132 keeps the selector 134 # i (i = 0 to 7) until the data necessary to delete unnecessary bits is output to the final shift register 130 # 0 according to the designated start position. Select signal = 0 is output. In a clock in which data necessary to delete unnecessary bits is output to the last-stage shift register 130 # 0, the selection signal = 0 is output to the selector 134 # i at the data position before the deletion target data. For the back data including the data at the designated start position, a selection signal is output to instruct to select the back data by the deletion amount. Deleted bit amount = deleted data bit length−shrinkage bit length.
[0061]
FIG. 18 is a diagram showing the operation of the reorder unit 124 when deleting data. In particular, FIG. 18A shows the input of the reorder unit 124 and FIG. 18B shows the output of the reorder unit 124. FIG. 17 shows the operation when the bus width is 128 bits, the deleted data size is 160 bits, and the designated start position is 112 bits. The data length to be deleted is data of 160 ÷ 128 remainder = 32 bits from the designated start position. As shown in FIG. 17B, the data before the data deletion position is passed through the data output from the expansion / contraction buffer 122 data. For the following data including the data at the data deletion position, the data after 32 bits = 2 words (32 ÷ 16 = 2) is selected and passed.
[0062]
FIG. 19 is another diagram showing the operation of the reorder unit 124 in other cases when data is deleted. In particular, FIG. 19A shows the input of the reorder unit 124, and FIG. 19B shows the output of the reorder unit 124. Show. FIG. 19 shows the operation when the bus width is 128 bits, the size of the deleted data is 160 bits, and the designated start position is 64 bits. The data to be deleted is 160 + 128 remainder + 128 = 160 bits data from the designated start position. As shown in FIG. 19B, the data before the data deletion position is passed through the data output from the expansion / contraction buffer 122 data. For the subsequent data including the data at the data deletion position, the data after 160 bits = 10 words (160 ÷ 16 = 10) is selected and passed. The data write unit 128 passes through the deleted packet data.
[0063]
(C) Operation of subsequent packet data processing processor group
The packet data processor group 110 # C at the subsequent stage of the data adding / deleting mechanism unit 112 performs the same processing as the packet data processor 90 # C according to the first embodiment, and the packet data processor 110 # at the final stage. The packet is output from n to the switch fabric 64.
[0064]
(2) Operation of switch fabric 64
The switch fabric 64 inputs a packet from the reception interface card 62 # i (i = 1 to n), refers to the routing table according to the IP address or MAC address set in the packet header, and corresponds to the transmission interface. Route to card 66 # k (k = 1 to n). However, the routing table reference processing may be performed by the packet processor group 104 # i, and the switch fabric 64 may be routed to the transmission interface card 66 # k (k = 1 to n) determined according to the processing result.
[0065]
(3) Operation of transmission interface card 66 # i
The transmission interface card 66 # i receives a packet from the switch fabric 64 and transmits the packet according to the physical interface of the transmission path.
[0066]
As described above, as a special packet data processor, the packet data processor allows the data addition / deletion mechanism with a buffer function to perform data addition / deletion so that the data without worrying about the bus width can be obtained. Addition and deletion can be performed. Also, instead of stopping the data shift of the packet data processor group every time data is added, the data shift is stopped for the first time when there is no more free space in the buffer. Can be reduced.
[0067]
Third embodiment
FIG. 20 is a block diagram of a packet data processing apparatus according to the third embodiment of the present invention. Components that are substantially the same as those in FIG. 9 are given the same reference numerals. 20 is different from the packet data processor group 104 # i in FIG. 9 in the packet data processor group 144 # i in the reception interface card 142 # i. The packet data processor group 144 # i is provided with a buffer for storing packet data and intermediate data at the first stage, the back pressure signal is input only to the packet data processor at the first stage, and data addition / deletion The packet data processing processor group 104 in FIG. 9 continues the packet data processing group without stopping even when the data addition / deletion mechanism unit performs the data addition processing. Different from #i.
[0068]
FIG. 21 is a configuration diagram of the packet data processor group 144 # i in FIG. 20, and components that are substantially the same as those in FIG. 10 are given the same reference numerals. The buffer 150 has the following functions. (i) Input packet data and intermediate data in synchronization with the clock, and write them into the FIFO memory. (ii) The packet data and intermediate data held in the FIFO memory are read and output to the buses 108 and 109. (iii) When the back pressure signal line 92 is asserted, reading of packet data and intermediate data from the FIFO memory is stopped. While the reading from the FIFO memory is stopped, the packet data and the intermediate data are written. Therefore, in order to prevent the FIFO memory from being insufficient, the FIFO data is written according to the packet data to be written while the reading is stopped. Memory capacity is determined. (iv) When the back pressure signal line 92 is negated, reading of packet data and intermediate data from the FIFO memory is resumed.
[0069]
Since the back pressure signal line 92 is not input to the packet data processor 152 # i (i = 1 to B) before the data addition / deletion mechanism unit 154, the data addition / deletion mechanism unit 154 receives the data Packet processing is not stopped while the additional processing is executed. The data addition / deletion mechanism unit 154 is not different from the configuration of the data addition / deletion mechanism unit 112 shown in FIG. 12, and asserts the back pressure signal line 92 when the buffer 122 in FIG. However, since the back pressure signal line 92 is not input to the packet data processor 152 # i but is input to the buffer 150, the operation of the packet data processor 152 # i does not stop, so the packet data processor 152 # The packet data at i is input even while the back pressure signal line 92 is asserted.
[0070]
Therefore, when the back pressure signal line 92 is asserted, there is not enough free space in the buffer so that the expansion / contraction buffer configured as in FIG. 12 does not overflow even if all the packets in the packet data processor 152 # i are input. I must. By asserting the back pressure signal line 92, when sufficient space is generated in the expansion / contraction buffer, the data addition / deletion mechanism unit 154 negates the back pressure signal line 92 so as to restart the input of the packet to the buffer 150. Hereinafter, the operation of the packet data processing apparatus 140 of FIG. 20 will be described.
[0071]
(1) Operation of reception interface card 142 # i
The reception interface unit 70 # i and the pre-processing unit 72 # i in each reception interface card 142 # i operate in the same manner as in the first embodiment.
[0072]
(A) Writing / reading packet data
The buffer 150 inputs packet data and intermediate data in synchronization with the clock, and sequentially writes them into the FIFO memory. When the back pressure signal line 92 is negated, the packet data and intermediate data held in the FIFO memory are read and output to the packet data processor group at the next stage.
[0073]
(B) Determination of data addition / deletion
The packet data processors 152 # 1,..., 152 # B prior to the data addition / deletion mechanism unit 150 are packet processors 90 # 1,..., Upstream from the packet data processor 90 # A in FIG. Processing similar to 90 # C is performed. Similar to the packet data processor 90 # B, the packet data processor 152 # B determines whether or not to perform processing for adding / deleting data to / from the packet based on the header of the packet. Write the relevant intermediate data to the intermediate data register.
[0074]
(C) Operation of the data addition / deletion mechanism unit 154
The data addition / deletion mechanism unit 154 performs data addition / deletion processing similar to that of the second embodiment. When data expansion is performed, if the buffer configured similarly to the buffer 122 in FIG. 12 is likely to run out, the back pressure signal line 92 is asserted. At this time, since the back pressure signal line 92 is not input to the packet data processor 152 # i but is input to the buffer 150, the packet data processor 152 # i (i = 1, 2,..., B) Since the data is not stopped, the packet data in the packet data processor 152 # i (i = 1, 2,..., B) is not backed while the data addition / deletion mechanism unit 154 is asserting the back pressure signal line 92. Even while the pressure signal line 92 is asserted, the data addition / deletion mechanism unit 150 operates without stopping.
[0075]
The fact that the packet data processor 152 # i does not stop means that, for example, data is passed from the outside when two clocks have passed after execution of a certain instruction, and the packet data processor 152 # i performs processing based on that data. Since a certain process must be performed after a fixed clock from such a process, the packet data processor 152 # i cannot be stopped. Even in such a case, the packet data can be added. When the buffer 122 has enough space by asserting the back pressure signal line 92, the data adding / deleting mechanism unit 154 negates the back pressure signal line 92 to resume the input of the packet to the buffer 150. To do. In this embodiment, the buffer 150 corresponding to the back pressure is included in the packet data processor group 144 # i as a configuration. However, if the upstream processing unit 72 # i has a buffer, the upstream processing unit 72 # i may also function as the buffer 150.
[0076]
The present invention includes the following supplementary notes.
[0077]
(Supplementary note 1) In a packet data processing apparatus having a packet data processing group composed of a plurality of packet data processing units configured in a pipeline to process each input packet and output to the subsequent stage,
A data adding unit provided in a first packet data processing unit in the packet data processing group for adding the data to be added to an input packet;
While the data adding unit is performing the data adding process, the first packet data processing unit is instructed to stop outputting packets before the first packet data processing unit, and after the data adding process is completed, the first packet data A control unit instructing the output of the packet to be resumed at the front stage of the processing unit;
A packet data processing apparatus comprising:
[0078]
(Supplementary Note 2) The control unit instructs all the packet data processing units upstream of the first packet data processing unit to stop and restart the output of the packet, and the previous packet of the first packet data processing unit. The packet data processing apparatus according to appendix 1, wherein the data processing unit stops and restarts the output of the packet based on an instruction from the control unit.
[0079]
(Additional remark 3) The 2nd packet data processing part in the said packet data processing group of the front | former stage of the said 1st packet data processing part determines whether it is necessary to add data based on the input packet And an additional information generation unit that calculates additional data, additional data length, and additional position based on the input packet and outputs to the subsequent stage when the determination unit determines that data needs to be added. The packet data processing device according to appendix 1, wherein the data adding unit adds data based on the additional data, the additional data length, and the additional position.
[0080]
(Supplementary Note 4) The data adding unit includes a processor, a first shift register having a first number of stages having a first bit width for holding the packet, a second bit width for holding the additional data, the additional data length, and the additional position. A second shift register of the second number of stages, stopping the shift operation of the first shift register based on the additional data length and the predetermined register of the first shift register for packet data located behind the additional position 4. The packet data processing apparatus according to appendix 3, wherein data addition is performed by writing the additional data to the network.
[0081]
(Additional remark 5) In the packet data processing apparatus which has the packet data processing group comprised from the several packet data processing part by the pipeline structure which processes with respect to each input packet, and outputs to a back | latter stage,
A first memory having a predetermined data bus width provided in a first packet data processing unit in the packet data processing group;
Write the input packet to the first memory, read data from the beginning of the packet from the first memory, sequentially output the data bus width unit, and the data bus width unit data including the data at the additional position A memory control unit provided in the first packet data processing unit for repeatedly outputting based on the data addition length and the addition position;
Based on the data bus width, the additional position, and the additional data length, the data from the first data of the packet output from the first memory in units of data bus width to the additional position is output as it is, and the data is output from the additional position. For data after the additional data length, a reorder unit provided in the first packet data processing unit for selecting and outputting data after the data length to be deleted; and
A write unit provided in the first packet data processing unit for overwriting data at an additional position of a packet output from the reorder unit with additional data;
When the memory is insufficient, the front side of the first packet data processing unit is instructed to stop outputting the packet. When the memory is free, the front side of the first packet data processing unit A control unit for instructing to resume the output of the packet,
A packet data processing apparatus comprising:
[0082]
(Supplementary Note 6) A packet memory is further provided with a second memory that accumulates packet data in the previous stage of the packet data processing unit in the first stage of the packet data processing group and sequentially outputs from the head of the packet, and the control unit transmits the packet data to the second memory. The packet data processing device according to appendix 5, wherein the output is instructed to be stopped and restarted.
[0083]
【The invention's effect】
According to the present invention described above, it is also possible to take a technique of restricting packet input to a packet data processing unit preceding the packet data processing unit that performs processing for adding data to packet data when necessary. Thus, processing that increases the total length of the packet, such as addition of a header, is possible without impairing high-speed processing of the packet.
[Brief description of the drawings]
FIG. 1 is a principle diagram of the present invention.
FIG. 2 is a block diagram of a packet data processing apparatus according to the first embodiment of the present invention.
3 is a configuration diagram of a packet data processor group in FIG. 2;
4 is a block diagram of the packet data processor A in FIG. 3. FIG.
5 is a configuration diagram of a packet data processing processor B in FIG. 3;
FIG. 6 is a diagram showing a state of the packet data processor A after determination of data addition.
FIG. 7 is a diagram showing a state of the packet data processor A after two clocks.
FIG. 8 is a diagram illustrating a state of the packet data processor A after data movement.
FIG. 9 is a block diagram of a packet data processing apparatus according to a second embodiment of the present invention.
10 is a configuration diagram of a packet data processor group in FIG. 9;
11 is a configuration diagram of the packet data processing processor in FIG. 10;
12 is a configuration diagram of a data addition / deletion mechanism unit in FIG. 10;
13 is a configuration diagram of a reorder unit in FIG. 12. FIG.
FIG. 14 is a diagram illustrating a data expansion operation in units of bus width.
FIG. 15 is a diagram illustrating the operation of the reorder unit when data is added.
FIG. 16 is a diagram illustrating a data contraction operation in units of bus width.
FIG. 17 is a diagram illustrating a data contraction operation in units of bus width.
FIG. 18 is a diagram illustrating an operation of a reorder unit when data is deleted.
FIG. 19 is a diagram illustrating the operation of the reorder unit when data is deleted.
FIG. 20 is a block diagram of a packet data processing apparatus according to a third embodiment of the present invention.
FIG. 21 is a configuration diagram of the packet data processor group in FIG. 20;
FIG. 22 is a diagram illustrating a conventional store and forward packet processing method.
FIG. 23 is a block diagram of a packet data processing processor.
FIG. 24 is a diagram illustrating a hardware configuration in which a plurality of packet data processors are arranged.
FIG. 25 is a diagram showing a network configuration in which two private networks are connected by a shared network.
FIG. 26 is a diagram illustrating a state of a packet data processor before data addition / deletion;
FIG. 27 is a diagram illustrating a state of a shift register when packets are closely connected.
[Explanation of symbols]
50 # i (i = 1, 2,...) Packet data processing unit
50 # A first packet data processing unit
52 packet data processing group
54 Data addition part
56 Control unit

Claims (5)

In a packet data processing apparatus having a packet data processing group composed of a plurality of packet data processing units configured in a pipeline to process each input packet and output to the subsequent stage,
A data adding unit provided in a first packet data processing unit in the packet data processing group for adding data to an input packet;
When data is added to the input packet, the packet is output to the packet data processing unit upstream of the first packet data processing unit in order to secure at least the additional data length interval with the previous packet of the packet to be added A control unit that instructs the packet data processing unit in the previous stage of the first packet data processing unit to resume the output of the packet when the interval with the previous packet is secured,
A packet data processing apparatus comprising: A second packet data processing unit in the packet data processing group preceding the first packet data processing unit; a determination unit that determines whether or not data needs to be added based on an input packet; And an additional information generation unit that calculates additional data, additional data length, and additional position based on the input packet when the determination unit determines that data needs to be added, and outputs the calculated data to a subsequent stage. 2. The packet data processing apparatus according to claim 1, wherein the data adding unit adds data based on the additional data, an additional data length, and an additional position. The data adding unit includes a processor, a first shift register having a first stage number having a first bit width for holding the packet, a second stage number having a second bit width for holding the additional data, the additional data length, and the additional position. The shift operation of the first shift register for storing packet data located behind the additional position based on the additional data length is stopped, and the additional data is written to the first shift register. 3. The packet data processing apparatus according to claim 2, wherein the data is added by the processor executing the above. In a packet data processing apparatus having a packet data processing group composed of a plurality of packet data processing units configured in a pipeline to process each input packet and output to the subsequent stage,
A first memory having a predetermined data bus width provided in a first packet data processing unit in the packet data processing group;
Write the input packet to the first memory, read data from the beginning of the packet from the first memory, sequentially output the data bus width unit, and the data bus width unit data including the data at the additional position A memory control unit provided in the first packet data processing unit for repeatedly outputting based on the data addition length and the addition position;
Based on the data bus width, the additional position, and the additional data length, the data from the first data of the packet output from the first memory in units of data bus width to the additional position is output as it is, and from the additional position, For data after the additional data length, a reorder unit provided in the first packet data processing unit for selecting and outputting data after the data length to be deleted; and
A write unit provided in the first packet data processing unit for overwriting data at an additional position of a packet output from the reorder unit with additional data;
When there is not enough free space in the first memory, the first packet data processing unit is instructed to stop outputting packets, and when free space in the first memory is secured, the first packet data processing is performed. A control unit that instructs the upstream side of the unit to resume the output of the packet;
A packet data processing apparatus comprising: A second memory for accumulating packet data and sequentially outputting the packet data from the beginning of the packet is further provided in front of the first packet data processing unit of the packet data processing group, and the control unit stops outputting packets to the second memory. 5. The packet data processing apparatus according to claim 4, wherein a restart instruction is issued.

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