JP2002247095A - Packet data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet data processor capable of adding data to a packet without impairing a high speed processing of the packet. SOLUTION: The packet data processor having a packet data processing group to be constituted of a plurality of pipeline structured packet data processing parts each of which performs processing to inputted packets and outputs them to a rear stage respectively is provided with a data adding part provided in a first packet data processing part in the packet data processing group to add data to the inputted packets and a control part to instruct the packet data processing part at the previous stage of the first packet data processing part to stop the output of the packets in order to secure an interval between an object packet to be added and the previous packet at least for data length to be added when the data is added to the inputted packets and to instruct the packet data processing part at the previous stage of the first packet data processing part to restart the output of the packets when the interval with the previous packet is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipelined packet data processing apparatus for processing input packet data.

[0002]

2. Description of the Related Art At the time of performing packet communication between terminals, the most commonly used one at present is an IP (Interrupt).
net Protocol) network. In this IP network, a network node that relays between networks performs packet processing, such as header rewriting processing in a packet and searching and routing of a destination table provided in the apparatus, for the relay apparatus. With the recent increase in the speed of the Internet, a network node that relays a packet attempts to speed up the packet processing by performing the packet processing with dedicated hardware. Conventionally, there is a method in which a packet processing unit of a network node that relays a packet processes the packet by store and forward.

FIG. 22 is a diagram showing a conventional configuration of a store-and-forward system. In this configuration, the packet processing unit 2 configured by a general processor or dedicated hardware and the memory 4 are connected by the bus 6, and the packet processing unit 2 stores the necessary data of the packet stored in the memory 4. By performing the processing on this, the processing necessary for packet relay is performed. In the conventional packet processing by store and forward, the packet processing unit 2 performs processing on a packet stored in the memory 4 in accordance with a command of software prepared in advance. Therefore, in the packet processing, the processing to be performed on the packet can be easily changed later by rewriting the instruction of the software prepared in advance. Therefore, the processing contents can be changed later to revise the protocol or improve the service function provided as a network.

However, in this process, since the packet data is stored in the memory 4, a read / write operation to / from the memory 4 storing the packet data is required. The packet processor 2 gives the address of the memory to be read to the memory 4 and then reads data from the memory 4, or the packet processor 2 gives the memory 4 the address of the memory to which the packet processor 2 writes 4 is performed. At this time, the time when the packet processing unit 2 reads and writes data from the memory 4 after the processor gives the address to the memory 4 is considerably longer than the cycle time of the processor. For this reason, the overhead of the read / write processing to the memory 4 becomes a problem, and the packet processing cannot be performed at high speed.

Therefore, in recent years, a method of executing packet processing at high speed by a dedicated hardware circuit has been devised.
In a dedicated hardware circuit, packet processing can be performed with a high-speed hardware clock, so that packets can be processed at high speed. However, there is a problem that it is not possible to easily change the function for improving the function, and it is necessary to develop new hardware each time. By the way, when the network node processes the IP and lower layer protocols, it processes based on the information in each protocol header, and rarely needs the information in the data part of the IP. Hardware that performs high-speed processing can be considered by paying attention to the locality that this processing target is only each protocol header.

FIG. 23 is a diagram showing a packet data processor focusing on the locality of processing. The packet data processor 10 includes a general-purpose register 12, an arithmetic
And shift registers 16 and 18. In the packet data processor 10, a pipeline constituted by shift registers 16 and 18 for shifting packet data and information synchronized with the packet such as the result of an operation to be temporarily stored to the next stage for each clock, respectively. To be stored. In the packet data processor 10, processing to be performed on a packet is described in advance by software. The packet data processor 10 is activated when the head of the packet is input, and performs processing according to the description of software prepared in advance. The data in the registers 16 and 18 constituting each pipeline is shifted by the clock, and the packet data processor 10 performs the processing for a predetermined number of clocks. After the processing is completed, when the next packet is input, the same processing is performed on that packet.

FIG. 24 is a diagram showing a hardware configuration in which a plurality of packet processors are arranged. As shown in FIG. 24, in this hardware configuration, a plurality of packet processors 30 # i (i = 1 to n) are arranged. Each packet data processor arranged as shown in FIG. 24 performs each process, and completes the packet processing required by the network node as a whole. Processing a packet with such a processing system can be performed at high speed by using a pipelined register when packet processing has locality such as when processing extends only to the IP layer. The processing can be flexibly changed.

[0008]

On the other hand, there is an increasing need for multi-functional processing in network nodes.
In some of such processes, a new header needs to be added to a packet or unnecessary headers need to be deleted. For those that require such processing,
There is a tunneling process. The tunneling process is used, for example, when communication between two private networks is used via a shared network such as the Internet.

FIG. 25 is a network configuration diagram in which two private networks are connected by a shared network. In FIG. 25, a case is considered where communication is performed from private network 40 # A to private network 40 # B. Private network 4
The packet transmitted from 0 # A is added with a header for the shared network 42 (capsule processing) by a network node 44 # A connecting the private network 40 # A and the shared network 42 (encapsulation processing), and transmitted to the shared network 42 such as the Internet. You. Then, the network node 44 # B that connects the shared network 42 and another private network 40 # B that receives the packet is connected to the private network 4
When a packet sent from 0 # A is received, the header added at the time of the encapsulation processing is deleted (decapsulation processing), and the packet is returned to the packet before being subjected to the encapsulation processing, and the packet is transferred to another private network 40 # B An operation such as transmission is performed. Therefore, the network node 44 # that needs to perform the capsule processing / decapsulation processing
In A, 44 # B, it is necessary to perform the header addition / deletion operation as described above.

In the packet data processing system in which the processing is performed by paying attention to the locality of the packet processing, since the processing is performed by register access, the packet processing can be performed at a high speed. Since addition / deletion of a header is also performed by paying attention to the header, high-speed processing can be performed by using this processing method.

FIG. 26 is a diagram showing the state of the packet data processor before data addition / deletion. For example,
Consider a case where a packet is stored in the shift register 18 in the state shown in the figure. In FIG. 26, a hatched portion indicates a packet, and a packet header is stored in P2. At this time, if it is desired to delete the data at P0, the data at P2 and P1 are deleted at P1 and P0, respectively.
Should be overwritten. To add data between P0 and P1, the data in P1 and P2 are
2. It is sufficient to overwrite P3 and write the data to be added to P1. However, in the data addition processing, there is a problem because the total length of the packet after processing is longer than the packet before processing.

FIG. 27 is a diagram showing a state of the shift register when packets are close. In this packet data processing method, when packets are continuously input, packets are input one after another as shown in FIG. 27 and exist in the shift register 18 without any gap. If a packet is added in this state, data will be written on the packet processed before the packet, and the data of the previously processed packet will be destroyed. For example, when data of a previously processed packet is stored in P3, data in P2 is destroyed by data of a later packet. In order to avoid this, when a packet is input to the packet data processing group, by controlling so that a certain interval is provided between packets, data is not overwritten on a previously processed packet,
Data can be added. However, providing a constant interval between all the packets also results in an interval for packets that do not need to add data, which may reduce the throughput of processing.

As described above, a process for shortening the total length of a packet, such as deleting a packet, can be handled by a conventional packet data processor without any problem. However, if a conventional packet data processor performs a process in which the total length of a packet, such as adding a packet, is longer than the original total length, the processing efficiency is reduced.

The present invention has been made in view of the above, and an object of the present invention is to provide a packet data processing device capable of adding packet data without lowering processing efficiency.

[0015]

FIG. 1 is a diagram illustrating the principle of the present invention. As shown in FIG. 1, the bucket data processing device includes:
A packet data processing group 52 composed of a plurality of pipelined packet data processing units 50 # i (i = 1, 2,...) That process each input packet and output the processed packet to the subsequent stage. Have. The first packet data processing unit 50 # A in the packet data processing group 52 has a data adding unit 54 that adds data to an input packet. The packet data processing device includes a data adding unit 54
During the data addition processing, the first packet data processing unit 50 # A instructs the preceding stage to stop outputting the packet, and after the data addition processing is completed, the first packet data processing unit 50 # A A control unit 56 for instructing to restart the output of the packet before the #A is further provided.

When a packet is input to the packet data processing device, each packet data processing unit 50 # i (i = 1,
2,...) Perform predetermined processing on the packet. When the packet data processing group 52 or the control unit 56 provided separately from the packet data processing group 52 needs to add data to the packet, the interval between the packet to which the data is added and the previous packet is set to at least the data addition length. Packet data processing unit 50 # i (i = 1, 2,..., B) at the preceding stage of the first packet data processing unit 50 # A to secure
To stop the output of the packet data. The data adding unit 54 adds data to the packet when the data adding length is secured. Thus, the packet data processing group 52
Performs processing on the packet by pipeline processing, and when it is necessary to add data to the packet, it only temporarily stops the output of the packet data to the subsequent stage. You can make additions.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 2 is a block diagram of a packet data processing device according to the first embodiment of the present invention. The packet data processing device shown in FIG. 2 includes, for example, network nodes 44 # A and 44 # connecting private networks 40 # A and 40 # B of the network shown in FIG. 25 and a shared network 42 such as the Internet. B has been applied. As shown in FIG. 2, the packet data processing device 60
Represents a plurality of reception interface cards 62 # i (i = 1
To n), a switch fabric 64, and a plurality of transmission interface cards 66 # i (i = 1 to n). The receiving interface card 62 # i (i = 1 to n) has the following functions. The packet is received from a corresponding private network, for example, a LAN or a shared network. For the received packet, it is determined from the packet header whether or not it is necessary to perform the encapsulation / decapsulation processing. When it is necessary to perform the capsule processing / decapsulation processing, the capsule processing / decapsulation processing is performed. In addition, in the capsule processing, the data addition processing,
In the decapsulation process, a data deletion process is performed. The packet subjected to the capsule processing or the like is transferred to the switch fabric 64.
Output to

The receiving interface card 62 # i has a receiving interface unit 70 # i, a pre-processing unit 72 # i, and a packet data processor group 74 # i. The receiving interface unit 70 # i receives a packet according to the physical interface. The pre-processing unit 72 # i performs pre-processing such as packet header detection for the packet processing processor group 74 # i to add / delete data to / from the packet. The packet processing processor group 74 # i is configured such that a plurality of packet data processing processors are pipelined to perform processing on packets, and have, for example, the following functions. From the packet header, it is determined whether it is necessary to add or delete data to the packet. If it is determined that it is necessary to add data to the packet, the data to be added, the data length, and the position to be added on the packet are determined. If it is determined that data needs to be deleted from the packet, the data length to be deleted and the position to be deleted on the packet are obtained. The data is added / deleted based on the data length and the like obtained in the above steps. In the case of adding data, in order to secure at least the interval between the packet to be added and the previous packet by the additional data length, the packet processor at the preceding stage of the packet data processor performing the data adding process stops outputting the packet data and operates during the operation. Stop the operation of the packet data processor. When an interval corresponding to the length of the preceding packet and the additional data length is secured, the preceding packet processor restarts outputting the packet data and restarts the operation of the packet data processor that has stopped its operation. The packet length after the change by data addition / deletion is set in the packet header.

FIG. 3 is a configuration diagram of the packet data processor group 74 # i in FIG. As shown in FIG.
The packet processor group 74 # i includes a bus 88 for transferring intermediate data other than packets, a bus 89 for transferring packets, and a plurality of packet data processors 90 # i (i = 1
To n) and a back pressure signal line 92. The buses 88 and 89 are data buses for transferring intermediate data and packets. The packet data processor 90 # i (i = 1 to n) holds the intermediate data and the packet data input from the buses 88 and 89 in its own shift register and performs a predetermined process on the packet. . The number of stages is set arbitrarily according to the contents of the entire packet processing.

Packet data processor 90 # A
Performs addition / deletion of data according to an instruction from the packet data processor group at the preceding stage. Specifically, the following processing is performed. It is determined whether the packet needs to add or delete data according to the instruction of the packet data processor group at the preceding stage. When it is necessary to add data to the packet, the position of the additional data and the additional data are specified based on the instruction of the packet processor group at the preceding stage, and the data adding process is performed. Based on the additional data length, the back pressure signal line 92 is asserted for the number of clocks corresponding to the additional data length, and the operation of the packet data processor group preceding the packet data processor is stopped. When you need to delete data,
Based on an instruction from the packet processor group at the preceding stage, the position of the deleted data and the length of the deleted data are specified, and the data is deleted. Incidentally, the packet data processor 90 # i in the preceding stage of the packet data processor 90 # A
The operation stop / restart control for (i = 1, 2, B,...) May be performed by a control unit independent of the packet data processor group. Also, during the period when the back pressure signal line 92 is asserted and the operation of the packet data processor group is stopped, the preceding stage (the former stage processing unit 72 # i in the configuration of FIG. 2) temporarily stops the data transfer according to the back pressure. Stop.

FIG. 4 is a configuration diagram of the packet data processor 90 # A in FIG. As shown in FIG. 4, the packet data processor 90 # A includes a general-purpose register 93 # A, a computing unit 94 # A, and an intermediate data register 96 #.
A and a packet access register 98 # A. The general-purpose register 93 # A is, for example, eight 32-bit registers r0 to r7. Arithmetic unit 94 # A is a processor that performs an operation in accordance with an instruction code described in a program, and when data is added, asserts back pressure signal line 92 for a period corresponding to the additional data length. The intermediate data register 96 # A is, for example, a 16-stage 32-bit shift register register e0 to e15 for holding and transmitting a processing result regarding the packet data in synchronization with the packet data. The data held in the intermediate data register 96 # A includes, for example, data indicating the beginning of a packet, a flag bit indicating whether data addition / deletion is necessary, additional data, additional data position, additional data length, and deletion data. Position and length of deleted data. The packet access register 98 # A is, for example, a 16-stage 32-bit shift register register p0 to p15 for directly taking in packet data.

The packet data processor 90 # B upstream of the packet data processor 90 # A
The following processing is performed. It is determined whether or not it is necessary to perform processing for adding / deleting data to the packet from the packet header. If it is determined that it is necessary to add data to the packet, the data to be added, the data length, and the position to be added on the packet are determined. If it is determined that data is to be deleted from the packet, the length of the data to be deleted and the position on the packet to be deleted are obtained. The intermediate data obtained by is output on the data bus. When the back pressure signal line 92 is asserted, the shift operation of the packet data and the intermediate data is stopped, and if the packet processing is being performed, the processing is stopped.
When the back pressure signal line 92 is negated, the shift operation of the packet data and the intermediate data is restarted and the stopped processing is restarted.

FIG. 5 is a configuration diagram of the packet data processor 90 # B in FIG. When the back pressure signal line 92 is asserted, the packet data processor 90 # B stops the system clock based on, for example, the back pressure signal, so that the arithmetic unit 94 # B, the intermediate data register 96 # B, The operation of the packet access register 98 # B is stopped. General-purpose register 93 # B, arithmetic unit 94 # B, intermediate data register 96
#B and the packet access register 98 # B are substantially the same as those in FIG. Packet processor 90 # at the preceding stage of packet data processor 90 # A
The configuration of i (i = 1, 2,...) is substantially the same as that of the packet data processor 90 # B. The configuration of the packet processor 90 # C at the subsequent stage of the packet data processor 90 # A is substantially the same as that of the packet data processor 90 # B except that the operation does not need to be stopped according to the back pressure signal line 92. For example, when data addition / deletion is performed according to the intermediate data, the packet length information in the packet header is updated.

The switch fabric 64 shown in FIG. 2 receives a packet from the receiving interface card 62 # i (i = 1 to n) and stores a routing table in accordance with the IP address or MAC address set in the header of the packet. The routing is performed with reference to the corresponding transmission interface card 66 # k (k = 1 to n). However,
The routing table reference processing is performed by the packet processing processor group 74 # i, and the switch fabric 64 determines the transmission interface card 6 determined according to the processing result.
6 # k (k = 1 to n) may be implemented. The transmission interface card 66 # i has a transmission interface unit 80 # i. Transmission interface unit 8
0 # i receives a packet from the switch fabric 64 and transmits the packet according to the physical interface of the transmission path. Hereinafter, the packet data processing device 50 of FIG.
The operation of will be described.

(1) Receive interface card 62 #
Operation of i The reception interface unit 70 # i in each reception interface card 62 # i receives the packet data from the transmission line according to a predetermined physical interface, and
Output the packet data to 2 # i. Pre-processing unit 72 #
i performs serial / parallel conversion of packet data to 32-bit parallel data, and outputs the result to a data bus connected to the packet access register 96 # 1. The packet header is detected and a flag indicating the header is output to the data bus connected to the intermediate data register 96 # 1 in synchronization with the packet. Packet data processor group 74 #
i, each packet data processor 90 # j (j =
1, 2,...), When the packet is stored in the packet access register 98 # j, the intermediate data register 96 # j
Performs each processing on the packet according to the intermediate data stored in the packet. Further, the packet processing processor group 7
Data output is stopped during the period when back pressure is notified from 4 # i by the back pressure signal.

(A) Determination of Data Addition / Deletion The packet data processor 90 # B determines whether or not to perform processing for adding / deleting data to a packet from the header of the packet. If it is determined that data is to be added to the packet, the data to be added, the data length, and the position on the packet to be added are determined. If it is determined that data is to be deleted from the packet, the length of the data to be deleted and the position on the packet to be deleted are obtained. Flag bit indicating whether or not to add / delete, data to be added, data to be added, data length to be added, position in packet to add, data to be deleted, data length to be deleted, data to be deleted The position of the data on the packet is synchronized with the packet and the intermediate data register 96
Write to #B. The packet data and the intermediate data are synchronized with the clock and the packet processor group 74 # i
The data is transferred by a packet access register, an intermediate data register, and a data bus.

(B) Packet data processor 9
Operation of 0 # A The packet data processor 90 # A is activated when a packet is input to the packet access register 98 # A. If the packet is the packet access register 98 # A
When the packet is input to the intermediate data register 96 # A in synchronization with the packet, the flag bit determines whether data addition / deletion is necessary for the packet according to the instruction of the preceding packet data processor. When the addition is necessary from the flag bit, the data to be added, the additional data length, and the addition position on the packet are obtained from the intermediate data register 96 # A. If deletion is necessary, the length of the deleted data and the position of the deletion on the packet are obtained from the intermediate data register 96 # A. Here, it is assumed that an instruction has been given to add 64-bit data to the 32nd bit from the beginning of the packet.

(B-1) Addition of Data FIG. 6 is a diagram showing the packet data processor 90 # A after data addition is determined. It is assumed that the leading data of the packet to which data is to be added is stored in the register P3 of the packet access register 98 # A. It is also assumed that the last data of the previous packet of this packet is stored in the register P4. Packet data processor 90
#A asserts the back pressure signal line 92 for the clock time corresponding to the additional data length and makes the packet to which the data is to be added to the packet data processor in the preceding stage so as not to shift the packet access register. The shift operation of the stored packet access register 98 # A is stopped. The shift operation is performed on the register of the packet access register 98 # A in which the packet before the data addition target packet is stored. Here, since the head of the data addition target packet is stored in the register P3 of the packet access register 98 # A, the shift operation of the registers P3-P0 is stopped. On the other hand, the shift operation of the registers P4 to P15 continues.

On the other hand, the packet data processor 90
#A packet data processor 90 # in the preceding stage
When the back pressure signal line 92 is asserted, i (i = 1, 2, B,...) stops the operation of the operation unit, the packet access register, and the intermediate data register.
For example, the system clock is negated. here,
Since the size of the additional data is 64 bits and the packet access register 98 # A is 32 bits, the data transfer of the packet to which data is added and the subsequent packet data is stopped for 64 ÷ 32 = 2 clocks. The previous packet data must continue the data transfer. Therefore, the transfer of the packet data after the register P3 is stopped for two clocks, and the transfer of the packet data before the data of the register P4 is continuously performed.

FIG. 7 is a diagram showing the packet data processor 90 # A after two clocks. As shown in FIG. 7, after two clocks, vacancies are secured in the registers P4 and P3 of the 32nd bit from the head of the packet where data is to be added. Then, the packet data processor 9 that has determined that the two clocks must be stopped
The packet access register 98 # A 0 # A can restart the packet shift after two clocks have elapsed.
Is resumed, the back pressure signal line 92 is negated, and the packet data processor 9
It instructs the packet data processor located before 0 # A to resume the shift. When the back pressure signal line 92 is negated, the packet data processor preceding the packet data processor 90 # A restarts the shift operation. The packet data processor that has interrupted the instruction resumes the interrupted instruction. The packet data processor 90 # A moves by the additional data length from the packet head data stored in the packet access register 98 # A to the data immediately before the position where data is to be added. After that, the data to be added stored in the intermediate data register 96 # A is stored in the register of the packet access register 98 # A at the position to be added. Then, the data of the intermediate data register 96 # A synchronized with the packet also moves as necessary.

FIG. 8 shows the state of packet data processor 90 # A after data movement. Here, since it is added to the 32nd bit from the head of the packet,
The data of the register P3 in which the 32-bit data before the second bit is stored is shifted by 64 bits.
That is, the data in the register P3 is moved to the register P5. Then, a 64-bit vacant place, register P3,
The additional data stored in the intermediate data register 96 # A is added to P4. The added packet is transferred to the subsequent packet data processor group by the shift operation of the packet access register 98 # A.

(B-2) Data Deletion If deletion is necessary from the flag bit, the length of the deleted data and the position of deletion on the packet are set in the intermediate data register 9.
6 Get from #A. For the packet to be deleted, data before the deletion position stored in the packet access register 98 # A is moved to the rear of the deletion data length. For example, when the deletion position on the packet is the 32nd bit from the packet head, the deletion data length is 64 bits, and the packet head is stored in the register P3, the 32-bit data stored in the register P3 is moved by 64 bits. That is, it moves to the register P1. At this time, the data of the intermediate data register 96 # A synchronized with the packet also moves as necessary. The deleted packet is transferred to the subsequent packet data processor group by the shift operation of the packet access register 98 # A.

(C) Packet data processor 9
Operation of the Packet Data Processor Group at the Subsequent Stage of 0 # A
Receiving the packet data and the intermediate data from 89,
When packet processing, for example, data addition / deletion by the packet data processor 90 # A, the header length of the packet is updated, and the packet data processor 90 # C at the last stage switches the switch fabric 6
4 is output.

(2) Operation of Switch Fabric 64 The switch fabric 64 receives a packet from the receiving interface card 62 # i (i = 1 to n), and sets the IP address or MA set in the header of the packet.
According to the C address, referring to the routing table, the corresponding transmission interface card 66 # k (k = 1 to
n). However, the routing table reference processing is performed for the packet processing processor group 74 # i, and the switch fabric 64 determines the transmission interface card 66 # k (k = 1 to k) determined according to the processing result.
An implementation for routing to n) may be used.

(3) Transmission interface card 66 #
Operation of i The transmission interface card 66 # i receives a packet from the switch fabric 64 and transmits the packet according to the physical interface of the transmission path.

As described above, the packet data processor group determines whether data addition / deletion is necessary for a packet, and generates data required for addition / deletion. The packet data processor A receives such data,
Determine whether it is necessary to add a packet interval by data addition processing, and if necessary, have the packet data processing processor group at the preceding stage limit the input of packets to determine from the size of the data to be added. The data addition process can be performed without increasing the packet interval and without lowering the throughput of the packet processing.

Second Embodiment FIG. 9 is a block diagram of a packet data processing apparatus according to a second embodiment of the present invention. Components that are substantially the same as those shown in FIG. are doing. In the packet data processing device 100 shown in FIG. 9, the packet data processing processor group 104 # i in the receiving interface card 104 # i is different from the packet data processing processor group 74 # i in FIG. Packet data processor group 1
04 # i indicates that addition / deletion of data can be performed even when the data length of the addition / deletion data is not a multiple of the bit width of the packet access register of the packet data processor. A buffer memory for holding intermediate data is provided so that the shift operation is not always stopped when data is added, but is stopped only when the buffer becomes insufficient due to data addition in FIG. This is different from the packet data processor group 74 # i.

FIG. 10 is a configuration diagram of the packet data processor group 104 # i in FIG. 9, and the same reference numerals are given to the same components as those in FIG. The buses 108 and 109 and the packet data processor 110 # i have the bit widths of the buses 108 and 109 and the packet access register and the intermediate data register in FIG. And the packet data processor 90 # i.

FIG. 11 is a block diagram of the packet data processor 110 # i shown in FIG. 10, and substantially the same components as those in FIG. 5 are denoted by the same reference numerals. The intermediate data register 120 # i is, for example, a 4-stage 64-bit shift register register e0 to e3 for holding and transmitting a processing result regarding the packet data in synchronization with the packet data. The packet access registers 122 # i are, for example, four-stage 128-bit shift register registers p0 to p3 for directly taking in packet data. Data addition / deletion mechanism 1
Reference numeral 12 denotes a packet data processor 90 # in FIG.
Data addition / deletion is performed in the same manner as in A. The data addition / deletion mechanism unit 112 is configured by, for example, dedicated hardware.

FIG. 12 is a block diagram of the data addition / deletion mechanism 112 in FIG. As shown in FIG. 12, the data addition / deletion mechanism unit 112 includes a data length check unit 12
0, an expansion / contraction buffer 122, a reorder unit 124, a write data extraction unit 126, and a data write unit 128. The data length check unit 120 calculates the total length of the data after data addition / deletion from the packet data and the intermediate data,
Check that the maximum allowed packet length is not exceeded. If it exceeds, an error is output.

The expansion / contraction buffer 122 includes a packet data memory and an intermediate data memory for storing packet data and intermediate data, and a controller for controlling these memories. Each memory is FIFO (First
In First Out) buffer. The packet data memory is a FIFO consisting of a memory area having the same data bit width as the packet access register 122 # i, for example, a 128-bit width. The intermediate data buffer has the same data bit width as the intermediate data register 120 # i, for example, 6 bits.
It is a 4-bit wide FIFO.

The controller has the following functions. The flag bit is read from the intermediate data buffer to check whether data addition / deletion is necessary. When it is necessary to delete data, the data is deleted in units of bus width. If deletion is possible in units of bus width, deletion is performed in units of bus width. Data deletion can also be performed by moving data on the packet data memory. However, from the viewpoint of speeding up packet processing, the data to be deleted can be deleted in parallel with the writing of packet data to the packet data memory. It is desirable to skip reading data and read data that is not targeted for deletion.
However, since data is deleted in units of the bus width, if the data deletion length is not an integral multiple of the bus width of the bus 109, the data deletion position is the first position on the bus 109 even if the data deletion length is an integral multiple of the bus width. Otherwise, data that cannot be deleted remains, but this data is deleted by the reorder unit 124. If it is necessary to add data, (i) judge whether the packet data memory is sufficient based on the size of the additional data in the intermediate data and the free space of the packet data memory. The back pressure signal line 92 is asserted for a clock time corresponding to the capacity. In the data addition process, the same data is copied in data bus width units.
This is because the packet data memory may be insufficient. (ii) Data expansion is performed in bus width units. Data expansion refers to securing an area to which data is added. From the viewpoint of speeding up the packet processing, the data decompression is performed a plurality of times (in the size of the additional data ÷ This is realized by reading the bus width (rounded up if there is a remainder). However, since data decompression is performed in units of a bus width, when the data addition length is not an integral multiple of the bus width, when the data addition position is not at the head of the bus 109, an extra data area exceeding the data addition length is secured. However, the extra data is deleted by the reorder unit 124.

The reorder section 124 has the following functions.
When data addition / deletion is not performed, the data read from the addition / deletion buffer 122 is output to the data write unit 128 as it is. When data is added or deleted, data that has not been deleted by data deletion and excess data by data addition are deleted.

FIG. 13 is a configuration diagram of the reorder section 124 in FIG. The reorder unit 124 includes three stages of 128-bit shift registers 130 # 0, 130 # 1, and 130 #.
2. Reorder control sequencer 132 and selector 134
#I (i = 0 to 7). Shift register 130 #
i is a register for shifting the packet data of 128 bits width output from the buffer 122, for example, 8
16-bit registers 131 # ij (j = 0 to 7)
Consists of The reason why the register 131 # ij is 16 bits is that the data unit of data addition / deletion is 1 here.
This is because it has 6 bits. Shift register 130
The reason why #i (i = 0 to 2) is set to three stages is that when the 128-bit packet data is divided by 16 bits, it expands and contracts in 128-bit units.
This is because the data to be overwritten with the 6-bit data is 16-bit data that is at most 14 bits later.

The reorder control sequencer 132 has the following functions. It is determined from the flag bits of the intermediate data whether data addition / deletion is necessary. When there is no need to add / delete data, the selector 134 # i (i =
0-7), the selection signal = 0 is output so as to select the 16-bit output of the register 131 # 0i. When it is necessary to add / delete data, (i) the selector 134 # i (i = 0 to 7) until the data which needs to delete unnecessary bits is output to the final stage shift register 130 # 0. )
Output a selection signal = 0. (ii) The data for which unnecessary bits need to be deleted is stored in the shift register 130 at the last stage.
With the clock output to # 0, the selection signal = 0 is output to the selector 134 # i at the data position before the data to be deleted. The data to be deleted refers to data to be deleted when data deletion is instructed and extra data due to data expansion. When data is not deleted or added,
Output data of shift register 130 # 0i and selector 1
34 # i. (iii) For data behind the deletion position, a selection signal instructing to select data behind by the amount of deletion is output. For example, when deleting 16 × k bits, the selection signal = k.

The selector 134 # i is connected to the shift register 1
When the output signal of 31 # 0i and the output signal of 16 × 15 bits of the output signals of up to 14 shift registers are input and the selection signal = 0, the shift register 131 #
An output signal of 0i is selected, and when the selection signal = k (k ≠ 0), a signal output from the kth subsequent register is selected. For example, the selector 134 # 0
# 0j (j = 0 to 7) and the register 131 # 1j (j =
0-6), and when 0 ≦ k ≦ 7,
The output signal of the register 131 # 0k is selected, and 8 ≦ k ≦ 1
At 4, the output signal of the shift register 131 # 1 (k-8) is selected.

The write data extraction unit 126 in FIG. 12 determines whether data addition is necessary based on the flag bit, and if data addition is necessary, extracts the additional data from the intermediate buffer memory. Output to the data write unit 128. When data addition is required, when data requiring data addition is output from the reorder unit 124 in 128-bit units, the data writing unit 128 overwrites the data with the corresponding additional data. Hereinafter, the operation of the packet data processing device 100 of FIG. 9 will be described.

(1) Receive interface card 102
Operation of #i The reception interface unit 70 # i and the pre-processing unit 72 # i in each reception interface card 102 # i operate in the same manner as in the first embodiment.

(A) Judgment of data addition / deletion Packet data processing processors 110 # 1,..., 110 # B at a stage prior to the data addition / deletion mechanism 112 are transmitted from the packet data processing processor 90 # A in FIG. , 90 # B perform the same processing as the previous packet processing processors 90 # 1,..., 90 # B. Packet data processing processor 11
0 # B, as in the packet data processor 90 # B, determines from the header of the packet whether or not to perform processing for adding / deleting data to the packet, and determines intermediate data related to data addition / deletion. Intermediate data register 12
Write to 0 # B.

(B) Operation of the data addition / deletion mechanism 112 The data length checker 120 obtains the total length of the data after data addition / deletion from the packet header and the intermediate data.
Check that the maximum packet length is not exceeded. Output an error when the maximum packet length is exceeded. The decompression / deletion buffer 122 writes the packet data to the packet data memory and the intermediate data to the intermediate data memory.
It is determined from the flag bits of the intermediate data whether data addition / deletion is necessary.

(B-1) When it is not necessary to add / delete data The expansion / contraction buffer 122 reads out packet data from the packet data memory and outputs it to the reorder unit 124.
Shift register 130 #i (i =
2, 1, 0) shifts the packet data. The reorder control sequencer 132 sets the selection signal = 0 to the selector 1
34 # i (i = 0 to 7). Selector 134 #
i selects the data output from the shift register 131 # 0i and outputs it to the data write unit 128. The data write unit 128 outputs data output from the reorder unit 124.

(B-2) When Data Addition is Necessary The expansion / contraction buffer 122 judges whether or not the packet data memory is sufficient based on the size of the additional data in the intermediate data and the free space of the packet memory. In this case, the back pressure signal line 92 is asserted for the insufficient clock time. Back pressure signal line 92
Is asserted, the packet data processor group prior to the data addition / deletion mechanism 112 stops the shift operation and interrupts the instruction at the instruction position being executed. The expansion / contraction buffer 122 reads data from the data memory up to data in units of a bus width including the designated start position of additional data. The data in the unit of the bus width including the start position for specifying the additional data is copied times the size of the additional data divided by the bus width (rounded up if there is a remainder).

FIG. 14 is a diagram showing the expansion operation when the bus width is 128 bits, the size of the additional data is 64 bits, and the designated start position is 32 bits. In particular, FIG. (B) is a diagram showing a state after data expansion. As shown in FIG. 14A, when the data addition position is the 32nd bit, the expansion / contraction buffer 122 copies the 128-bit data included in the data addition position 64 ÷ 128 = 1 (the remainder is rounded up) times.
At this time, since the data has been copied by 64 = (128-64) bits extra, the reorder unit 1 will be described later.
24, this extra data is deleted.

The packet expanded and contracted by the expansion and contraction buffer 122 is input to the reorder unit 124. Reorder part 12
4 shift register 130 # i (i = 2, 1, 0)
Shifts input packet data in synchronization with a clock. The reorder control sequencer 132 keeps selecting the selector 134 # i until the data whose unnecessary bits need to be deleted is output to the final-stage shift register 130 # 0 in accordance with the designated start position indicated by the intermediate data.
A selection signal = 0 is output to (i = 0 to 7). In the clock in which the data whose unnecessary bits need to be deleted is output to the shift register 130 # 0 at the last stage, the selection signal = 0 is output to the selector 134 # i at the data position before the data to be deleted. For the subsequent data including the data at the designated start position, a selection signal instructing to select the subsequent data by the amount of deletion is output. Number of deleted bits =
(The number of decompressed bits−the number of additional data bits).

FIG. 15 shows the reorder unit 12 when data is added.
4A and 4B show the operation of the reorder unit 124, and FIG. 4B shows the input of the reorder unit 124, and FIG. FIG. 15 shows the operation when the bus width is 128 bits, the size of the additional data is 64 bits, and the designated start position is 32 bits. Data length to be deleted = 12
8- (the remainder at 64 ÷ 128) = 64 bits. Therefore, the amount of deletion = 64/16 = 4 words. The reorder unit 124 passes the input data up to the data at the data addition position. Subsequent data including the data at the data addition position selects and passes data four words behind.

The write data extracting section 126 reads out the additional data from the intermediate data and outputs it to the data write section 128. The data write unit 128 includes the write data extraction unit 12
In step 6, the data from the data addition position is overwritten with the additional data extracted from the intermediate data.

(B-3) When Data Deletion is Needed The expansion / contraction buffer 122 contracts data in bus width units. That is, first, the data from the head data of the packet to the data in the unit of the bus width including the data at the start position of the deleted data is read from the bucket data memory. Next, the data in the bus width unit including the data at the end position of the deleted data is read from the packet data memory, and the data in the bus width unit next to the data at the start position of the deletion data is read from the data in the bus width unit before the data at the end position of the deletion data. By skipping to the data, the data is contracted in units of the bus width.

FIGS. 16A and 16B are diagrams showing the contraction of data in units of a bus width. In particular, FIG. 16A shows a state before data contraction, and FIG. 16B shows a state after data contraction. FIG. You. In FIG. 16, the bus width is 128 bits, the size of the deletion data is 160 bits, and the designation start position is 112 bits. When this packet data is shrunk in units of bus width, as shown in FIG.
28-bit data is deleted.

FIGS. 17A and 17B are diagrams showing another case of contraction of data in units of bus width. FIG. 17A shows a state before data contraction, and FIG. 17B shows a state after data contraction. It is a figure showing the state of. In FIG. 17, the bus width is 128 bits, the size of the deletion data is 160 bits, and the designated start position is 64 bits.
Is a bit. As shown in FIG. 17A, even when the size of the deleted data exceeds 128 bits, there are cases where the data cannot be contracted in units of the bus width.

The packet reduced in the unit of the bus width by the expansion / contraction buffer 122 is input to the reorder unit 124. Shift register 130 # i in the reorder section 124 (i = 2,
1, 0) shifts the input packet data in synchronization with the clock. The reorder control sequencer 132
The selection signal = 0 is output to the selector 134 # i (i = 0 to 7) until data requiring unnecessary bits to be deleted is output to the final-stage shift register 130 # 0 according to the designated start position. I do. In the clock in which the data whose unnecessary bits need to be deleted is output to the shift register 130 # 0 at the last stage, the selection signal = 0 is output to the selector 134 # i at the data position before the data to be deleted. For the subsequent data including the data at the designated start position, a selection signal instructing to select the subsequent data by the amount of deletion is output. Deletion bit amount = deletion data bit length−reduction bit length.

FIG. 18 shows the reorder unit 12 when data is deleted.
4A and 4B show the operation of the reorder unit 124, and FIG. 4B shows the input of the reorder unit 124, and FIG. In FIG. 17, the bus width is 128 bits, the size of the deleted data is 160 bits, and the designated start position is 112 bits.
The operation at the time of a bit is shown. The data length to be deleted is the remainder of 160 ÷ 128 = 32 bits of data from the designated start position. As shown in FIG. 17B, for the data before the data deletion position, the expansion buffer 122
The data output from the data is passed through. For the subsequent data including the data at the data deletion position, 32
The data after the bit = 2 words (32/16 = 2) is selected and passed.

FIG. 19 shows the reorder section 12 when data is deleted.
4 is another diagram showing the operation in another case, in particular, FIG. 4A shows the input of the reorder unit 124, and FIG. 4B shows the output of the reorder unit 124. FIG. 19 shows the operation when the bus width is 128 bits, the size of the deletion data is 160 bits, and the designated start position is 64 bits. The data to be deleted is the data of 160 ＝ 128 remainder + 128 = 160 bits from the designated start position. FIG.
As shown in (b), for the data before the data deletion position, the data output from the expansion / contraction buffer 122 data is passed through. For the subsequent data including the data at the data deletion position, 160 bits = 10 words (1
60 ÷ 16 = 10) Select and pass the subsequent data. The data write unit 128 passes the deleted packet data through.

(C) Operation of Subsequent Packet Data Processor Group The subsequent packet data processor group 110 # C... Of the data addition / deletion mechanism 112 is the same as the packet data processor 90 # C of the first embodiment. To the final stage of the packet data processor 110 # n
The packet is output to the switch fabric 64.

(2) Operation of Switch Fabric 64 The switch fabric 64 receives a packet from the receiving interface card 62 # i (i = 1 to n), and sets the IP address or MA set in the header of the packet.
According to the C address, referring to the routing table, the corresponding transmission interface card 66 # k (k = 1 to
n). However, the routing table reference processing is performed by the packet processing processor group 104 # i, and the switch fabric 64 determines the transmission interface card 66 # k (k = 1 to k) determined according to the processing result.
An implementation for routing to n) may be used.

(3) Transmission interface card 66 #
Operation of i The transmission interface card 66 # i receives a packet from the switch fabric 64 and transmits the packet according to the physical interface of the transmission path.

As described above, as a special packet data processor,
By causing a data addition / deletion mechanism having a buffer function to perform addition / deletion of data, data addition / deletion can be performed regardless of the bus width. Also, instead of stopping the shift of data in the packet data processor group each time data is added, the shift of data is stopped only when the free space in the buffer is exhausted, thereby reducing the number of times the pipeline is stopped. Can be reduced.

Third Embodiment FIG. 20 is a block diagram of a packet data processing apparatus according to a third embodiment of the present invention. Components that are substantially the same as those shown in FIG. are doing. In the packet data processing device 140 shown in FIG. 20, a packet data processor group 144 # i in the receiving interface card 142 # i is different from the packet data processor group 104 # i in FIG. The packet data processor group 144 # i has a buffer for storing packet data and intermediate data at the first stage, a back pressure signal is input only to the first stage packet data processor, and data addition / deletion. The packet data processor group 104 in FIG. 9 can continue without stopping the packet data processing even when the data addition / deletion mechanism unit is performing data addition processing. Different from #i.

FIG. 21 is a block diagram of the packet data processor group 144 # i in FIG. 20. Components that are substantially the same as those in FIG. 10 are given the same reference numerals. The buffer 150 has the following functions. (i) The packet data and the intermediate data are input in synchronization with the clock, and written into the FIFO memory. (ii) The packet data and the intermediate data held in the FIFO memory are read and output to the buses 108 and 109. (iii) When the back pressure signal line 92 is asserted, reading of packet data and intermediate data from the FIFO memory is stopped. Since the packet data and the intermediate data are written even while the reading from the FIFO memory is stopped, the FIFO memory is controlled according to the packet data written while the reading is stopped so as not to run out of the FIFO memory. The memory capacity is determined. (iv) When the back pressure signal line 92 is negated, reading of packet data and intermediate data from the FIFO memory is restarted.

The packet data processor 152 # i (i = 1 to 1) at a stage prior to the data addition / deletion mechanism 154
In B), since the back pressure signal line 92 is not input, the packet processing does not stop even while the data addition / deletion mechanism unit 154 is executing the data addition processing. The data addition / deletion mechanism 154 does not differ from the configuration of the data addition / deletion mechanism 112 shown in FIG. 12, and asserts the back pressure signal line 92 when the buffer 122 in FIG. However, the back pressure signal line 92 is not input to the packet data processor
0, the packet data processor 1
Since the operation of 52 # i does not stop, the packet data in the packet data processor 152 # i is also input while the back pressure signal line 92 is being asserted.

Therefore, when the back pressure signal line 92 is asserted, the packet data processor 152
Even if all the packets in #i are input, there must be enough free space in the buffer that does not overflow the expandable buffer configured as in FIG. By asserting the back pressure signal line 92, the data addition / deletion mechanism 154 is provided when a sufficient space is generated in the expansion / contraction buffer.
Negates the back pressure signal line 92 to restart the input of the packet to the buffer 150. Hereinafter, FIG.
The operation of the packet data processing device 140 of 0 will be described.

(1) Receiving interface card 142
Operation of #i The reception interface unit 70 # i and the pre-processing unit 72 # i in each reception interface card 142 # i operate in the same manner as in the first embodiment.

(A) Writing / reading of packet data The buffer 150 receives the packet data and the intermediate data in synchronization with the clock and sequentially writes the data into the FIFO memory. When the back pressure signal line 92 is negated, the packet data and the intermediate data held in the FIFO memory are read and output to the packet data processor group at the next stage.

(B) Judgment of Data Addition / Deletion Packet data processors 152 # 1,..., 152 # B at a stage prior to the data addition / deletion mechanism 150 are transmitted from the packet data processor 90 # A in FIG. , 90 # C perform the same processing as that of the preceding packet processor 90 # 1,. Packet data processor 15
2 # B, similarly to the packet data processor 90 # B, determines whether or not to perform processing for adding / deleting data to a packet from the header of the packet, and determines intermediate data related to data addition / deletion. Write to the intermediate data register.

(C) Operation of the data addition / deletion mechanism 154 The data addition / deletion mechanism 154 performs the same data addition / deletion processing as in the second embodiment. At the time of data expansion, if the buffer configured similarly to the buffer 122 in FIG.
Assert 2. At this time, since the back pressure signal line 92 is not input to the packet data processor 152 # i but is input to the buffer 150, the packet data processor 152 # i (i = 1, 2,...,
Since B) does not stop, the data addition / deletion mechanism unit 154
Also asserts the back pressure signal line 92 while the packet data processor 152 # i (i =
The packet data in (1, 2,..., B) is added with data while the back pressure signal line 92 is asserted.
The deletion mechanism 150 operates without stopping.

Packet data processor 152 # i
Does not stop, for example, after executing an instruction,
Since data is passed from the outside when the clock passes, certain processing must be performed after a fixed clock from certain processing such as processing performed by the packet data processor 152 # i based on the data. Processor 152 # i cannot be stopped. In such a case, the packet data can be added. Then, by asserting the back pressure signal line 92, when a sufficient space is generated in the buffer 122, the data addition / deletion mechanism unit 154 causes the buffer 150
Then, the back pressure signal line 92 is negated in order to restart the input of the packet. In this embodiment, the buffer 150 corresponding to the back pressure is included in the packet data processor group 144 # i as a configuration. However, if the pre-processing unit 72 # i has a buffer, the pre-processing unit 72 # i may also have the function of the buffer 150.

The present invention includes the following supplementary notes.

(Supplementary Note 1) In a packet data processing apparatus having a packet data processing group composed of a plurality of packet data processing units having a pipeline configuration, each of which processes an input packet and outputs the processed packet to a subsequent stage. A data addition unit provided in a first packet data processing unit in the packet data processing group for adding the data to be added to an input packet; and a data addition unit performing data addition processing. , Instructing the preceding stage of the first packet data processing unit to stop outputting packets,
A packet data processing device, comprising: a control unit for instructing to restart outputting a packet at a stage preceding the first packet data processing unit after the data adding unit ends the data adding process.

(Supplementary Note 2) The control unit instructs all of the packet data processing units preceding the first packet data processing unit to stop and restart the output of the packet. The packet data processing device according to claim 1, wherein the packet data processing unit at the preceding stage stops and restarts the output of the packet based on an instruction from the control unit.

(Supplementary Note 3) The second packet data processing unit in the packet data processing group preceding the first packet data processing unit determines whether it is necessary to add data based on the input packet. A determining unit for determining, when the determining unit determines that it is necessary to add data,
An additional information generation unit that calculates additional data, an additional data length and an additional position based on the input packet, and outputs the additional data to a subsequent stage, wherein the data adding unit includes the additional data, the additional data length and The packet data processing device according to claim 1, wherein data is added based on the addition position.

(Supplementary Note 4) The data adding unit includes a processor, a first shift register having a first number of stages having a first bit width to hold the packet, a second data to hold the additional data, the additional data length, and the additional position. A second shift register having a second stage number of 2 bits, and stopping packet operation of the first shift register based on the additional data length and stopping the shift operation of the first shift register based on the additional data length; 4. The packet data processing device according to claim 3, wherein the data addition is performed by writing the additional data to a predetermined register.

(Supplementary Note 5) In a packet data processing apparatus having a packet data processing group composed of a plurality of packet data processing units having a pipeline structure, each of which processes an input packet and outputs the processed packet to a subsequent stage. Writing a first memory of a predetermined data bus width provided in a first packet data processing unit in the packet data processing group and an input packet to the first memory;
Data is read from the first memory from the beginning of the packet and sequentially output in the data bus width unit, and the data in the data bus width unit including the data at the addition position is repeated based on the data addition length and the addition position. A memory control unit provided in the first packet data processing unit for outputting a packet output from the first memory in data bus width units based on the data bus width, the additional position, and the additional data length. For the data from the leading data to the additional position, the data is output as it is, and for the data after the additional data length from the additional position, the first packet data that selects and outputs the data that is the data length to be deleted is output. Adds the data at the reordering unit provided in the processing unit and the position where the packet output from the reordering unit is added A write unit provided in the first packet data processing unit for overwriting with the data, and instructing a preceding stage of the first packet data processing unit to stop outputting a packet when the memory becomes insufficient. A packet data processing device, comprising: a control unit for instructing a stage preceding the first packet data processing unit to restart packet output when the memory space is secured.

(Supplementary Note 6) A second memory for accumulating packet data at a stage preceding the packet data processing unit at the first stage of the packet data processing group and sequentially outputting the packet data from the beginning of the packet is further provided. Supplementary note 5 characterized by instructing the memory to stop and restart packet output.
The packet data processing device as described in the above.

[0083]

According to the present invention described above, a method for restricting the input of a packet to a packet data processing unit prior to a packet data processing unit for performing a process of adding data to packet data when necessary. By doing so, processing that increases the total length of the packet, such as adding a header, is possible without impairing the high-speed processing of the packet.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a packet data processing device according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a packet data processing processor group in FIG. 2;

4 is a configuration diagram of a packet data processor A in FIG. 3;

FIG. 5 is a configuration diagram of a packet data processor B in FIG. 3;

FIG. 6 is a diagram showing a state of the packet data processor A after data addition is determined;

FIG. 7 is a diagram showing a state of the packet data processor A after two clocks.

FIG. 8 is a diagram showing a state of the packet data processor A after data movement.

FIG. 9 is a configuration diagram of a packet data processing device according to a second embodiment of the present invention.

FIG. 10 is a configuration diagram of a packet data processing processor group in FIG. 9;

FIG. 11 is a configuration diagram of a packet data processor in FIG. 10;

12 is a configuration diagram of a data addition / deletion mechanism unit in FIG.

13 is a configuration diagram of a reorder unit in FIG.

FIG. 14 is a diagram illustrating a data decompression operation in units of a bus width.

FIG. 15 is a diagram illustrating the operation of the reorder unit when data is added.

FIG. 16 is a diagram illustrating a data contraction operation in units of a bus width.

FIG. 17 is a diagram illustrating a data contraction operation in units of a bus width.

FIG. 18 is a diagram illustrating the operation of the reorder unit when data is deleted.

FIG. 19 is a diagram illustrating the operation of the reorder unit when data is deleted.

FIG. 20 is a configuration diagram of a packet data processing device according to a third embodiment of the present invention.

FIG. 21 is a configuration diagram of a packet data processing processor group in FIG. 20;

FIG. 22 is a diagram showing a conventional packet processing method based on store and forward.

FIG. 23 is a configuration diagram of a packet data processing processor.

FIG. 24 is a diagram illustrating a hardware configuration in which a plurality of packet data processors are arranged.

FIG. 25 is a diagram showing a network configuration in which two private networks are connected by a shared network.

FIG. 26 is a diagram illustrating a state of the packet data processor before data addition and deletion;

FIG. 27 is a diagram illustrating a state of a shift register when packets are close to each other.

[Explanation of symbols]

 50 # i (i = 1, 2,...) Packet data processing unit 50 # A First packet data processing unit 52 Packet data processing group 54 Data addition unit 56 Control unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Abiru 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yuji Kojima 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 F-term in Fujitsu Limited (reference) 5K030 GA01 HA08 JA05 KA13 KX04 KX12 KX13 LE11 MB11

Claims (5)

[Claims] 1. A packet data processing apparatus having a packet data processing group including a plurality of pipelined packet data processing units for processing input packets and outputting the processed packets to a subsequent stage. A data adding unit provided in the first packet data processing unit in the packet data processing group for adding data to the input packet, and a data adding unit for adding data to the input packet. In order to secure the interval at least for the additional data length, the packet data processing unit in the preceding stage of the first packet data processing unit is instructed to stop outputting the packet. A control unit for instructing the packet data processing unit preceding the packet data processing unit to restart outputting the packet; A packet data processing device comprising: 2. A second packet data processing unit in the packet data processing group preceding the first packet data processing unit determines whether data needs to be added based on an input packet. A determination unit, and when the determination unit determines that it is necessary to add data, calculates an additional data, an additional data length and an additional position based on the input packet, and outputs an additional information to a subsequent stage. 2. The packet data processing apparatus according to claim 1, further comprising: a data adding unit that adds data based on the additional data, the additional data length, and the additional position. 3. The data adding unit includes a processor, a first shift register having a first bit width and a first number of stages for holding the packet, a second bit for holding the additional data, the additional data length, and the additional position. A second shift register having a second number of stages having a width, the shift operation of the first shift register storing packet data located after the additional position being stopped based on the additional data length, and the first shift register 3. The packet data processing device according to claim 2, wherein data addition is performed by the processor performing writing of the additional data. 4. A packet data processing device having a packet data processing group composed of a plurality of packet data processing units having a pipeline configuration, each of which processes an input packet and outputs the processed packet to a subsequent stage, A first memory having a predetermined data bus width provided in a first packet data processing unit in a packet data processing group; an input packet written to the first memory; and data read from the first memory from the beginning of the packet The first packet data processing unit is configured to sequentially output the data in the data bus width unit and repeatedly output the data in the data bus width unit including the data at the addition position based on the data addition length and the addition position. The memory control unit based on the data bus width, the additional position, and the additional data length. The data from the head data of the packet output from one memory in data bus width units to the additional position is output as it is, and the data after the additional data length from the additional position is shifted by the data length to be deleted. A reorder unit provided in the first packet data processing unit for selecting and outputting the data of the first packet data unit; and a first packet data processing unit for overwriting data at an addition position of a packet output from the reorder unit with additional data And a write unit provided in the first memory, when the first memory becomes insufficient,
Control for instructing the previous stage of the packet data processing unit to stop outputting the packet, and instructing the previous stage of the first packet data processing unit to restart the output of the packet when the space in the first memory is secured. A packet data processing device, comprising: 5. A second memory for accumulating packet data and sequentially outputting the packet data from the beginning of the packet is further provided before the first packet data processing unit of the packet data processing group,
The packet data processing device according to claim 4, wherein the control unit instructs the second memory to stop and restart the output of the packet.