JP4183550B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

[Industrial application fields]
The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.
[Prior art]
In recent years, flash memories are often used as semiconductor memories used in flash memory systems such as memory cards and silicon disks. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.
By the way, a NAND flash memory that is often used in the above-described device is a memory cell when a memory cell is changed from an erased state (logic value = 1) to a written state (logic value = 0). However, when the memory cell is changed from the written state (0) to the erased state (1), it cannot be performed in units of the memory cell, and a predetermined erase unit composed of a plurality of memory cells. This can only be done in (block). Such a batch erase operation is generally called “block erase”.
Due to the above characteristics, in a device using a NAND flash memory, when data is written, a block erased area is searched and new data is written in the detected empty area. . In addition, since the block which is an erasure unit is composed of a plurality of pages (for example, 32 pages), even when only the data of one page is rewritten, other blocks including the page are included. All the data of the page must be written again in the area where the block is erased. Therefore, in an apparatus using a NAND flash memory, an inter-block transfer process in which data of a block in which data is written is rewritten to another block frequently occurs.
[Problems to be solved by the invention]
The above block transfer process and the data write process in response to an instruction from the host computer to which the flash memory system is installed are more efficient when processed separately, but the power is unexpectedly cut off, etc. In consideration of this, there is a case where the inter-block transfer process must be interrupted during the data write process in accordance with an instruction from the host computer.
Accordingly, the present invention provides a memory controller capable of interrupting inter-block transfer processing in the middle of data write processing while suppressing a decrease in efficiency of inter-block transfer processing and data write processing, and a flash memory including the memory controller It is an object of the present invention to provide a system and a flash memory control method.
[Means for Solving the Problems]
An object of the present invention is to provide a plurality of buffers for holding data to be written to the flash memory or data to be read from the flash memory,
A first detection function for detecting a full or empty state of the buffer;
A second detection function for detecting a request for inter-block transfer processing,
When a request for inter-block transfer processing is detected by the second detection function,
Stop the writing process from the buffer to the flash memory,
Furthermore, when it is detected by the first detection function that the buffers are all full,
While stopping the process of taking the data to be written into the flash memory into the buffer,
Start the writing process from the buffer to the flash memory,
Furthermore, when it is detected by the first detection function that all the buffers are in an empty state,
While performing an inter-block transfer process using the buffer,
It is achieved by a flash memory system comprising a memory controller and a memory controller configured to start a process of fetching data to be written to a flash memory in the buffer that is not used in the inter-block transfer process .
And a third detection function for detecting the end of the inter-block transfer process.
When the end of inter-block transfer processing is detected by the third detection function,
While starting the process of taking data to be written to the flash memory into the buffer used in the inter-block transfer process,
By being configured to start the writing process from the buffer to the flash memory, it is possible to obtain a better effect (suppression of a decrease in processing efficiency).
The purpose of the present invention is to detect a request for interblock transfer processing.
Stop writing to the flash memory from a plurality of buffers holding data to be written to the flash memory or data to be read from the flash memory,
Furthermore, when it is detected that all the buffers are full,
While stopping the process of taking the data to be written into the flash memory into the buffer,
Start the writing process from the buffer to the flash memory,
Furthermore, when it is detected that all the buffers are empty,
While performing an inter-block transfer process using the buffer,
This is achieved by a flash memory control method which starts a process of fetching data to be written into the flash memory into the buffer which is not used in the inter-block transfer process.
Furthermore, when the end of the inter-block transfer process is detected,
While starting the process of taking data to be written to the flash memory into the buffer used in the inter-block transfer process,
By starting the writing process from the buffer to the flash memory, it is possible to obtain a better effect (suppression of a decrease in processing efficiency).
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. This flash memory system 1 is generally stored in a PC card, a compact flash (registered trademark of SanDisk Corporation), or the like. Yes. As shown in the figure, the flash memory system 1 includes a flash memory 2 and a controller 3.
The PC card conforms to the PCMCIA (Personal Computer Memory Card Association) standard, and the compact flash conforms to the CFA (Compact Flash Association) standard. The present invention also includes "SmartMedia (registered trademark of Toshiba Corporation)" of SSFDC Forum, "MMC (MultiMedia Card)" proposed by MultiMedia Card Association, and "Memory Stick (trademark of Sony Corporation)" proposed by Sony Corporation. It is also possible to apply the present invention to "
The PC card or compact flash in which the flash memory system 1 is housed is normally used by being detachably attached to the host computer 4 and used as a kind of external storage device for the host computer 4 as a pair. Examples of the host computer 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.
The flash memory 2 shown in FIG. 1 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block consists of 32 pages, and one page consists of a 512-byte user area and 16 pages. Each page is composed of 512 bytes when viewed from the host computer 4 side.
[Description of controller 3]
1 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block. 11 and a flash sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.
The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.
The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.
The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host computer 4 under the control of the microprocessor 6.
In other words, when the flash memory system 1 is mounted on the host computer 4, the flash memory system 1 and the host computer 4 are connected to each other via the external bus 13. Data supplied to the host computer is taken into the controller 3 through the host interface block 7 as an entrance, and data etc. supplied from the flash memory system 1 to the host computer 4 through the host interface block 7 as an exit 4 is supplied.
The host interface block 7 further includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host computer 4 and an error register (not shown) set when an error occurs. ) Etc.
The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block including a plurality of SRAM cells.
The buffer 9 is a functional block that temporarily accumulates data read from the flash memory 2 and data to be written to the flash memory 2. That is, read from the flash memory 2
Data is held in the buffer 9 until the host computer 4 can receive data, and data to be written to the flash memory 2 is held in the buffer 9 until the flash memory 2 becomes writable.
Here, the buffer 9 includes two FIFO (first-in first-out) structure buffers (hereinafter, one FIFO structure buffer is referred to as FIFO-A, and the other is referred to as FIFO-B). By using them alternately, the time required for writing data to the flash memory 2 or reading data from the flash memory 2 is shortened.
For example, when data is written to the flash memory 2, data sent from the host computer 4 is sequentially taken into the FIFO-A and FIFO-B via the host interface block 7.
Here, data is preferentially taken into the FIFO structure buffer that has become empty first (hereinafter, the empty FIFO structure buffer is called empty). On the other hand, the data taken into the FIFO-A and FIFO-B is sequentially sent to the flash memory 2 via the flash memory interface block 10. Here, the data in the FIFO structure buffer that has been full first (hereinafter, the state in which the FIFO structure buffer is fully loaded with data) is preferentially sent to the flash memory 2.
When data is fetched until the FIFO structure buffer becomes full, a full flag is set in a flag register (not shown) indicating the state. Also, when all the data fetched in the FIFO structure buffer is sent and the FIFO structure buffer becomes empty, an empty flag is set in a flag register (not shown).
The flash memory interface block 10 is a functional block that exchanges data, address information, status information, and internal command information with the flash memory 2 via the internal bus 14. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host computer 4 to the flash memory system 1.
The ECC block 11 generates an error correction code to be added to data to be written in the flash memory 2, and detects and corrects an error included in the read data based on the error correction code added to the read data. It is a functional block.
The flash sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on an internal command. The flash sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing internal commands in the plurality of registers is set under the control of the microprocessor 6. When information necessary for executing the internal command is set in the plurality of registers, the flash sequencer block 12 executes the internal command based on the information.
[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.
FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory 2. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series within the memory cell array 7.
The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.
In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, the P-type semiconductor between the source diffusion region 18 and the drain diffusion region 19 when the read voltage is not applied to the control gate electrode 23. A channel is not formed on the surface of the substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. And the drain diffusion region 19 are electrically connected by this channel.
That is, in the “erased state”, when no read voltage is applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the read voltage is applied to the control gate electrode 23. In this state, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.
FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, the source diffusion region 18, the drain diffusion region 19, and the like regardless of whether or not the read voltage is applied to the control gate electrode 23. A channel 24 is formed on the surface of the P-type semiconductor substrate 17 therebetween. Therefore, in the “write state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not the read voltage is applied to the control gate electrode 23. Become.
Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the memory cell array 7. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if this serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.
When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when the flash memory cell 16 in the written state is changed to the erased state, a high voltage that causes the control gate electrode 23 to be on the low potential side is applied and accumulated in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.
[Description of flash memory structure]
Next, the memory structure of the flash memory 2 will be described. FIG. 4 is a diagram schematically showing the memory structure of the flash memory 2. As shown in FIG. 4, the flash memory 2 includes “pages” that are access units for reading and writing data and “blocks” that are data erasing units.
The “page” is composed of a 512-byte user area 25 and a 16-byte redundant area 26. The user area 25 is an area for storing user data supplied from the host computer 4, and the redundant area 26 is an area for storing additional information such as an error correction code generated by the ECC block 11. The error collection code is additional information for correcting an error included in the data stored in the corresponding user area 25. If the error included in the data stored in the user area 25 is equal to or less than a predetermined number, It is used to correct this and obtain correct data.
In the redundant area 26, “erase flag” and “corresponding logical block address” are stored in addition to the error correction code. The “erase flag” is a flag indicating whether or not the block is an erased block. The “corresponding logical block address” is the logical block address of the block when data is stored in the block. It shows whether it corresponds to. Whether or not the “corresponding logical block address” is stored without providing the “erase flag” determines whether or not the block is an erased block (the “corresponding logical block address” is stored). If not, it is determined that the block is an erased block).
The “block” is composed of 32 “pages”. Here, since the flash memory cannot overwrite data, even when only the data of one “page” is rewritten, all the data of 32 “pages” of “block” including the “page” is written. Must be written again to the “block” where all the “page” data has been erased.
Here, when accessing a specific “page”, the lower 5 bits (when “block” is composed of 32 “pages”) of the host address, the page address, and the remaining higher bits are the block address Then, the block address is used to specify “block”, and the page address is used to specify “page” (page 0 to page 31) included in the specified “block”.
[Description of logical block address and physical block address]
As described above, since the flash memory cannot overwrite data, in order to write new data different from this to a “page” in which data has already been written, once the already written data is erased, a new data is written. A process of writing data is required. At this time, since the erasure is processed in units of blocks, when trying to erase the data of the “page” to which new data is written, all the “page” data of the “block” including the “page” is erased. End up. Therefore, when rewriting data that has already been written to a certain "page", the data for all the other pages of the "block" that contains the "page" to be rewritten is also written to the "page" to be rewritten. It is necessary to move to the erased block.
When rewriting data as described above, the data after rewriting is written in a “block” that is different from the “block” before rewriting. Therefore, the block address based on the host address (hereinafter, the block address based on the host address is logically expressed). And the block address in the flash memory 2 corresponding to the logical block address (hereinafter, the block address in the flash memory 2 is referred to as a physical block address). It changes dynamically every time it is rewritten. For this reason, an address conversion table in which the correspondence between the logical block address and the physical block address is written is required.
The “address conversion table” is a table showing the correspondence between “logical block address” and “physical block address”, and is stored in the work area 8 shown in FIG. In the “address conversion table”, for each of the reasons described above, each time the data written in the flash memory 2 is rewritten, the correspondence relationship of the portion related to the rewrite is updated.
[Description of write queue]
FIG. 5 is a schematic diagram showing a data structure of the write queue 28 stored in the work area 8 shown in FIG.
As shown in FIG. 5, the write queue 28 includes eight queues including queue 0 to queue 7, and physical block addresses are stored in each queue. Here, the physical block address of the erased block is stored in each queue. Therefore, the write queue 28 can hold physical block addresses of up to eight erased blocks. The write queue 28 detects an erased block with reference to the “erase flag” or “corresponding logical block address” stored in the redundant area 26 shown in FIG. 4, and stores the physical block address of the detected block in the queue 0. Store in queue 7
[Initial setting operation]
An initial setting operation of the flash memory system 1 shown in FIG. 1 will be described. This initial setting operation is executed when the flash memory system 1 is mounted on the host computer 4 or when a reset instruction is issued by the host computer 4.
In this initial setting operation, creation of the address conversion table and the write queue 28 shown in FIG. 5 is started under the control of the microprocessor 6, and when the creation is completed, the initial setting operation ends.
Note that while the initial setting operation of the flash memory system 1 is being performed, the controller 3 is in a busy state, and an instruction to read or write data from the host computer 4 is rejected. The busy state is canceled when the initial setting operation of the flash memory system 1 is completed.
[Description of processing according to the present invention]
Hereinafter, the process will be described with reference to FIG. 6 showing a flowchart of the process according to the present invention.
In the following processing, the flow of processing when interrupt processing between blocks is interrupted during the processing of writing data to a plurality of pages in accordance with the data writing instruction from the host computer 4 will be described. Here, inter-block transfer is a process of copying data written in a page of a specific block to a corresponding page of another erased block. In this process, data written in a page of a specific block is once read into a FIFO structure buffer (FIFO-A or FIFO-B), and the read data is written into a corresponding page in another erased block. It is crowded.
Note that, at the start of the flowchart shown in FIG. 6, the operation setting register included in the host interface control block 5 is given priority to FIFO-A and FIFO-B sequentially (FIFO structure buffer that is empty first). This order is referred to as FO order.) An operation mode for fetching data (hereinafter, an operation mode for fetching data in FIFO order in FIFO-A and FIFO-B is referred to as a 2-buffer mode) is set. On the other hand, under the control of the microprocessor 6, a write sequencer (to be described later) is sequentially set to a register (not shown) included in the flash sequencer block 12, and taken into FIFO-A and FIFO-B based on this setting. The data stored in the flash memory 2 is sequentially written (priority is given to the FIFO structure buffer that has become full first. This order is hereinafter referred to as FI order).
Step 1:
After completion of the currently executed process (data writing process to the flash memory 2), no new setting is performed for a register (not shown) included in the flash sequencer block 12. Accordingly, a new internal command is not executed after the currently executed process is completed.
Step 2:
After completion of the currently executed process, the process waits for FIFO-A and FIFO-B to become full, that is, waits for the full flag to be set, and proceeds to step 3 after the full flag is set. Here, since the host interface block 7 operates in the 2-buffer mode, data sent from the host computer 4 is taken into the FIFO-A and FIFO-B in the FO order. Therefore, after completion of the currently executed process, FIFO-A and FIFO-B become full, and a full flag is set in a flag register (not shown) of the buffer 9.
Step 3:
An operation mode for stopping the process of fetching data into the FIFO-A and FIFO-B in the operation setting register of the host interface control block 5 (hereinafter, the process of stopping the process of fetching data into the FIFO-A and FIFO-B) Mode is called stop mode).
Step 4:
Under the control of the microprocessor 6, the following write sequencer is set for a register (not shown) of the flash sequencer block 12.
1) An internal write command is set in a predetermined register (not shown) in the flash sequencer block 12 as an internal command.
2) The physical address corresponding to the write destination page and the number of pages to be written are set in a predetermined register (not shown) in the flash sequencer block 12. Here, the physical address corresponding to the write destination page is generated by adding the page address portion of the logical address to the physical block address of the erased block read from the write queue 28 shown in FIG. Further, since the data to be written into the flash memory 2 is data already taken into the FIFO-A and FIFO-B, 2 is set as the number of pages.
Next, the flash sequencer block 12 executes an internal command based on the setting of the write sequencer. When this internal command is executed, information for executing the internal command is supplied from the flash memory interface block 10 to the flash memory 2 via the internal bus 14. As a result, the data taken into FIFO-A and FIFO-B is written into the flash memory 2 in the FI order. The physical address of the write destination is automatically incremented (addition process for the page) according to the number of pages to be written. Therefore, if the write destination physical address of the data to be written first is A0, The write destination physical address of the data to be written from is A0 + 1. The same processing is performed when the number of pages is 3 or more.
Step 5:
The process waits for FIFO-A and FIFO-B to become empty, that is, waits for the empty flag to be set, and proceeds to step 6 after the empty flag is set. Here, since the host interface block 7 is in the stop mode, new data is not taken into the FIFO-A and FIFO-B. Therefore, FIFO-A and FIFO-B become empty after the processing currently being executed, and an empty flag is set in a flag register (not shown) of buffer 9. In step 4, the write sequencer may be set so that FIFO-A and FIFO-B become empty when the process is completed, and the process may proceed to step 6 after the process is completed. Here, when the data writing process is completed, a flag indicating that the process is completed is set in a register (not shown) of the flash sequencer block 12. Therefore, it is possible to detect the completion of the data writing process with this flag.
Step 6:
A new sequencer for writing is not set for a register (not shown) included in the flash sequencer block 12. Therefore, after the write process in step 4 is completed, a new internal write command is not executed.
Step 7:
Under the control of the microprocessor 6, the following transfer sequencer is set in a register (not shown) of the flash sequencer block 12.
1) An internal transfer command is set in a predetermined register (not shown) in the flash sequencer block 12 as an internal command.
2) The physical addresses of the transfer source and transfer destination and the number of pages to be transferred are set in a predetermined register (not shown) in the flash sequencer block 12. Here, the transfer destination physical address is generated by adding the page address portion of the transfer source physical address to the physical block address of the erased block read from the write queue 28 shown in FIG. Also, FIFO-B is selected as the FIFO structure buffer used for inter-block transfer. Here, the FIFO structure buffer used for inter-block transfer is not particularly limited.
Next, the flash sequencer block 12 executes an internal command based on the setting of the write sequencer. When this internal command is executed, information for executing the internal command is supplied from the flash memory interface block 10 to the flash memory 2 via the internal bus 14. As a result, the data written in the transfer source page is taken into the FIFO-B, and then the data taken into the FIFO-B is written into the transfer destination page.
The physical addresses of the transfer source and transfer destination are automatically incremented (addition process for pages) according to the number of pages to be transferred. Therefore, the physical address of the transfer source that is transferred first is A1, the transfer destination The physical address of the transfer source that is transferred second is A1 + 1, and the physical address of the transfer destination is A2 + 1. The same processing is performed when the number of pages is 3 or more.
Step 8:
After starting the inter-block transfer process in step 7, the operation setting register provided in the host interface control block 5 is an operation mode in which data is fetched only in FIFO-A (hereinafter referred to as an operation mode in which data is fetched only in FIFO-A). 1 buffer mode) is set. As a result, the operation mode of the host interface block 7 is switched from the stop mode to the 1 buffer mode, and the data sent from the host computer 4 is taken into the FIFO-A. The switching to the 1-buffer mode may be performed before the interblock transfer process in step 7 is started.
Step 9:
The process waits for the transfer process in step 7 to end, and proceeds to step 10 after the transfer process ends. Here, when the transfer process is completed, a flag indicating that the process is completed is set in a register (not shown) of the flash sequencer block 12. Therefore, it is possible to detect the end of the transfer process with this flag.
Step 10:
The 2-buffer mode is set in the operation setting register included in the host interface control block 5. As a result, the operation mode of the host interface block 7 is switched from the 1 buffer mode to the 2 buffer mode, and the data sent from the host computer 4 is taken into the FIFO-A and the FIFO-B in the FO order. .
Step 11:
Under the control of the microprocessor 6, the following write sequencer is set for a register (not shown) of the flash sequencer block 12.
1) An internal write command is set in a predetermined register (not shown) in the flash sequencer block 12 as an internal command.
2) The physical address corresponding to the write destination page and the number of pages to be written are set in a predetermined register (not shown) in the flash sequencer block 12. Here, the physical address corresponding to the write destination page is generated by adding the page address portion of the logical address to the physical block address of the erased block read from the write queue 28 shown in FIG.
Next, the flash sequencer block 12 executes an internal command based on the setting of the write sequencer. When this internal command is executed, information for executing the internal command is supplied from the flash memory interface block 10 to the flash memory 2 via the internal bus 14. As a result, the data taken into FIFO-A and FIFO-B is written into the flash memory 2 in the FI order according to the number of pages to be written. The physical address of the write destination is automatically incremented (addition process for pages) according to the number of pages to be written as described above.
In the above description, the case where the buffer 9 includes two FIFO structure buffers has been described. However, the present invention can be similarly implemented even when the buffer 9 includes three or more buffers. For example, in the case where n FIFO structure buffers are provided, the host interface block 7 is in an operation mode in which data is taken into n-1 FIFO structure buffers at step 7, that is, interblock transfer processing. In the operation mode in which data is fetched only into the FIFO structure buffer not used in the above-described case, and when the inter-block transfer processing is not performed (in the above-described two-buffer mode), the operation mode in which data is fetched into n FIFO structure buffers Become. Even when n FIFO structure buffers are provided, the data is taken into the FIFO structure buffer in the FO order, and the data in the FIFO structure buffer is sent out in the FI order.
【The invention's effect】
As described above, according to the present invention, it is possible to interrupt the inter-block transfer process in the middle of the data write process while suppressing a decrease in the efficiency of the inter-block transfer process and the data write process.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention.
FIG. 2 is a cross-sectional view schematically showing a structure of a memory cell 16 constituting the flash memory 2. FIG.
FIG. 3 is a cross-sectional view schematically showing a memory cell 16 in a write state.
FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory 2;
FIG. 5 is a schematic diagram showing a data structure of a write queue 28 stored in the work area 8;
FIG. 6 is a flowchart showing the operation of the flash memory system 1 according to the present invention.
[Explanation of symbols]
1 Flash memory system
2 Flash memory
3 Controller
4 Host computer
5 Host interface control block
6 Microprocessor
7 Host interface block
8 Work area
9 buffers
10 Flash memory interface block
11 ECC block
12 Flash sequencer block
13 External bus
14 Internal bus
16 memory cells
17 P-type semiconductor substrate
18 Source diffusion region
19 Drain diffusion region
20 Tunnel oxide film
21 Floating gate electrode
22 Insulating film
23 Control gate electrode
24 channels
25 User area
26 Redundant area
28 Write queue

Claims (6)

A plurality of buffers for holding data to be written to the flash memory or data to be read from the flash memory;
A first detection function for detecting a full or empty state of the buffer;
A second detection function for detecting a request for inter-block transfer processing,
When a request for inter-block transfer processing is detected by the second detection function,
Stop the writing process from the buffer to the flash memory,
Furthermore, when it is detected by the first detection function that the buffers are all full,
While stopping the process of taking the data to be written into the flash memory into the buffer,
Start the writing process from the buffer to the flash memory,
Furthermore, when it is detected by the first detection function that all the buffers are in an empty state,
While performing an inter-block transfer process using the buffer,
A memory controller configured to start a process of fetching data to be written to a flash memory in the buffer that is not used in the inter-block transfer process. A third detection function for detecting the end of the inter-block transfer process,
When the end of inter-block transfer processing is detected by the third detection function,
While starting the process of taking data to be written to the flash memory into the buffer used in the inter-block transfer process,
The memory controller according to claim 1, wherein the memory controller is configured to start a writing process from the buffer to the flash memory. A plurality of buffers for holding data to be written to the flash memory or data to be read from the flash memory;
A first detection function for detecting a full or empty state of the buffer;
A second detection function for detecting a request for inter-block transfer processing,
When a request for inter-block transfer processing is detected by the second detection function,
Stop the writing process from the buffer to the flash memory,
Furthermore, when it is detected by the first detection function that the buffers are all full,
While stopping the process of taking the data to be written into the flash memory into the buffer,
Start the writing process from the buffer to the flash memory,
Furthermore, when it is detected by the first detection function that all the buffers are in an empty state,
While performing an inter-block transfer process using the buffer,
A flash memory system comprising a memory controller configured to start a process of fetching data to be written to a flash memory in the buffer that is not used in the inter-block transfer process. A third detection function for detecting the end of the inter-block transfer process,
When the end of inter-block transfer processing is detected by the third detection function,
While starting the process of taking data to be written to the flash memory into the buffer used in the inter-block transfer process,
4. A flash memory system comprising a memory controller according to claim 3, wherein a write process from the buffer to the flash memory is started. When a request for block transfer processing is detected,
Stop writing to the flash memory from a plurality of buffers holding data to be written to the flash memory or data to be read from the flash memory,
Furthermore, when it is detected that all the buffers are full,
While stopping the process of taking the data to be written into the flash memory into the buffer,
Start the writing process from the buffer to the flash memory,
Furthermore, when it is detected that all the buffers are empty,
While performing an inter-block transfer process using the buffer,
A method of controlling a flash memory, comprising starting a process of fetching data to be written into a flash memory into the buffer that is not used in the inter-block transfer process. When detecting the end of the inter-block transfer process,
While starting the process of taking data to be written to the flash memory into the buffer used in the inter-block transfer process,
6. The flash memory control method according to claim 5, wherein a write process from the buffer to the flash memory is started.

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