JP2005107599A - Memory controller, flash memory system equipped with memory controller, and control method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller which can improve throughput in a flash memory system using a plurality of flash memories, the flash memory system equipped with the memory controller, and a control method of flash memories. <P>SOLUTION: The memory controller is equipped with an access control means of controlling access to a zone composed of a plurality of blocks of flash memories; and the zone is composed of blocks in flash memories of a plurality of chips and when one of the flash memories enters a state wherein a process request is rejected, the process request is supplied preferentially to a flash memory in a standby mode for a process request. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  By the way, the NAND flash memory that is often used in the above-described devices is used when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). Can be performed in units of memory cells. However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it must be performed in memory cells. This can only be done with a predetermined erase unit (block) consisting of a plurality of memory cells. Such a batch erase operation is generally called block erase.

  Therefore, when data is rewritten in the NAND flash memory, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting) is written. The process of erasing the block that has been included must be performed. Also, in the flash memory, after receiving internal command information, address information, etc. for executing processing such as erasing processing (block erasing) or writing processing, it is busy until the processing is completed (processing is not accepted). Thus, the next process cannot be performed until the busy state is canceled.

For these reasons, the processing efficiency of a memory system using a flash memory (hereinafter, a memory system using a flash memory is referred to as a flash memory system) is not good. 8-77066) has been proposed. In this proposal, the processing efficiency of the flash memory system is improved by simultaneously performing write processing and read processing on two flash memories.
JP-A-8-77066

  In the flash memory system disclosed in Patent Document 1, since write processing and read processing are simultaneously performed on two flash memories, the bus width of a data bus connected to the flash memory must be doubled. The burden on the circuit was great. Further, nothing has been improved about the problem that the next processing cannot be performed until the busy state is canceled.

  Therefore, the present invention is a flash memory system using a plurality of flash memories, and when any one of the flash memories is in a busy state, a write process or a read process is performed on another flash memory that is not in a busy state. Accordingly, an object of the present invention is to provide a memory controller capable of improving processing efficiency, a flash memory system including the memory controller, and a flash memory control method.

An object according to the present invention is a memory controller including an access control means for controlling access to a zone composed of a plurality of blocks of flash memory,
The zone is composed of blocks in a multi-chip flash memory,
When any of the flash memories is in a processing request acceptance refusal state, the processing request is preferentially supplied to a flash memory in a processing request standby state. This is achieved by the featured memory controller. The invention is also achieved by a flash memory system including the memory controller and a flash memory.

  Here, “the zone is composed of blocks in the flash memory of multiple chips” means that the blocks constituting the zone are not composed of only blocks in a single chip, but are scattered in multiple chips. Means that The “acceptance rejected state” means that the flash memory is busy (state that does not accept processing), and the “standby state” does not mean that the flash memory is busy (state that does not accept processing). This means that the processing request can be accepted.

  In addition, according to the present invention, it is preferable to provide a conversion table creating means for creating an address conversion table for each zone.

  In addition, according to the present invention, it is preferable that a candidate table creating unit that creates a candidate table for each chip constituting the zone is provided.

  According to the present invention, it is preferable that the acceptance refusal state is a result of execution of a write process, a read process, or an erase process.

  In addition, according to the present invention, it is preferable that the erasure state can be checked based on the reading process for the flash memory in the standby state.

An object of the present invention is a flash memory control method for controlling access to a zone composed of a plurality of blocks,
When one of the plurality of chips constituting the zone enters a processing request acceptance refusal state, the processing request is preferentially supplied to the flash memory in a processing request standby state. This is achieved by a flash memory control method.

  Here, “a plurality of chips constituting a zone” means that the blocks constituting the zone are not composed only of blocks in a single chip, but are scattered in a plurality of chips. The “acceptance rejected state” means that the flash memory is busy (state that does not accept processing), and the “standby state” does not mean that the flash memory is busy (state that does not accept processing). This means that the processing request can be accepted.

  Further, according to the present invention, it is preferable to control access to the zone using an address conversion table created for each zone.

  According to the present invention, it is preferable to control access to a zone using a candidate table created for each chip constituting the zone.

  According to the present invention, it is preferable that the acceptance refusal state is a result of execution of a write process, a read process, or an erase process.

  Further, according to the present invention, it is preferable to check the erased state based on the reading process for the flash memory in the standby state.

  According to the present invention, when one of the multiple-chip flash memories that are controlling access is in a busy state (a state in which processing is not accepted), a chip that is not in a busy state (a state in which processing is not accepted). On the other hand, the flash memory system is configured to preferentially supply command information, address information, etc. for executing write processing, read processing, erase processing, etc., thus improving the processing efficiency of the flash memory system Can be made.

  In addition, if a zone is composed of a plurality of chips of flash memory, processing according to requests from the host system can be avoided from being concentrated on a specific chip. Can be improved.

  Also, for a chip that is not busy (not accepting processing), read processing for checking the erase state of the write candidate block, and read processing for creating an address conversion table and an erased block search table are performed. This also improves the processing efficiency of the flash memory system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

  The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data or the like is taken into the controller 3 using the host interface block 7 as an entrance, and the data or the like supplied from the flash memory system 1 to the host system 4 is sent to the host system 4 using the host interface block 7 as an exit. To be supplied.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 becomes writable. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, and internal command information with the flash memory 2 via the internal bus 14.

The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.
[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

  The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

  In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 In the meantime, no channel is formed on the surface of the P-type semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage (high level voltage) is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by this channel.

  That is, in the “erased state”, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the control gate electrode 23 In the state where the read voltage (high level voltage) is applied, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23, A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between the drain diffusion region 19. Therefore, in the “written state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23. Connection state.

  Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when changing the flash memory cell 16 in the written state to the erased state, a high voltage is applied to the control gate electrode 23 on the low potential side, and the voltage is stored in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.
[Description of flash memory structure]
Next, the memory structure of the flash memory will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory is composed of pages, which are processing units for reading and writing data, and blocks, which are data erasing units.

  The page is composed of, for example, a data area 25 of 512 bytes and a redundant area 26 of 16 bytes. The data area 25 is an area mainly storing data supplied from the host system 4, and the redundant area 26 stores additional information such as an error correction code, a corresponding logical block address and a block status. It is an area.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25, and is generated by an ECC block. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. Judgment can be made. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block.

The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.
[Description of logical block address and physical block address]
Since data cannot be overwritten in the flash memory, when rewriting data, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting). The process of erasing the block in which "." Has been written must be performed. At this time, since erasure is processed in units of blocks, data of all pages of a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

When rewriting data as described above, since the data after rewriting is written in a different block from before rewriting, the logical block address given from the host system side and the physical block which is the block address in the flash memory The correspondence with the address changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area of the flash memory, and each time the data is rewritten, the correspondence relationship of the part involved in the rewriting is updated.
[Description of zone configuration]
Next, zone management for assigning a zone composed of a plurality of blocks in the flash memory to a logical block address space will be described with reference to the drawings. FIG. 5 shows an example in which a zone is composed of 1024 blocks. In the example shown in FIG. 5, the zone is composed of 1024 blocks B0000 to B1023, and each block is composed of 32 pages P00 to P31 which are units of read and write processing. This zone is assigned to a logical block address space for 1000 blocks. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing. Further, the reason why the blocks constituting the zone are allocated to the extra 24 blocks is that the occurrence of defective blocks is taken into consideration.

  In the flash memory system according to the present invention, the zone is composed of blocks in a plurality of flash memories. FIG. 6 shows an example in which a zone is constituted by a two-chip flash memory. In FIG. 6, each zone is composed of 512 blocks in the chip 0 of the flash memory and 512 blocks in the chip 1. Here, the physical block addresses in the chip 0 and the chip 1 of the blocks allocated to each zone are not particularly limited, but the first 512 blocks of the physical block address in the chip 0 and the physical block addresses in the chip 1 The 512 blocks from the top were assigned to zone 0, and the subsequent zones (zone 1 to zone N) were also assigned to each zone in the order of physical block addresses. Each zone (zone 0 to zone N) is assigned to a logical block address space for 1000 blocks.

In the flash memory system according to the present invention, an address conversion table and a candidate table, which will be described later, are created for a zone as described above to manage the zone. FIG. 7 shows the relationship between the address conversion table 31 created for each zone and the candidate tables 32 and 33. As shown in FIG. 7, one address conversion table 32 is created for the entire zone, and the candidate tables 32 and 33 are created for each chip constituting the zone, that is, for the chip 0. Then, a candidate table 33 is created for the chip 1.
[Description of address translation table]
Next, the address conversion table will be described with reference to the drawings. FIG. 8 shows an example of the address conversion table. The number of the chip storing the data corresponding to each logical block address and the physical block address in the chip are described in the order of the logical block address. ing. Here, when the zones are configured as shown in FIG. 6, the physical block address range of the blocks in the chip 0 constituting each zone is the same as the physical block address range of the blocks in the chip 1. However, since the chip number is described in the address conversion table, the storage destination of data corresponding to each logical block address is uniquely specified. For logical block addresses that do not store corresponding data, the corresponding data is not stored in the part corresponding to the logical block address in the address conversion table, but instead of the chip number or physical block address. A flag (hereinafter, a flag indicating that corresponding data is not stored is referred to as an unstored flag) is set.

When creating this address conversion table, for example, an area in which the chip number and physical block address for 1000 blocks can be described is secured on the SRAM, and either the area in which the chip number and physical block address are described, or An unstored flag is set as an initial setting for both. Thereafter, the blocks (redundant areas) in the chip 0 assigned to the zone for creating the address conversion table are sequentially read, and the logical block addresses (logical block addresses described as corresponding logical block addresses) are stored in the redundant areas. If it is described, the physical block address of the block in which the logical block address is described is described in the portion corresponding to the logical block address of the address conversion table. At this time, the chip number is also described together with the physical block address. The same processing is performed for the chip 1, and when this processing is completed for the 512 blocks in the chip 0 and the 512 blocks in the chip 1 assigned to the zone for creating the address conversion table, the address conversion table is completed. . Note that in the part where the physical block address and the chip number are not described in the process of creating the address conversion table, the unstored flag described in the initial setting remains as it is.
[Explanation of candidate table]
Next, the candidate table will be described with reference to the drawings. This candidate table is a table in which erased blocks prepared as data write destinations (hereinafter, erased blocks prepared as data write destinations are referred to as write candidate blocks) are set. In addition, as shown in FIG. 7, the candidate table includes two tables, one table for 512 blocks in chip 0 and one table for 512 blocks in chip 1. That is, for each zone, one block of write candidate blocks selected from 512 blocks in chip 0 and one block of write candidates selected from 512 blocks in chip 1 are set.

  Next, a method for searching for erased blocks set as write candidate blocks in the candidate table will be described. The erased block search method set as the write candidate block is the same for the 512 blocks in the chip 0 constituting the zone and for the 512 blocks in the chip 1. A method of searching for erased blocks for 512 blocks within 0 will be described.

  In this erased block search method, a 512-bit area corresponding to 512 blocks in chip 0 constituting a zone is secured on the SRAM, and an erased block search table in which each block is assigned to each bit of the area. Set. FIG. 9 is a conceptual diagram conceptually showing this erased block search table. The upper left bit of the erased block search table shown in FIG. 9A is a block of B0000 (physical block address 0000) in chip 0, and its neighbor is a block of B0001 (physical block address 0001). Corresponding settings are made and the lower right bit is made to correspond to the block B0511 (physical block address 0511). That is, each block in the chip 0 is sequentially allocated from the upper row to the lower row and from the left to the right in the order of the physical block addresses.

  Here, when data is written in a block in chip 0 corresponding to each bit, “0” is written in that bit, and when data is not written (in the case of an erased block), “1” is set in the bit. The erased block search table set in this way can be created together when creating the address conversion table. That is, when the data described in the redundant area of each block is read, if a corresponding logical block address or a block status indicating a defective block is described, “0” is set in the bit corresponding to the block. ”And the corresponding logical block address and the block status indicating that it is a defective block are not described,“ 1 ”is set to the bit corresponding to the block. After creation, when data is written to an erased block, the bit corresponding to that block is rewritten from “1” to “0”, and when a block in which data is written is erased, Updates such as rewriting the bit corresponding to the block from “0” to “1” are performed as needed.

  When searching for an erased block using this erased block search table, as shown in FIG. 9B, each bit is shifted from the upper left to the lower right, that is, B0000 (physical block address 0000). From the bit corresponding to B0511 (physical block address 0511) to the bit corresponding to B0511 (physical block address 0511), each row is sequentially searched from left to right from the top row to the bottom row. For example, the search is sequentially performed from the bit corresponding to B0000 (physical block address 0000). If the bit corresponding to B0010 (physical block address 0010) is “1”, the search ends here and the next search is performed. Starts with a bit corresponding to B0011 (physical block address 0011). If the search proceeds to the bit corresponding to B0511 (physical block address 0511), the search returns to the bit corresponding to B0000 (physical block address 0000).

  Next, a candidate table for setting erased blocks detected by the above search as write candidate blocks will be described. FIG. 10 is a diagram showing data items in the candidate table. In this candidate table, a block number, a check request flag, an error detection flag, and a check start page are set as data items.

  Here, in the block number setting section, the block address of the erased block detected by the search is set. In addition, when data is written to the write candidate block set in the candidate table, the block number setting part displays “unset flag (for example, whether the block address is valid or invalid in the block number setting part). If the bit indicates invalid, this bit is set as an unset flag, and when a block address is set in the block number setting part, this bit is set valid.) Set. In the check request flag setting section, the presence / absence of a check request is set, that is, the “present flag” is set before the check is completed, and the “not present flag” is set after the check is completed. In the error detection flag setting section, an “OK flag” is set when no error is detected in an erase state check described later, and an “NG flag” is set when an error is detected. In the check start page setting section, a page for continuing the processing after canceling the interruption when an erase state check to be described later is interrupted is set. In addition, when data is written in the write candidate block set in the candidate table, the “unset flag” is set in the setting part of the block number, check request flag and error detection flag, and the check start page setting part Set “0” to.

  The write candidate block set in this candidate table is checked for an erased state before data is written. In this erasure check, it is checked whether all the data of each page of the block set in the block number setting part of the candidate table is in the erasure state (logical value “1”), and all the bits are erased. If it is in the state (logical value “1”), if the “OK flag” is in the error detection flag setting part and the bit is in the write state (logical value “0”), the error detection flag setting part "NG flag" is set in

  For example, as shown in FIG. 10A during initialization, “unset flag” is set in the setting part of the block number, check request flag and error detection flag, and “0” is set in the setting part of the check start page. . Next, an erased block is searched, and if the block address is B0010, B0010 is set in the block number setting section, and “present flag” is set in the check request flag setting section (FIG. 10B). ).

Thereafter, the check of the erased state is executed, and when the processing is interrupted when the check is finished up to the 14th page, “15” is set in the check start page (FIG. 10C). Thereafter, the check of the erasure state is resumed, and when all the 32 pages have been normally erased when the processing is completed, as shown in FIG. “None flag” and “OK flag” in the error detection flag setting section. On the other hand, when a page that has not been normally erased is detected, as shown in FIG. 10E, the “none flag” is set in the check request flag setting section and “NG” is set in the error detection flag setting section. Set the flag.
[Description of Processing in Flash Memory System According to the Present Invention]
Next, processing in the flash memory system according to the present invention will be described with reference to the drawings. In the flash memory system according to the present invention, the flash memory is in a busy state (a state in which the process is not accepted) after the command information or address information for executing the internal command is received until the process is completed. The purpose is to suppress a decrease in processing efficiency due to the occurrence of the busy state.

  FIG. 11 is a conceptual diagram for explaining the operation of the flash memory system according to the present invention. In the example shown in FIG. 11, each zone is composed of two flash memories 35 and 36. Here, for example, the erasure processing of the block included in zone 0 is performed, and the block in the flash memory 35 (chip 0) is in a busy state (state in which processing is not accepted). In this case, processing when command information, address information, etc. are output to the flash memory 36 (chip 1) will be described.

  In this process, the memory controller 34 selects the chip 0 by the CE signal (chip enable signal), and outputs command information, address information, and the like for executing the erasure process. The flash memory 35 (chip 0) that has received this command information, address information, and the like is in a busy state (a state in which processing is not accepted) until the processing is completed. Further, the flash memory 35 (chip 0) notifies the memory controller 34 that it is in a busy state (state in which processing is not accepted) by a BUSY signal (busy signal). Receiving this notification, the memory controller 34 selects the chip 1 by the CE signal (chip enable signal), and outputs command information, address information, and the like for executing write processing, read processing, erase processing, and the like.

  Here, the processing in the flash memory system will be described with reference to the timing chart shown in FIG. First, the memory controller sets the CE signal (chip enable signal) on the chip 0 side to a low level, and outputs command information, address information, and the like for executing an erasing process as a DATA signal (data signal) to the internal bus. In response to this, the flash memory on the chip 0 side starts the erasing process, and keeps the BUSY signal (busy signal) at a low level until the process is completed. Subsequently, the memory controller that has detected that the BUSY signal (busy signal) on the chip 0 side has become low level sets the CE signal (chip enable signal) on the chip 1 side to low level, and sends a DATA signal (data) to the internal bus. As the signal), command information, address information, etc. for executing a write process, a read process or an erase process are output. At this time, if the process to be executed is a write process, the memory controller also outputs write data. If the process to be executed is a read process, the flash memory on the chip 1 side outputs read data.

The internal commands such as the write process, read process or erase process are executed as follows. For example, when causing the flash memory on the chip 0 side to execute the erase process, first, the following erase process is set in the register of the flash memory sequencer block.
1) An internal erase command is set as an internal command in a predetermined register in the flash memory sequencer block.
2) The chip number of the flash memory to be erased and the physical block address of the block to be processed are set in a predetermined register in the flash memory sequencer block.

  Thereafter, the flash memory sequencer block executes the process based on the setting of the erase process. When this process is executed, command information, address information, and the like for executing an internal erase command are supplied from the flash memory interface block to the flash memory via the internal bus. At this time, if chip 0 is set in the erasure process setting (chip number setting), the CE signal (chip enable signal) on the chip 0 side becomes low level, so this erasure process is performed on the chip 0 side. Until the processing is completed, the flash memory on the chip 0 side is in a busy state (a state in which processing is not accepted).

When this busy state (state not accepting processing) on the chip 0 side is detected by the BUSY signal (busy signal) and the flash memory on the chip 1 side is caused to execute write processing, first, the register in the flash memory sequencer block is stored. The following writing process is set.
1) An internal write command is set in a predetermined register in the flash memory sequencer block as an internal command.
2) The chip number of the flash memory to be written and the physical block address of the block to be written to are set in predetermined registers in the flash memory sequencer block.

  Thereafter, the flash memory sequencer block executes processing based on the write setting. When this process is executed, command information and address information for executing an internal write command are supplied from the flash memory interface block to the flash memory via the internal bus. At this time, if the chip 1 is set in the setting of the write process (chip number setting), the CE signal (chip enable signal) on the chip 1 side becomes low level. Start with flash memory.

  As described above, in the flash memory system according to the present invention, when one chip of the flash memory is in a busy state (a state where processing is not accepted), with respect to the other chip which is not busy (a state where processing is not accepted), The processing efficiency of the flash memory system is improved by outputting command information, address information, and the like for executing a write process, a read process or an erase process. Even in the case of a flash memory system having a flash memory of 3 chips or more, it is not busy state (state in which processing is not accepted) without waiting for completion of processing of a chip in busy state (state in which processing is not accepted). If command information, address information, and the like for executing write processing, read processing, erase processing, and the like are sequentially output to the chip, the processing efficiency of the flash memory system can be similarly improved.

  In the above description, the zone is constituted by a plurality of chips of flash memory in order to avoid processing corresponding to requests from the host system from being concentrated on a specific chip. For example, even when a request for writing data having consecutive logical block addresses is received from the host system side, if a zone is configured with a plurality of chips of flash memory, the processing target is assigned to a plurality of chips. The possibility of being distributed increases. Note that processing such as writing, reading, or erasing of a chip that is not in a busy state (state in which processing is not accepted) is not limited to processing based on a request from the host system side. For example, a read process for checking the erase state of a write candidate block, or a read process for creating an address conversion table or an erased block search table may be used.

  The configuration of the zone of the flash memory system according to the present invention is not particularly limited. For example, the number of blocks and the number of chips constituting the zone can be set as appropriate according to the application.

FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory 2. FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory 2. FIG. 5 is a diagram showing an example in which a zone is composed of 1024 blocks. FIG. 6 is a diagram showing an example in which a zone is configured by a two-chip flash memory. FIG. 7 is a diagram showing the relationship between the address conversion table and the candidate table for the zone shown in FIG. FIG. 8 is a diagram illustrating an example of an address conversion table. FIG. 9 is a conceptual diagram illustrating an example of an erased block search table. FIG. 10 is a diagram illustrating data items of the candidate table as an example of the candidate table. FIG. 11 is a conceptual diagram for explaining the processing of the flash memory system according to the present invention. FIG. 12 is a timing chart for explaining the processing of the flash memory system according to the present invention.

Explanation of symbols

1 Flash memory system 2, 35, 36 Flash memory 3 Controller 4 Host computer 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 16 Memory cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User area 26 Redundant area 31 Address conversion table 32, 33 Candidate table

Claims (11)

A memory controller comprising access control means for controlling access to a zone composed of a plurality of blocks of flash memory,
The zone is composed of blocks in a multi-chip flash memory,
When any of the flash memories is in a processing request acceptance refusal state, the processing request is preferentially supplied to a flash memory in a processing request standby state. A featured memory controller. 2. The memory controller according to claim 1, further comprising conversion table creating means for creating an address conversion table for each zone. 3. The memory controller according to claim 1, further comprising candidate table creating means for creating a candidate table for each chip constituting the zone. 4. The memory controller according to claim 1, wherein the acceptance refusal state is caused by execution of a write process, a read process, or an erase process. 5. The memory controller according to claim 1, wherein the memory controller is configured to be able to check an erased state based on a read process for the flash memory in the standby state. 6. A flash memory system comprising the memory controller according to claim 1 and a flash memory. A flash memory control method for controlling access to a zone configured by a plurality of blocks,
When one of the plurality of chips constituting the zone enters a processing request acceptance refusal state, the processing request is preferentially supplied to the flash memory in a processing request standby state. A method for controlling a flash memory. 8. The flash memory control method according to claim 7, wherein access to the zone is controlled using an address conversion table created for each zone. 9. The flash memory control method according to claim 7, wherein access to the zone is controlled using a candidate table created for each chip constituting the zone. 10. The flash memory control method according to claim 7, wherein the acceptance refusal state is caused by execution of a write process, a read process, or an erase process. 11. The flash memory control method according to claim 7, wherein the erase state is checked based on a read process for the flash memory in the standby state.

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