JP4181346B2 - Manufacturing method of lead terminal type semiconductor device - Google Patents

Manufacturing method of lead terminal type semiconductor device Download PDF

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JP4181346B2
JP4181346B2 JP2002193511A JP2002193511A JP4181346B2 JP 4181346 B2 JP4181346 B2 JP 4181346B2 JP 2002193511 A JP2002193511 A JP 2002193511A JP 2002193511 A JP2002193511 A JP 2002193511A JP 4181346 B2 JP4181346 B2 JP 4181346B2
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lead
type semiconductor
terminal type
lead terminal
semiconductor device
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JP2004039800A (en
JP2004039800A5 (en
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清二 星野
康浩 原
義昭 井上
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東芝コンポーネンツ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【発明の属する技術分野】
本発明はリード端子型半導体装置の製造方法に関し、特に縦１７．３ｍｍ以下、横１０．５ｍｍ以下、高さ５．１ｍｍ以下の外囲器で２．５４ｍｍピッチの３端子型半導体素子を複数個配置してなるリード端子型半導体装置の製造方法に関する。
【０００２】
【従来の技術】
従来、リード端子型半導体装置としては、図１に示すものが知られている。ここで、半導体素子は複数個リードフレームで繋がった状態にある。
図中の符番１は、図２に示すＭＯＳ型ＦＥＴの各リード端子となるリードを示す。これらリード１は、リードフレーム枠２の内側で該リードフレーム枠２と一体的に連結されている。前記ＭＯＳ型ＦＥＴ８には、縦１７．３ｍｍ以下、横１０．５ｍｍ以下、高さ５．１ｍｍ以下の外囲器４で２．５４ｍｍピッチの３端子をもつ構成となっている。ここで、３端子とは、ドレイン用リード端子９、ソース用リード端子１０、ゲート用リード端子１１を示す。樹脂封止により外囲器４を形成した各ＭＯＳ型ＦＥＴ８は、タイバー３により互いにつながっている。なお、図中の符番５は図示しない金型に形成されたカルを示し、このカル５にはランナー６を介して樹脂注入口７が接続されている。
【０００３】
つまり、金型の所定の位置に半導体チップ（図示せず）を搭載したリードフレームをセットした後、外囲器形成用の樹脂をカル５、ランナー６を介して樹脂注入口７に供給し、半導体チップ等を樹脂封止する外囲器４を形成する。樹脂封止後、カル部を折って除去する。樹脂封止後、各ＭＯＳ型ＦＥＴ８はタイバー３により互いにつながっているので、後工程においてＭＯＳ型ＦＥＴ８の電気的特性を測定するには、タイバー部を切断し、製品を個別に分けなければならない。
【０００４】
【発明が解決しようとする課題】
しかし、従来のリード端子型半導体装置においては、ＭＯＳ型ＦＥＴ８の電気的特性を測定する際、タイバー部を切断し、製品を個別に分けなければならず、搬送の効率が悪く、生産性が低下するという問題があった。
【０００５】
本発明はこうした事情を考慮してなされたもので、前記半導体チップ及び前記第１のリード部分を前記外囲器により樹脂封止するとともに，前記外囲器間を前記樹脂体により連結し、更に前記第１のリードと前記第２のリードとを接続するタイバーをカットして各リード端子型半導体素子が前記リードフレーム枠と電気的に独立した状態とした後、前記各リード端子型半導体素子の電気的特性の測定を行うことにより、各半導体素子がスルーゲートを介してリードフレーム枠に固定された状態で搬送でき、もって搬送効率を改善し、生産性を向上しえるリード端子型半導体装置の製造方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明は、第１のリードと、この第１のリードに搭載された半導体チップと、前記第１のリードと離間して配置された第２のリードと、前記半導体チップ及び該チップを搭載する第１のリード部分を少なくとも樹脂封止する外囲器とを具備するリード端子型半導体素子が複数個、樹脂体により互に連結した状態でリードフレーム枠に保持され、かつ各リード端子型半導体素子がリードフレーム枠と電気的に独立した状態のリード端子型半導体装置を製造する方法において、前記半導体チップ及び前記第１のリード部分を前記外囲器により樹脂封止するとともに，前記外囲器間を前記樹脂体により連結する工程と、前記第１のリードと前記第２のリードとを接続するタイバーをカットして各リード端子型半導体素子が前記リードフレーム枠と電気的に独立した状態とする工程と、前記各リード端子型半導体素子の電気的特性の測定を行う工程を具備することを特徴とするリード端子型半導体装置の製造方法である。
【０００７】
本発明において、前記スルーゲートは、リード端子型半導体素子の外囲器を形成する際に外囲器と同時に形成している。従って、一工程で外囲器とスルーゲートを形成することができる。
【０００８】
【発明の実施の形態】
以下、本発明の実施例に係るリード端子型半導体装置について図３、図４及び図５を参照して説明する。ここで、図３は本発明の一実施例に係るリード端子型半導体装置の平面図、図４は図３のリード端子型半導体装置のリード切断前の要部を説明するための平面図を示す。また、図５（Ａ），（Ｂ）は図３のリード端子型半導体装置から得られたＭＯＳ型ＦＥＴの説明図を示し、図５（Ａ）は断面図、図５（Ｂ）は図５（Ａ）の平面図を示す。
【０００９】
図５（Ａ），（Ｂ）に示すように、符番２１はリード端子型半導体素子としてのＭＯＳ型ＦＥＴを示す。このＭＯＳ型ＦＥＴ２１には、縦１７．３ｍｍ以下、横１０．５ｍｍ以下、高さ５．１ｍｍ以下の外囲器２８で２．５４ｍｍピッチの３端子をもつ構成となっている。具体的には、ＭＯＳ型ＦＥＴ２１は、図５に示すように、一部がドレイン用リード端子２７となる第１のリード２２を備えている。この第１のリード２２のマウント部には、半導体チップ２３が搭載されている。前記第1のリード２２と離間した位置には、第1のリード２２と段違いに第２のリードとしてのゲート用リード端子２５及びソース用リード端子２６が配置されている。
【００１０】
前記半導体チップ２３と前記ゲート用リード端子２５，ソース用リード端子２６とは接続部としてのコネクター２４により電気的に接続されている。前記半導体チップ２３及び該チップ２３の搭載する第１のリード部分は例えばエポキシ樹脂製の外囲器２８により樹脂封止されている。前記外囲器２８の所定の位置にはネジ穴２９が形成されている。
【００１１】
前記各ＭＯＳ型ＦＥＴ２１の外囲器２８は、図３及び図４に示すように樹脂製のスルーゲート（樹脂体）３５により互いに連結され、リードフレーム枠３０の内側に該リードフレーム枠３０と一体的に連結されている。なお、図３は後述するタイバーをカットした状態を示し、図４は各リード端子２５〜２７がタイバーにより互いに接続された状態を示す。
【００１２】
こうした構成の半導体素子において、外囲器２８は次のようにして形成した。即ち、まず、図示しないが、外囲器形成予定部に対応する部分に複数の開口部が形成され、さらに前記樹脂注入用ゲートに対応する部分に樹脂注入口３４、ランナー３３及びカル３２が夫々形成された金型に、半導体チップを搭載した第１のリード等をセットした。つづいて、金型に形成されたカル３２、ランナー３３、該ランナー３３に連通した複数の樹脂注入口３４にエポキシ樹脂原料を流し込むことにより、半導体チップ２３等を樹脂封止して外囲器２８を形成した。
【００１３】
ところで、外囲器２８を形成した直後の各ＭＯＳ型ＦＥＴ２１のリード端子２５〜２７は、図４の斜線で示すようにタイバー３６により電気的に連結した状態にある。そこで、各ＭＯＳ型ＦＥＴ２１の電気的測定を行う際には、前記タイバー３６をカットする必要がある。
【００１４】
実施例１に係るリード端子型半導体装置は、複数のＭＯＳ型ＦＥＴ２１をスルーゲート３５により互いに連結してリードフレーム枠３０に保持され、しかも各ＭＯＳ型ＦＥＴ２１は互いに電気的に独立した構成となっているので、樹脂封止により外囲器２８を形成した後は、図４に示すタイバー３６をカットすることにより、ＭＯＳ型ＦＥＴ２１をリードフレーム枠３０に固定したままで電気的特性の測定が可能となる。従って、製品を個別に搬送した従来技術と比べて生産効率を向上することができる。また、スルーゲート３５は外囲器２８を形成する際に同時に形成できるので、一工程でＭＯＳ型ＦＥＴ２１をスルーゲート３５を介してリードフレーム枠３０に保持することができる。
【００１５】
事実、図３のようなスルーゲート構造を採用することにより、ランナーの体積が減り、樹脂効率が従来の５３％から７６％に改善できることが確認された。
【００１６】
なお、上記実施例では、外囲器がＴＯ−２２０タイプで２．５４ｍｍピッチの３端子を有する場合のＭＯＳ型ＦＥＴを複数個配置したリード端子型半導体装置の場合について述べたが、これに限らず、ピッチが５．４５ｍｍ以下の３端子を有するＭＯＳ型ＦＥＴを複数個配置したリード端子型半導体装置の場合について複数個の製造方法についても、上記実施例と同様な効果が期待できる。
【００１７】
【発明の効果】
以上詳述したように本発明によれば、前記半導体チップ及び前記第１のリード部分を前記外囲器により樹脂封止するとともに，前記外囲器間を前記樹脂体により連結し、更に前記第１のリードと前記第２のリードとを接続するタイバーをカットして各リード端子型半導体素子が前記リードフレーム枠と電気的に独立した状態とした後、前記各リード端子型半導体素子の電気的特性の測定を行うことにより、各半導体素子がスルーゲートを介してリードフレーム枠に固定された状態で搬送でき、もって搬送効率を改善し、生産性を向上しえるリード端子型半導体装置の製造方法を提供できる。
【図面の簡単な説明】
【図１】従来のリード端子型半導体装置の平面図。
【図２】図１のリード端子型半導体装置から得られたＭＯＳ型ＦＥＴの平面図。
【図３】本発明の一実施例に係るリード端子型半導体装置の平面図。
【図４】図３のリード端子型半導体装置のリード切断前の要部を説明するための平面図。
【図５】図３のリード端子型半導体装置から得られたＭＯＳ型ＦＥＴの説明図。
【符号の説明】
２１…ＭＯＳ型ＦＥＴ（リード端子型半導体素子）、
２２…第1のリード、
２３…半導体チップ、
２４…コネクター（接続部）、
２５…ゲート用リード端子、
２６…ソース用リード端子、
２７…ドレイン用リード端子、
２８…外囲器、
２９…ネジ穴
３０…リードフレーム枠、
３２…カル、
３３…ランナー、
３４…樹脂注入口、
３５…スルーゲート、
３６…タイバー。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a lead terminal type semiconductor device, and in particular, a plurality of three-terminal type semiconductor elements having a pitch of 2.54 mm in an envelope of 17.3 mm or less in length, 10.5 mm or less in width, and 5.1 mm or less in height. The present invention relates to a method for manufacturing a lead terminal type semiconductor device.
[0002]
[Prior art]
Conventionally, the lead terminal type semiconductor device shown in FIG. 1 is known. Here, a plurality of semiconductor elements are connected by a lead frame.
Reference numeral 1 in the figure indicates leads that serve as lead terminals of the MOS FET shown in FIG. These leads 1 are integrally connected to the lead frame frame 2 inside the lead frame frame 2. The MOS FET 8 has a configuration having three terminals of 2.54 mm pitch in an envelope 4 having a length of 17.3 mm or less, a width of 10.5 mm or less, and a height of 5.1 mm or less. Here, the three terminals indicate a drain lead terminal 9, a source lead terminal 10, and a gate lead terminal 11. The MOS FETs 8 in which the envelope 4 is formed by resin sealing are connected to each other by a tie bar 3. Reference numeral 5 in the figure indicates a cull formed in a mold (not shown), and a resin injection port 7 is connected to the cull 5 via a runner 6.
[0003]
That is, after setting a lead frame on which a semiconductor chip (not shown) is mounted at a predetermined position of the mold, the resin for forming the envelope is supplied to the resin injection port 7 through the cal 5 and the runner 6, An envelope 4 for sealing a semiconductor chip or the like with resin is formed. After resin sealing, the cull portion is folded and removed. Since the MOS type FETs 8 are connected to each other by the tie bar 3 after the resin sealing, in order to measure the electrical characteristics of the MOS type FET 8 in a later process, the tie bar part must be cut and the products must be individually divided.
[0004]
[Problems to be solved by the invention]
However, in the conventional lead terminal type semiconductor device, when measuring the electrical characteristics of the MOS type FET 8, the tie bar portion must be cut and the products must be individually separated, the conveyance efficiency is poor, and the productivity is lowered. There was a problem to do.
[0005]
The present invention has been made in view of such circumstances, and the semiconductor chip and the first lead portion are resin-sealed by the envelope, and the envelopes are connected by the resin body. After the tie bar connecting the first lead and the second lead is cut so that each lead terminal type semiconductor element is electrically independent from the lead frame frame, each lead terminal type semiconductor element By measuring the electrical characteristics, each semiconductor element can be transported while being fixed to the lead frame through the through gates, thereby improving the transport efficiency and improving the productivity of the lead terminal type semiconductor device. An object is to provide a manufacturing method.
[0006]
[Means for Solving the Problems]
The present invention mounts a first lead, a semiconductor chip mounted on the first lead, a second lead spaced apart from the first lead, the semiconductor chip and the chip. A plurality of lead terminal type semiconductor elements having at least a resin-sealed envelope for the first lead portion are held by the lead frame frame in a state of being connected to each other by a resin body , and each lead terminal type semiconductor element In the method of manufacturing the lead terminal type semiconductor device in a state that is electrically independent of the lead frame, the semiconductor chip and the first lead portion are resin-sealed by the envelope, and between the envelopes And connecting the first lead and the second lead with each other by cutting the tie bar between the lead frame and the lead frame. A step of the independent state, said a method of manufacturing a lead terminal type semiconductor device characterized by comprising the step for measuring the electrical characteristics of the lead-terminal semiconductor device.
[0007]
In the present invention, the through gate is formed simultaneously with the envelope when forming the envelope of the lead terminal type semiconductor element. Therefore, the envelope and the through gate can be formed in one step.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a lead terminal type semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 3, FIG. 4 and FIG. Here, FIG. 3 is a plan view of a lead terminal type semiconductor device according to an embodiment of the present invention, and FIG. 4 is a plan view for explaining a main part of the lead terminal type semiconductor device of FIG. . 5A and 5B are explanatory views of a MOS type FET obtained from the lead terminal type semiconductor device of FIG. 3, FIG. 5A is a cross-sectional view, and FIG. The top view of (A) is shown.
[0009]
As shown in FIGS. 5A and 5B, reference numeral 21 denotes a MOS FET as a lead terminal type semiconductor element. This MOS FET 21 has a configuration having three terminals of 2.54 mm pitch with an envelope 28 having a length of 17.3 mm or less, a width of 10.5 mm or less, and a height of 5.1 mm or less. Specifically, as shown in FIG. 5, the MOS FET 21 includes a first lead 22, part of which serves as a drain lead terminal 27. A semiconductor chip 23 is mounted on the mount portion of the first lead 22. A gate lead terminal 25 and a source lead terminal 26 as second leads are arranged at a position apart from the first lead 22, which is different from the first lead 22.
[0010]
The semiconductor chip 23 is electrically connected to the gate lead terminal 25 and the source lead terminal 26 by a connector 24 as a connecting portion. The semiconductor chip 23 and the first lead portion mounted on the chip 23 are sealed with an envelope 28 made of, for example, epoxy resin. A screw hole 29 is formed at a predetermined position of the envelope 28.
[0011]
The envelope 28 of each MOS FET 21 is connected to each other by a resin through gate (resin body) 35 as shown in FIGS. 3 and 4, and is integrated with the lead frame frame 30 inside the lead frame frame 30. Connected. 3 shows a state in which tie bars to be described later are cut, and FIG. 4 shows a state in which the lead terminals 25 to 27 are connected to each other by tie bars.
[0012]
In the semiconductor device having such a configuration, the envelope 28 was formed as follows. That is, first, although not shown, a plurality of openings are formed in a portion corresponding to the envelope formation scheduled portion, and a resin injection port 34, a runner 33, and a cull 32 are respectively formed in the portion corresponding to the resin injection gate. A first lead or the like mounted with a semiconductor chip was set on the formed mold. Subsequently, an epoxy resin raw material is poured into the cal 32 , runner 33, and a plurality of resin injection ports 34 communicating with the runner 33, so that the semiconductor chip 23 and the like are sealed with resin. Formed.
[0013]
By the way, the lead terminals 25 to 27 of the respective MOS type FETs 21 immediately after the formation of the envelope 28 are in an electrically connected state by the tie bars 36 as shown by the oblique lines in FIG. Therefore, when performing electrical measurement of each MOS FET 21, the tie bar 36 must be cut.
[0014]
In the lead terminal type semiconductor device according to the first embodiment, a plurality of MOS FETs 21 are connected to each other by through gates 35 and held in a lead frame frame 30 , and the MOS FETs 21 are electrically independent from each other. Therefore, after forming the envelope 28 by resin sealing, by cutting the tie bar 36 shown in FIG. 4, it is possible to measure the electrical characteristics while the MOS type FET 21 is fixed to the lead frame frame 30. Become. Therefore, production efficiency can be improved as compared with the prior art in which products are individually conveyed. Further, since the through gate 35 can be formed simultaneously with the formation of the envelope 28, the MOS FET 21 can be held on the lead frame 30 via the through gate 35 in one step.
[0015]
In fact, it was confirmed that by adopting the through gate structure as shown in FIG. 3, the volume of the runner is reduced and the resin efficiency can be improved from 53% to 76%.
[0016]
In the above embodiment, the case of a lead terminal type semiconductor device in which a plurality of MOS type FETs are arranged when the envelope is a TO-220 type and has three terminals of 2.54 mm pitch has been described. In the case of a lead terminal type semiconductor device in which a plurality of MOS type FETs having three terminals with a pitch of 5.45 mm or less are arranged, the same effects as in the above embodiment can be expected for a plurality of manufacturing methods.
[0017]
【The invention's effect】
As described above in detail, according to the present invention, the semiconductor chip and the first lead portion are resin-sealed by the envelope, the envelopes are connected by the resin body, and the first After the tie bar connecting the first lead and the second lead is cut so that each lead terminal type semiconductor element is electrically independent from the lead frame frame, the electrical connection of each lead terminal type semiconductor element is performed. A method of manufacturing a lead terminal type semiconductor device in which each semiconductor element can be transported while being fixed to a lead frame frame via a through gate by measuring characteristics, thereby improving transport efficiency and improving productivity. Can provide.
[Brief description of the drawings]
FIG. 1 is a plan view of a conventional lead terminal type semiconductor device.
2 is a plan view of a MOS type FET obtained from the lead terminal type semiconductor device of FIG. 1. FIG.
FIG. 3 is a plan view of a lead terminal type semiconductor device according to an embodiment of the present invention.
4 is a plan view for explaining a main part of the lead terminal type semiconductor device of FIG. 3 before cutting a lead; FIG.
5 is an explanatory diagram of a MOS type FET obtained from the lead terminal type semiconductor device of FIG. 3. FIG.
[Explanation of symbols]
21 ... MOS type FET (lead terminal type semiconductor element),
22 ... first lead,
23. Semiconductor chip,
24 ... Connector (connection part),
25 ... Gate lead terminal,
26 ... Lead terminal for source,
27 ... Drain lead terminal,
28: Envelope,
29 ... Screw hole 30 ... Lead frame frame,
32 ... Cal,
33 ... Runner,
34. Resin injection port,
35 ... Through gate,
36 ... Tie bar.

Claims (1)

第１のリードと、この第１のリードに搭載された半導体チップと、前記第１のリードと離間して配置された第２のリードと、前記半導体チップ及び該チップを搭載する第１のリード部分を少なくとも樹脂封止する外囲器とを具備するリード端子型半導体素子が複数個、樹脂体により互に連結した状態でリードフレーム枠に保持され、かつ各リード端子型半導体素子がリードフレーム枠と電気的に独立した状態のリード端子型半導体装置を製造する方法において、
前記半導体チップ及び前記第１のリード部分を前記外囲器により樹脂封止するとともに，前記外囲器間を前記樹脂体により連結する工程と、前記第１のリードと前記第２のリードとを接続するタイバーをカットして各リード端子型半導体素子が前記リードフレーム枠と電気的に独立した状態とする工程と、前記各リード端子型半導体素子の電気的特性の測定を行う工程を具備することを特徴とするリード端子型半導体装置の製造方法。A first lead; a semiconductor chip mounted on the first lead; a second lead spaced apart from the first lead; and the first lead on which the semiconductor chip and the chip are mounted A plurality of lead terminal type semiconductor elements having at least a resin-sealed envelope are held by the lead frame frame in a state of being connected to each other by a resin body , and each lead terminal type semiconductor element is a lead frame frame In a method of manufacturing a lead terminal type semiconductor device in an electrically independent state,
A step of resin-sealing the semiconductor chip and the first lead portion with the envelope, and connecting the envelopes with the resin body; and the first lead and the second lead. Cutting a connecting tie bar so that each lead terminal type semiconductor element is electrically independent from the lead frame; and measuring the electrical characteristics of each lead terminal type semiconductor element. A method of manufacturing a lead terminal type semiconductor device.
JP2002193511A 2002-07-02 2002-07-02 Manufacturing method of lead terminal type semiconductor device Expired - Fee Related JP4181346B2 (en)

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