JP4181268B2 - Multi-channel memory controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-channel memory controller, and more particularly to a multi-channel memory controller that controls access to a plurality of types of memory devices independently of processing of the plurality of devices.
[0002]
[Prior art]
Today, the demand for memory control is diversified and complicated as the industry develops, and at the same time the circuit scale is increasing. For example, due to a high-speed memory control request, a plurality of devices (multiple channels) directly request a memory access to the DMA controller without going through the CPU, or an interrupt request is directly made to the DMA controller. In addition, the types of memory devices to be used are diversified, and it is necessary to simultaneously access and control a plurality of types of memory devices.
[0003]
As a conventional example of such a DMA controller, one described in Japanese Patent Laid-Open No. 2-280259 (name of invention “multi-channel memory controller”) is known.
[0004]
The multi-channel memory controller of the publication includes a plurality of address registers for storing a start address and a counter register for storing the number of transfers in the DMA controller. The address generation is repeated for a predetermined number of data. That is, simple DMA control is performed in which a fixed amount of addresses are generated by a fixed address update count instruction mechanism.
[0005]
[Problems to be solved by the invention]
Therefore, the conventional DMA controller is not suitable for each channel of a plurality of devices to directly perform a request (request) and a confirmation (acknowledge) with the DMA timing control unit. Further, in order to generate a register update signal and update a register at the timing when the memory is actually accessed in the DMA timing control unit, it is necessary to provide a control circuit in advance for all types of memory to be used. It becomes complicated and the circuit scale increases.
[0006]
Specifically, various cases, such as a case of a direct memory interrupt request, generation of timing of an address update period such as a memory refresh period, and address update timing of a plurality of types of memory devices such as DRAM, SRAM, etc. A complicated and large-scale configuration is required in which the timing is individually generated by the DMA timing control unit. Furthermore, it is difficult to perform efficient control according to instructions from the CPU.
[0007]
Therefore, the present invention has been made in view of the above problems, and is a simple and low-cost multi-channel configuration capable of controlling access from a plurality of channels to a plurality of types of memory devices in accordance with the above-described requirements. An object of the present invention is to provide a type memory controller.
[0008]
[Means for Solving the Problems]
In order to solve the above problems , the present invention provides an address value designated for each channel in a multi-channel memory controller that controls access to a plurality of types of memories based on different requests from a plurality of channels. A plurality of storage means for storing the address and an addition value for the address value for each channel read from the plurality of storage means, and the addition value and an arbitrary address value or the read address value are added Addition means, selection means for selectively outputting an instruction address from the plurality of channels or an address value output from the addition means, and an address issue permission signal in response to a request from the plurality of channels, and control means Permission means for permitting address issuance to the plurality of types of memory, and the control means And controls the writing from the selecting means by using the acknowledge signal to be returned to et the plurality of channels to the plurality of storage means, and an address updating means for updating the address value of the plurality of storage means in accordance with said request The control means can be connected to the plurality of types of memories, and when the address issue permission signal is input from the permission means, the output address value from the addition means is issued to the plurality of types of memories to control different timings. And a memory control means for outputting the acknowledge signal to be returned to the plurality of channels in accordance with the issuance .
[0010]
[Action]
According to the present invention configured as described above, when the permission unit outputs an address issuance permission signal in response to a request from a plurality of channels and permits the control unit to issue an address to a plurality of types of memories, the control unit returns to the plurality of channels. A power acknowledge signal is returned, and writing to the plurality of storage means is controlled using this acknowledge signal.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0012]
FIG. 1 is a circuit diagram of an embodiment of a multi-channel memory controller according to the present invention.
[0013]
First, the direct memory access operation of a plurality of channels in the configuration of FIG. 1 will be schematically described. Although the number of channels is three here, the present invention is not limited to three channels.
[0014]
The DMA address generation circuit 118 is independent of processing of a CPU (not shown) or the like of each channel in response to request signals REQ1, REQ2, and REQ3 from a plurality of channels CH1, CH2, and CH3 denoted by reference numerals 121 to 123. As described later, address data ADR is generated. The address data ADR is output to the memory controller 130. When the address issue permission signal AVARID from the DMA timing control circuit 108 provided in the DMA address generation circuit 118 is supplied to the controller 130 and the address issue is permitted, the DRAM 131 and the SRAM 132 connected to the controller 130 are separately provided. The controller 130 controls the memory access so as to issue the address data DADR and SADR.
[0015]
When the memory controller 130 issues the address data, it outputs an acknowledge signal ACK to be returned to the request source channel, and returns it to any channel via the DMA address generation circuit 118.
[0016]
In addition to the DMA timing control circuit 108 described above, the DMA address generation circuit 118 includes a selector 100, address registers 101, 102, 103, count registers 111, 112, 113, an adder 104, an addition value control unit 105, and a comparator 106. , An address / latch unit 107, and an address / register update control unit 115 that realizes functions characteristic of the apparatus of the present invention. Each register is provided corresponding to each channel. The address registers 101 to 103 store addresses designated for the respective channels. The count registers 111 to 113 are count values corresponding to the respective channels. Is memorized.
[0017]
The selector 100 selects the control line 1 or the address / count bus 2 according to the bus select signal 5 from the DMA timing control circuit 108. The control line 1 serves as an interface between the DMA address generation circuit 118 and each channel, and performs initial data input, DMA mode setting, and the like. When the selector 100 selects the control line 1, the initial data (arbitrarily set leading transfer address, transfer count) from each channel is output to the corresponding registers via the selection bus 3.
[0018]
The address / count bus 2 is connected to the output of the adder 104 and transfers the calculation result of the address / count value by the adder 104. When the selector 100 selects the address / count bus 2, the current transfer address / remaining transfer count calculated by the adder 104 is output to the corresponding registers via the selection bus 3.
[0019]
The write timing to each register is controlled by the address / register update control unit 115 as described later.
[0020]
The data held in each register is transferred to the adder 104 via the DMA bus 4, where it is added with the addition value 7 instructed from the addition value control unit 105. That is, the addition value control unit 105 generates and outputs the addition value 7 in accordance with the mode signal 8 from the DMA timing control circuit 108. When this addition value 7 is output, the adder 104 outputs the transfer mode, address calculation time, and count calculation. The address value and the count value are added according to time and output to the address / count bus 2.
[0021]
The adder 104 calculates the current transfer address for each transfer for the data (arbitrary address value or the address value in the previous transfer) held in the address registers 101 to 103, and the count registers 111 to 113 For the held data (arbitrary transfer count or remaining transfer count in the previous transfer), the remaining transfer count is calculated for each transfer. The transfer address and the remaining transfer count determined in accordance with the addition value 7 in the adder 104 are selected as the next transfer data by the selector 100 via the address / count bus 2 and used as update data for each register.
[0022]
The added output is supplied to the comparator 106, where a comparison for notifying the DMA timing control circuit 108 of whether or not the transfer is completed is performed. That is, the remaining transfer count is compared with “0”, and if it is “0”, the end of transfer is notified by the end signal 9. In response to the end signal 9, the address / register update control unit 115 operates in a different manner as described later.
[0023]
The DMA timing control circuit 108 further sends a latch signal 11 to the address latch unit 107 at a predetermined timing. The address latch unit 107 latches and holds the addition output from the adder 104 at a timing according to the latch signal 11, and outputs the held data to the memory controller 130 as a DMA address (ADR) as described above.
[0024]
When the memory controller 130 issues the DMA address and outputs the acknowledge signal ACK to be returned to the request source channel as described above, the address register update control unit 115 receives the acknowledge signal and receives each request source channel and each corresponding channel. Acknowledgment signals ACK1, ACK2, and ACK3 are output to the registers via separate transmission lines. For example, when the request source is the channel CH1 (121), the acknowledge signal ACK1 is returned to the channel, and is further supplied to the address register 101 and the count register 111 for writing control.
[0025]
In the configuration shown in FIG. 1, the direct memory access is established without returning an acknowledge signal to the request source channel.
[0026]
The address register update control unit 115 operates according to the ACK relay control signal 12 from the DMA timing control circuit 108, and sends an acknowledge signal ACK from the memory controller 130 to the request source channel to the request source channel and the request source channel. To ACK1 to ACK3 at a predetermined timing. As described above, when the address is updated, writing is controlled so that the value of each register is updated based on the acknowledge signal ACK. In other cases, an arbitrary address value or a value according to each channel request or the comparison result of the comparator 106 is controlled. Writing is controlled so that the count value is stored in each register.
[0027]
According to the above-described embodiment, the memory controller 130 receives the address issue permission signal AVARID, issues an address, and returns the acknowledge signal ACK to be returned to the request source channel for simple and low cost control of register update. This makes it easy to check the address generation in the request source channel, and does not require a complicated configuration to generate a register update signal as in the past, and it depends on the type of memory device used. In addition, there is an effect that the address update in the multi-channel DMA can be performed by efficiently controlling the address update according to the memory interruption or stop.
[0028]
FIG. 2 is a circuit diagram of another embodiment of a multi-channel memory controller according to the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.
[0029]
The DMA address generation circuit 128 shown in FIG. 2 does not include a count register therein, and a plurality of channels CH1, CH2, and CH3 denoted by reference numerals 121a to 123a include count registers 211 to 213, respectively. The address register update control unit 115 receives the acknowledge signal ACK from the memory controller 130, and sends the acknowledge signals ACK1, ACK2 to the request source channels 121a to 123a and the corresponding address registers 101 to 103 via separate transmission lines. , ACK3 is output.
[0030]
That is, the DMA address generation circuit 128 returns the acknowledge signals ACK1, ACK2, and ACK3 in response to the request signals REQ1, REQ2, and REQ3 from the channels 121a to 123a, so that the interface between each channel and the DMA address generation circuit 128 is established. It is the structure which is made. Also in this configuration, the control by the address register update control unit 115 is performed as described above so that the acknowledge signals ACK1, ACK2, and ACK3 are used for the write timing control of the address registers 101 to 103.
[0031]
Also in the present embodiment, the same effects as those of the above-described embodiment can be achieved with a simpler configuration.
[0032]
【The invention's effect】
As described above, according to the present invention, when the permission unit outputs an address issuance permission signal in response to a request from a plurality of channels and permits the control unit to issue an address to a plurality of types of memories, the control unit shifts to a plurality of channels. An acknowledge signal to be returned is returned, and writing to a plurality of storage means is controlled by using this acknowledge signal. Therefore, a plurality of types of memories are not required without requiring a configuration for generating a signal for writing control. In contrast, it is possible to perform direct memory access by a plurality of channels.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of a multi-channel memory controller according to the present invention.
FIG. 2 is a circuit diagram of another embodiment of a multi-channel memory controller according to the present invention.
[Explanation of symbols]
101-103 Address register 108 DMA timing control circuit 111-113, 211-213 Count register 115 Address register update control unit 118, 128 DMA address generation circuit 121-123, 121a-123a Channel 130 Memory controller ACK, ACK1 ~ ACK3 acknowledge signal REQ1-REQ3 request signal

Claims (1)

In a multi-channel memory controller that controls access to multiple types of memory based on separate requests from multiple channels,
A plurality of storage means for storing address values designated for each channel;
Instructing an addition value for an address value for each channel read from the plurality of storage means, and an addition means for adding the addition value and an arbitrary address value or the read address value;
A selection means for selectively outputting an instruction address from the plurality of channels or an address value output by the addition means;
An output unit that outputs an address issuance permission signal in response to a request from the plurality of channels, and a permission unit that permits the control unit to issue an address to the plurality of types of memories;
Address update means for controlling writing from the selection means to the plurality of storage means using an acknowledge signal returned from the control means to the plurality of channels, and updating address values of the plurality of storage means according to the request and, with a,
As the control means,
When the address issue permission signal from the permission means is input, the output address value from the addition means is issued to the plurality of types of memory to control different timings, and according to the issue A multi-channel type memory controller comprising memory control means for outputting the acknowledge signal to be returned to the plurality of channels .

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