JP4178454B2 - Gate drive circuit for power semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device that enables continuous operation without stopping the device when a gate is short-circuited due to a lifetime or an accident in one or more devices in a power conversion device including a plurality of devices. It is related with the gate drive.
[0002]
[Prior art]
FIG. 15 shows a general example of a power conversion device using an IGBT (insulated gate bipolar transistor). This is to supply arbitrary power to the load L connected to the output terminal by configuring the IGBTs in series or in parallel and connecting them to the DC power supply Ed.
FIG. 16 shows a general example of an IGBT drive circuit (gate drive circuit).
The gate drive circuit GDU is turned on by applying a forward voltage Von between the gate and emitter of the IGBT in synchronization with an on / off signal given from a control device (not shown), and turned off by applying a reverse voltage Voff. When the IGBT is normal, the voltage VGE between the gate and the emitter of the IGBT is charged to Von or Voff.
[0003]
By the way, when it is desired to increase the power capacity to be supplied to the load L, it is necessary to increase the capacity of each IGBT constituting the power converter, and the capacity can be increased by connecting a plurality of elements in parallel from the capacity of the single IGBT. And a large-capacity power conversion device can be provided. FIG. 17 shows an internal equivalent circuit of the IGBT having a large capacity. Here, a plurality of IGBT elements Q1 to Qn are connected in parallel.
[0004]
However, as shown in FIG. 18A, each of Q1 to Qn has a gate-emitter input capacitance Cge. Further, since the characteristics of Q1 to Qn are varied, the switching times of Q1 to Qn are varied. Further, a resonance current Igr as shown in FIG. 18B is generated due to the influence of the input capacitance Cge between the chips and the parasitic inductance Lgs existing in the gate wiring. In order to prevent these, resistors Rg1 to Rgn are connected to the gate terminals of each chip as shown in FIG. 17, and the switching current variation and the resonance current Igr between the input capacitors are suppressed.
[0005]
When a plurality of elements are connected in parallel as described above, when one chip or a plurality of chips are destroyed due to the lifetime of the IGBT or an accident, the impedance between the gate and the emitter is short-circuited. FIG. 19 shows a case where one chip Qn is short-circuited. At this time, when the GDU operates to charge the gate of the IGBT by an ON signal given from the control device, the voltage VGE applied to the gate of the IGBT is expressed by the following equation (1).
VGE = [Rgn / (Rgon + Rgn)] · Von (1)
[0006]
In such a case, the other IGBT chips do not charge the gate voltage to the specified voltage Von, the collector-emitter voltage increases from VCE1 to VCE2 as shown in FIG. 20, and the IGBT conduction loss increases. Eventually, the device may be destroyed by thermal runaway, which may lead to a major accident. For this reason, there are devices that suppress the current flowing into the destroyed element (see Patent Document 1), and devices that shut off (turn off) the drive circuit (see Patent Document 2). However, these do not deal with a case where a plurality of elements are connected in parallel.
On the other hand, there are some that deal with a plurality of elements (see Patent Document 3), but this is merely to detect an abnormality of the element, and nothing is described about the processing after the detection.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-209831 (page 3-4, FIG. 1)
[Patent Document 2]
Japanese Patent Laid-Open No. 10-070832 (page 3, FIG. 2)
[Patent Document 3]
JP 2002-222920 A (page 3-4, FIG. 1)
[0008]
[Problems to be solved by the invention]
Therefore, even if the gate impedance of one or a plurality of chips of a power semiconductor element such as an IGBT in which a plurality of elements are connected in parallel is short-circuited, the problem of the present invention is that the other elements are not affected. The purpose is to guarantee (continue) the operation.
[0009]
[Means for Solving the Problems]
In order to solve such a problem, in the invention of claim 1, in a gate drive circuit of a power semiconductor element used in parallel connected to each arm of the power converter,
A detecting means for detecting the current flowing through the gate of the power semiconductor element for each arm and a current increasing means for increasing the current flowing through the gate are provided, and the corresponding power semiconductor element when a gate current of a certain value or more flows. The gate wiring is actively fused .
In the first aspect of the present invention, the current flowing through the gate can be increased during the steady state after the transient state of the power semiconductor element is completed (the second aspect of the invention).
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing the first principle of the present invention.
In this case, electric wires L1 to Ln whose cross-sectional areas and materials are selected are used for the gate lines of each chip so that the current flows when one chip is short-circuited.
The operation of FIG. 1 will be described with reference to FIGS.
First, when all the IGBT elements Q1 to Qn are normal, the gate current of each IGBT is expressed by the following equation in a steady state after a current for charging between the gate and the emitter flows when an on / off signal is input. 0.
Ig = Ig1 = Ig2 = ...... = Ign = 0 (2)
[0011]
In FIG. 1, when a certain chip Qn has a short-circuited gate-emitter impedance as shown in FIG. 2 due to its life or failure, the current shown in the following equation (3) always flows through Qn. .
Ign = Voff / (Rgoff + Rgn) (3)
Therefore, as the electric wires L1 to Ln, an electric wire having a cross-sectional area and a material that melts when the current shown by the above expression (3) flows is selected. Thereby, when an Ign current flows, that is, when the gate of one chip is short-circuited, the gate wiring of the chip is melted and the connection with the gate drive circuit GDU is disconnected as shown in FIG. The chip from which the gate wiring has been separated continues to be turned off regardless of the on / off signal because the gate is short-circuited. In addition, if the gate wiring of the chip whose gate is short-circuited is blown, other chips can charge the gate voltage of the IGBT to Von or Voff by GDU in synchronization with the on / off signal. Similarly, the IGBT can be driven.
[0012]
FIG. 4 shows a second principle configuration of the present invention.
This is one in which fuses F1 to Fn are inserted into the gate wiring of each element as means for separating the gate wiring. Since the fuses F1 to Fn have functions equivalent to those of the electric wires L1 to Ln in FIG. 1, FIGS. 5 and 6 for explaining the operation of FIG. 4 are almost the same as those in FIGS.
[0013]
FIG. 7 shows an embodiment of the present invention.
In this example, in order to cut off the gate wiring, a comparator Cmp for comparing the gate end-to-gate voltage VGE for detecting a gate current with a reference voltage Vref, an output of the Cmp and an OFF signal are input to an AND circuit AND. This circuit is connected to a circuit (not shown) that raises the voltage Voff that turns off the IGBT according to the output of the circuit.
[0014]
The operation will be described.
When the current Ign flows, Cmp detects Ign as shown in FIG. 8 and raises the DC voltage Voff in the steady state after the OFF signal is input. As Voff increases, Ign increases (see FIG. 9). That is, if Voff is increased to Voff1, the current Ign1 flowing at this time is a value represented by the following equation (4).
Ign1 = Voff1 / (Rgoff + Rgn) (4)
Here, the gate wiring is made to be meltable when Ign1 flows. Then, when the gate of one chip is short-circuited, the gate wiring of the chip is melted and the wiring with the GDU is cut off. Since the gate of the chip from which the gate wiring is cut is short-circuited, the chip continues to be turned off regardless of the on / off signal (see FIG. 10).
[0015]
FIG. 11 shows another embodiment of the present invention.
In FIG. 7, the voltage is increased when the gate wiring of the chip is actively melted. Instead, the gate resistance Rgoff is Rgoff = Rgoff1 + Rgoff2, and the voltage at both ends of the Rgoff is detected by the comparator Cmp ( When the value exceeds a predetermined value, the switch S is closed via an AND circuit with an OFF signal, the gate current Ign is increased to Ign1 with Rgoff = Rgoff1 (see FIG. 13), and the gate is short-circuited. By cutting the gate wiring of the chip and disconnecting it from the GDU (see FIG. 14), the same operation as in FIG. 7 is enabled.
[0016]
【The invention's effect】
According to the present invention, when driving a plurality of power semiconductor elements connected in parallel to increase the capacity, even if the gate impedance of one chip or a plurality of chips is short-circuited due to a lifetime or an accident, other elements are affected. The advantage is that its operation can be guaranteed without giving Since the power conversion device can be continuously operated, the reliability of the device is improved as compared with the device that stops the operation.
[Brief description of the drawings]
[1] the first principles block diagram FIG. 2 short-circuit diagram of Figure 1 Figure 3 fusing operation explanatory diagram of Figure 1 Figure 4 second principle diagram Figure of the invention of the invention 5] Explanatory diagram of short circuit and fusing operation in FIG. 4 [FIG. 6] Explanatory diagram at the time of fusing in FIG. 4 [FIG. 7] Circuit diagram showing an embodiment of the present invention [FIG. FIG. 7 is an explanatory diagram at the time of current increase. FIG. 10 is an explanatory diagram at the time of fusing of FIG. 7. FIG. 11 is a circuit diagram showing another embodiment of the present invention. 11 is an explanatory diagram when current is increased. FIG. 14 is an explanatory diagram when fusing is shown in FIG. 11. FIG. 15 is a circuit configuration diagram of a general power converter. FIG. 16 is a general IGBT drive circuit diagram. FIG. 18 is a diagram illustrating an example of a configuration of a capacitive IGBT. FIG. 18 is an explanatory diagram of an IGBT input capacitance and resonance current. FIG. 19 is an explanatory diagram when an IGBT is short-circuited. Illustration of a collector-emitter voltage characteristics of BT DESCRIPTION OF SYMBOLS
L1 to Ln: Electric wire (gate wiring), F1 to Fn: Fuse, Q1 to Qn: IGBT (insulated gate bipolar transistor), Rg1 to Rgn: Gate resistance, Rgon: On resistance, Rgoff: Off resistance, Ig1 to Ign ... Gate current, GDU: gate drive circuit, Cmp: comparator, AND: AND circuit, S: switch.

Claims (2)

In the gate drive circuit of the power semiconductor element used by connecting in parallel to each arm of the power converter,
A detecting means for detecting the current flowing through the gate of the power semiconductor element for each arm and a current increasing means for increasing the current flowing through the gate are provided, and the corresponding power semiconductor element when a gate current of a certain value or more flows. A gate drive circuit for a power semiconductor element, wherein the gate wiring is actively fused . 2. The gate drive circuit for a power semiconductor device according to claim 1, wherein the current flowing through the gate is increased in a steady state after the transient state of the power semiconductor device is finished .

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