JP4166232B2 - Signal processing circuit - Google Patents

Description

  The present invention relates to a signal processing circuit used in an information processing apparatus that processes audio data, image data, and the like recorded on an optical disc, and more particularly to error correction processing.

  Data handled in an information processing apparatus using an optical disc such as a compact disc (CD), a compact disc ROM (CD-ROM), a write-once compact disc (CD-R), a digital video disc (DVD) is audio data. It includes not only digital data such as programs, character information, and image information. Data recorded on such an optical disk is read out by, for example, the system described in Patent Document 1 or the system shown in FIG.

  FIG. 5 shows the configuration of a system for reading data recorded on a CD-ROM. This system includes a detection unit 11, a CD decoder 13, a signal processing circuit 15, a buffer memory 17, and a system control unit 19. In this figure, the data recorded on the CD-ROM 10 is taken out as an electrical signal by the detection unit 11, EFM (Eight to Fourteen Modulation) demodulation and error correction are performed by the CD decoder 13, and then input to the signal processing circuit 15. Is done. An example of the configuration of data output from the CD decoder 13 to the signal processing circuit 15 at this time is shown in FIG. The signal processing circuit 15 processes 2352 bytes of data configured as shown in FIG. 6 as one sector. Here, the sector is a unit in which the signal processing circuit 19 processes data. In the example shown in FIG. 6, one sector includes a synchronization signal (12 bytes), a header (4 bytes), user data (2048 bytes), an EDC code (4 bytes), a blank space (8 bytes), and a P parity (172 bytes). ) And Q parity (104 bytes).

  The signal processing circuit 15 receives the EFM demodulated data from the CD decoder 13 and performs data processing for each sector (2352 bytes) by detecting a synchronization signal. In the case of CD-ROM data, higher reliability is required than in the case of audio data. Therefore, after EFM demodulation and error correction are performed by the CD decoder 13, further error correction is performed in the digital signal processing circuit 15. Generally, error correction at this time is performed by a plurality of symbols positioned in different directions when data is two-dimensionally arranged as disclosed in Japanese Patent Publication No. 7-101543 (a symbol is data used for error correction). This is usually performed by error correction using a code sequence of 1 symbol as 8 bits. That is, error correction is performed by decoding a P sequence (P decoding) and decoding a Q sequence (Q decoding). The error-corrected data is transferred to the host computer 21. The system control unit 19 controls operations of the detection unit 11, the CD decoder 13, and the signal processing circuit 15 in such processing. The control at this time will be described below.

  The system control unit 19 outputs a data read command to the digital signal processing circuit 15. When the signal processing circuit 15 receives this command, the digital data is input from the CD decoder 13 for each sector and stored in the buffer memory 17. To do. Next, the system control unit 19 outputs a data signal decoding processing instruction to the signal processing circuit 15. When the signal processing circuit 15 receives this command, it reads data from the buffer memory 19, performs error detection processing, stores the error detection result in a predetermined register, and notifies the system control unit 19 of the end of processing. . When the system control unit 19 receives the processing end notification from the signal processing circuit 15, the system control unit 19 reads out the error detection result stored in the register and determines the presence or absence of an error. When no error is detected, the above process is repeated for the next sector. When an error is detected, the system control unit 19 outputs an error correction processing command to the signal processing circuit 15. At this time, the signal processing circuit 15 performs error correction according to the instruction, and stores the correction result in a predetermined register. When the error correction process ends, the system control unit 19 is notified of the end of the process. When the end of the process is notified, the system control unit 19 repeats the same process for the data in the next sector. In such a signal processing circuit 15, since control signals are frequently exchanged for each sector between the system control unit 19 and the signal processing circuit 15, data processing takes time, and the system control unit 19 Was burdened.

In response to such a problem, the number of error correction executions is set as the signal processing circuit 15 for reducing the number of control signal exchanges between the system control circuit 19 and the signal processing circuit 15, and whether or not there is an error. In some cases, similar processing is performed on data in all sectors for a set number of times. That is, in the error correction process, when the signal processing circuit 15 receives the data decoding process command from the system control unit 19, the error correction process is performed a predetermined number of times on the data of one sector, and after completion of the predetermined number of error corrections, Error detection processing is performed, the detection result is stored in a predetermined register, and the system control unit 19 is notified of the end. The system control unit 19 determines whether or not to perform further error correction based on the detection result after correction, and appropriately controls the signal processing circuit 15. In such a signal processing circuit 15, the exchange of control between the system control unit 19 and the signal processing circuit 15 is reduced as compared with the above, and the burden on the system control unit 19 is greatly reduced.
Japanese Patent Application No. 7-253127 (Japanese Patent Laid-Open No. 9-91889)

  However, in this case, since error correction processing is performed on all sectors, unnecessary error correction processing is performed on sectors including data with no error. Usually, the error rate of data output from the CD decoder 13 is very low, and in most cases, it is considered that there is no need for error correction in the signal processing circuit 15. For this reason, the signal processing circuit 15 frequently repeats unnecessary error correction processing, resulting in a decrease in processing speed. In the future, with the improvement of the processing capability of the information processing apparatus using the optical disk system, it is desired to improve the data processing speed in the optical disk system, and as a result, the reduction in the processing speed in the signal processing circuit as described above becomes a big problem. .

  The present invention has been made to solve the above problems, and its object is to improve the data processing speed in the optical disc system by improving the efficiency of error correction processing of data recorded on the optical disc. An object of the present invention is to provide a signal processing circuit capable of

A first signal processing circuit according to the present invention includes a decoding unit that performs EFM demodulation on data recorded on an optical disc, a system control unit that outputs a control command, and a buffer memory that temporarily stores data. In a signal processing circuit connected to the CD processing means for inputting the data after EFM demodulation from the decoding means in a unit of sector and storing it in a predetermined area of the buffer memory, the decoding is performed based on the control of the system control means. A pre-error detection means for detecting an error in the data in the process of storing the data input for each sector from the means in a predetermined area of the buffer memory in association with the sector, Error correction is performed on the data stored in the memory by two series of decoding processes There is provided error correction processing means having PQ decoding means and error detection means for performing error detection on the data corrected by the PQ decoding means, and the pre-error detection based on the control of the system control means Based on the error detection result by the means, the error correction is not performed by the PQ decoding means when there is no error, the error correction is performed by the PQ decoding means when there is an error, and the error correction processing means is performed after the error correction. The error detection means performs error detection. The CD interface means and the error correction processing means are controlled based on an external control signal.

As the second signal processing circuit according to the present invention, in the first signal processing circuit, internal control means for controlling the CD interface means and the error correction processing means based on the control command from the system control means is further provided. May be.
This eliminates complicated signal exchange between the system control means and the signal processing circuit in error correction processing, thereby reducing the data processing time in the signal processing circuit and reducing the burden on the system control means. .

As the third signal processing circuit according to the present invention, in the first signal processing circuit, the CD interface means may store the error detection result by the pre-error detection means in association with the data in a predetermined area of the buffer memory. .
As a result, the error detection result is stored in the buffer memory. This error detection result is referred to before the error correction is started, and unnecessary error correction is performed by determining whether or not to perform error correction on the data stored in the buffer memory in the signal processing circuit. Since no processing is performed, the data processing time is shortened.

As the fourth signal processing circuit according to the present invention, in the first signal processing circuit, the CD interface means may notify the system control means of the error detection result by the pre-error detection means.
As a result, the control instruction is output to the signal processing circuit so that only the data that needs to be corrected in the system control means is corrected, so that the data processing time is shortened.

  As the fifth signal processing circuit according to the present invention, in the first signal processing circuit, the pre-error detection means may perform error detection by a cyclic redundancy code check.

As a sixth signal processing circuit according to the present invention, in the second or fifth signal processing circuit, the internal control means causes the PQ decoding means to perform error correction of data for each sector, and after the error correction, the error Let the correction processing means set a correction execution flag indicating whether or not the data of the sector has been corrected, refer to the set correction execution flag, and correct the error when the data is not corrected based on the reference result The error correction processing means may be controlled so that the error detection means in the processing means does not perform error detection on the data of the sector.
With this configuration, after the error correction by the PQ decoding means, a correction execution flag indicating whether or not the data has been corrected is set, the correction execution flag is referred to, and whether or not error correction by the subsequent error correction means is performed. By making the determination, unnecessary error correction processing is not performed, so that the data processing time is shortened.

As a seventh signal processing circuit according to the present invention, in the sixth signal processing circuit, the internal control means performs subsequent error correction processing when the error detection means no longer detects an error in the data. The error correction processing means may be controlled so as not to occur.
With this configuration, after error detection by the error detection means, when no error is detected in the data, subsequent error correction processing is not performed, so unnecessary error correction processing is not repeated and data processing time is reduced. Shortened.

  According to the present invention, in the CD interface means, error detection is performed when the data input from the decoder means is stored in the buffer memory. After the data is stored in the buffer memory, the error detection result is referred to and error correction is performed. An execution decision is made. As a result, unnecessary error correction processing is not performed, error correction processing is performed only for data with errors, and error detection is performed in parallel by both the pre-error detection means and the error detection means. Therefore, the data processing time is shortened.

Hereinafter, an embodiment of a signal processing circuit according to the present invention will be described with reference to the accompanying drawings.
FIG. 1 shows the configuration of the signal processing circuit 25 of the present embodiment. As shown in this figure, the signal processing circuit 25 includes a system control unit 19 that controls the signal processing circuit 25, a CD decoder 13 that performs EFM demodulation and error correction on data recorded on a CD, and a signal processing circuit 25 that performs data processing. Is connected to a buffer memory 17 for temporarily storing data during processing. The signal processing circuit 25 also includes an internal sequencer 27 that controls the operation of each function unit in the signal processing circuit 25 based on the control of the system control unit 19, a CD interface 29 that receives data from the CD decoder 13, And an error correction processing unit 31 that performs error correction on the received data. Further, the CD interface 29 has a first error detector 33, and the error correction processing unit 31 has a PQ decoder 35 and a second error detector 37. For simplification of explanation, in FIG. 1, functional units not related to error detection / correction processing are omitted.

  Data read from the optical disc is subjected to error correction by EFM demodulation and CIRC code in the CD decoder 13 and input to the signal processing circuit 25 together with error information for each byte of the data. The signal processing circuit 25 captures data in units of sectors by detecting a synchronization signal of input data, and stores the data in a predetermined area of the buffer memory 17 for each sector. FIG. 2 shows the allocation of the data area in the buffer memory 17 at this time. As shown in FIG. 2A, the area in the buffer memory 17 is divided into page areas having a predetermined size. Each page area is associated with a sector, and data for one sector is stored in one page. Further, as shown in FIG. 2 (b), one page is made up of a sync signal, a header, a subheader, user data, an error detection byte (EDB), an error flag, and a spare area. The data for one sector (each data in the format shown in FIG. 6) input to 25 is stored in correspondence with the respective areas shown in FIG. The signal processing circuit 25 performs error correction when there is an error in the data stored in the buffer memory 17.

  When the signal processing circuit 25 starts taking in the data EFM demodulated by the CD decoder 13, the system control unit 19 outputs an error detection sequence start command to the signal processing circuit 25. Based on this command, the internal sequencer 27 starts an error detection sequence. FIG. 3 is a flowchart showing the operation of the CD interface 29 at this time. As shown in FIG. 3, when the CD interface 29 inputs data from the CD decoder 13 for each sector under the control of the internal sequencer 27 (S1), the page corresponding to the sector having the page configuration shown in FIG. 2352 bytes of data corresponding to one sector from the CD decoder 13 is stored in the 000h to 92Fh area, and error information from the CD decoder 13 is stored in the EDB area (1 bit error information for each byte of 2352 bytes). (Consisting of 294 bytes) for storage (S2).

  While the data is stored in the buffer memory 17, the first error detector 33 performs a CRC (Cyclic Redundancy Code) check for detecting an error on the input data at the same time (S3). After the CRC check, the CD interface 29 stores a flag indicating the detection result in a predetermined area in the spare area in the page where the data is stored in the buffer memory 17 (S4). Thereby, the data for one sector from the CD decoder and the error detection result for the data are associated with each other by the page. Thereafter, steps S1 to S4 are repeated until there is no more data to be processed (S5).

  After storing the error detection result for a certain sector in the CD interface 29 in the buffer memory 17, the internal sequencer 27 notifies the system controller 19 of the end of the error detection processing for that sector. Thereafter, similarly, under the control of the internal sequencer 27, the CD interface 33 performs error detection on the data input from the CD decoder 13 for each sector in the first error detector 33, and detects this error together with the data in the buffer memory 17. Repeat the process of storing the results.

  During this time, the system control unit 19 outputs to the signal processing circuit 25 an error correction sequence start command for performing error correction on the data of the sector that has been stored in the buffer memory 17. The internal sequencer 27 controls the error correction processing unit 31 based on this command. Hereinafter, the operation of the error correction processing unit 31 at this time will be described with reference to the flowchart of FIG.

  Under the control of the internal sequencer 27, the error correction processing unit 31 reads an error flag indicating an error detection result corresponding to the sector data stored in the buffer memory 17 (S11), and checks this error flag (S12). . As a result, when there is no error for the sector, the error flag of the next sector is read. At this time, if the data of the next sector is not stored in the buffer memory 17, it waits for the data of the next sector to be stored and reads the data after the storage is completed.

  If there is an error, the internal sequencer 27 outputs an error correction processing (decoding processing) execution instruction to the PQ decoder 35. Based on this command, the PQ decoder 35 reads the data of the corresponding sector from the buffer memory 17, and first performs a P-sequence decoding process (hereinafter referred to as "P decoding") (S13). The data after P decoding is stored in the buffer memory 17, and when there is a bit corrected by P decoding, an error correction execution flag indicating that correction has been executed is set (S14). Next, the PQ decoder 35 again reads the data of the corresponding sector from the buffer memory 17, and performs a Q-sequence decoding process (hereinafter referred to as "Q decoding") (S15). The data after Q decoding is stored in the buffer memory 17, and when there is a bit corrected by Q decoding, an error correction execution flag is set (S16). This error correction execution flag is set in a predetermined register in the internal sequencer 27. By referring to this error correction execution flag, the internal sequencer 27 can recognize the presence or absence of an error that cannot be completely corrected by P decoding and Q decoding. When data is corrected by P decoding or Q decoding, an error flag corresponding to the data is reset. Even during such error correction processing, the signal processing circuit 25 performs error detection on the data of another sector and stores it in the buffer memory 17.

  Next, the internal sequencer 27 determines whether or not the data has been corrected after the error correction processing by referring to the error correction execution flag (S17). When corrected, that is, when there is corrected bit data, the second error detector 37 performs error detection by CRC check on the corrected data (S18). Thereafter, the presence or absence of an error is determined based on the CRC check result (S19). When an error is detected, P decoding (S13) and Q decoding (S15) are again performed by the PQ decoder 35, and an error is detected. When is not detected, the process proceeds to the next sector.

  As a result of referring to the error correction execution flag (S17), when error correction is not performed, it is determined that there is an error that cannot be corrected by P decoding and Q decoding, and subsequent error detection is not performed. . That is, the internal sequencer 27 notifies the system control unit 19 that there is an uncorrectable error for the data in that sector (S20), and ends the processing for the data in that sector. In this way, the signal processing circuit 25 repeats error correction by the PQ decoder 35 until all errors in the data of the sector are corrected or an uncorrectable error is confirmed (S13 to S20).

  When error correction is completed for one sector of data, it is determined whether or not the data is the last data (S21). If the data is the last data, the process is terminated. If it is not the last data, the process proceeds to the next sector, and thereafter, the above processes S11 to S21 are repeated until the data of all the sectors is completed (S21).

  As described above, the signal processing circuit 25 according to the present embodiment performs error detection when the EFM demodulated data input from the CD decoder 13 is stored in the buffer memory 17, and the detection result together with the data for each sector. Stored in the buffer memory 17. Thereafter, it is determined whether or not to perform error correction on the data stored in the buffer memory 17 with reference to the error detection result, and error correction is performed only on the data of the sector where the error exists. Therefore, unnecessary error correction is not performed.

  Further, in the signal processing circuit 25, since the internal sequencer 27 controls the above operation, it is not necessary to receive an error correction command for each sector from the system control unit 19, and the signal processing circuit 19 and the system control unit 19 are not affected. Complicated exchange of control signals can be reduced, the data processing time can be shortened, and the load on the system control unit 19 can be reduced.

  Furthermore, in this embodiment, a correction execution flag indicating whether or not data has been corrected during the error correction processing is set, and when it is determined that there is an uncorrectable error with reference to this correction execution flag, (2) When no error is detected as a result of error detection by the error detector 37, the subsequent error detection and correction processing is not performed. As a result, the number of error corrections can be set optimally, and correction processing can be performed efficiently. Further, by providing the second error detector 37 in addition to the first error detector 33, the error detection of the data input from the CD decoder 13 is performed and stored in the buffer memory 17, and in parallel with another Since error correction of sector data can be processed, the processing speed can be improved.

  In the above description, the error detection result when the data from the CD decoder 13 is stored in the buffer memory 17 is stored in the buffer memory 17 together with the data. However, instead of storing in the buffer memory 17, the error detection result is stored in the system. The signal processing circuit 25 may be notified to the control unit 19 so that the system control unit 19 recognizes the presence of an error in the sector and performs error correction processing only on the data of the sector in which the error exists. You may control.

1 is a block diagram of a signal processing circuit according to the present invention. The page block diagram of a buffer memory. 6 is a flowchart showing an error detection operation of a CD interface. The flowchart which shows the decoding processing operation | movement of a signal processing circuit. 1 is a configuration diagram of a CD-ROM system. The figure which shows an example of a CD-ROM format.

Explanation of symbols

10 ... CD (compact disc)
DESCRIPTION OF SYMBOLS 11 ... Detection part 13 ... CD decoder 15 ... Signal processing circuit 17 ... Buffer RAM
DESCRIPTION OF SYMBOLS 19 ... System control part 21 ... Host computer 25 ... Signal processing circuit 27 of this embodiment ... Internal sequencer 29 ... CD interface 31 ... Error correction processing part 33 ... First error detector 35 ... PQ decoder 37 ... Second error detection vessel.

Claims (1)

Connected to a decoding means for performing EFM demodulation on the data recorded on the optical disc, a system control means for outputting a control command, and a buffer memory for temporarily storing the data. In a signal processing circuit comprising CD interface means for inputting data in units of sectors and storing the data in a predetermined area of the buffer memory,
Based on the control of the system control means, a pre-error detection is performed to detect the error of the data in the process of storing the data inputted for each sector from the decoding means in a predetermined area of the buffer memory in correspondence with the sector. Means in the CD interface means,
An error having PQ decoding means for performing error correction on the data stored in the buffer memory by two series of decoding processes, and error detection means for performing error detection on the data corrected by the PQ decoding means Providing correction processing means,
Under the control of the system control means, based on the error detection result by the pre-error detection means , when there is no error, the PQ decoding means does not perform error correction, and when there is an error, the PQ decoding means The error correction is performed by the error detection means in the error correction processing means after the error correction ,
The signal processing circuit, wherein the CD interface means and the error correction processing means are controlled based on an external control signal .

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