JP4163499B2 - 複数の機能を実施するために複数のリアセンブリ・メモリを使用する方法および装置 - Google Patents

複数の機能を実施するために複数のリアセンブリ・メモリを使用する方法および装置 Download PDF

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Publication number
JP4163499B2
JP4163499B2 JP2002367651A JP2002367651A JP4163499B2 JP 4163499 B2 JP4163499 B2 JP 4163499B2 JP 2002367651 A JP2002367651 A JP 2002367651A JP 2002367651 A JP2002367651 A JP 2002367651A JP 4163499 B2 JP4163499 B2 JP 4163499B2
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JP
Japan
Prior art keywords
circuit
memory
packet
reassembled
reassembly
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Expired - Fee Related
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JP2002367651A
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English (en)
Japanese (ja)
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JP2003218908A5 (enExample
JP2003218908A (ja
Inventor
エー．ボーチャード クレッグ
カレ マーリシオ
アール．ディヴィッドソン ジョエル
ダブリュ．ハザウェイ マイケル
テー．カーク ジェームス
ブリアン ワルトン クリストファー
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Agere Systems LLC
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Agere Systems LLC
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Publication of JP2003218908A5 publication Critical patent/JP2003218908A5/ja
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Publication of JP4163499B2 publication Critical patent/JP4163499B2/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/56—Routing software
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architectures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP2002367651A 2001-12-21 2002-12-19 複数の機能を実施するために複数のリアセンブリ・メモリを使用する方法および装置 Expired - Fee Related JP4163499B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/029,679 US8782287B2 (en) 2001-12-21 2001-12-21 Methods and apparatus for using multiple reassembly memories for performing multiple functions
US10/029679 2001-12-21

Publications (3)

Publication Number Publication Date
JP2003218908A JP2003218908A (ja) 2003-07-31
JP2003218908A5 JP2003218908A5 (enExample) 2006-02-09
JP4163499B2 true JP4163499B2 (ja) 2008-10-08

Family

ID=21850300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002367651A Expired - Fee Related JP4163499B2 (ja) 2001-12-21 2002-12-19 複数の機能を実施するために複数のリアセンブリ・メモリを使用する方法および装置

Country Status (5)

Country Link
US (1) US8782287B2 (enExample)
EP (1) EP1326475A1 (enExample)
JP (1) JP4163499B2 (enExample)
KR (1) KR100941569B1 (enExample)
TW (1) TWI254529B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7280527B2 (en) * 2002-05-13 2007-10-09 International Business Machines Corporation Logically grouping physical ports into logical interfaces to expand bandwidth
US7379467B1 (en) * 2003-05-08 2008-05-27 Cypress Semiconductor Corporation Scheduling store-forwarding of back-to-back multi-channel packet fragments
KR100970989B1 (ko) * 2008-04-28 2010-07-21 김상현 다목적 가위
JP6369175B2 (ja) * 2014-07-04 2018-08-08 富士通株式会社 パケット処理装置、制御プログラム、及びパケット処理装置の制御方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317034A (en) * 1976-07-30 1978-02-16 Sharp Corp Image sensor output correcting system
US4149243A (en) * 1977-10-20 1979-04-10 International Business Machines Corporation Distributed control architecture with post and wait logic
US4593357A (en) * 1982-02-19 1986-06-03 Laboratory Equipment Corp. Motor vehicle performance monitoring system
US4885684A (en) * 1987-12-07 1989-12-05 International Business Machines Corporation Method for compiling a master task definition data set for defining the logical data flow of a distributed processing network
US5179530A (en) * 1989-11-03 1993-01-12 Zoran Corporation Architecture for integrated concurrent vector signal processor
US5396490A (en) * 1992-03-23 1995-03-07 Motorola, Inc. Packet reassembly method and apparatus
US5623494A (en) * 1995-06-07 1997-04-22 Lsi Logic Corporation Asynchronous transfer mode (ATM) interconnection system for multiple hosts including advanced programmable interrupt controller (APIC)
US6058114A (en) * 1996-05-20 2000-05-02 Cisco Systems, Inc. Unified network cell scheduler and flow controller
FI974020A0 (fi) 1997-10-21 1997-10-21 Nokia Telecommunications Oy Optimering av resurser i ett paketnaetsflerprocessorsystem
US6249528B1 (en) * 1998-03-12 2001-06-19 I-Cube, Inc. Network switch providing per virtual channel queuing for segmentation and reassembly
US6483839B1 (en) * 1998-03-18 2002-11-19 Conexant Systems, Inc. Apparatus and method for scheduling multiple and simultaneous traffic in guaranteed frame rate in ATM communication system
US6330584B1 (en) * 1998-04-03 2001-12-11 Mmc Networks, Inc. Systems and methods for multi-tasking, resource sharing and execution of computer instructions
JP3742250B2 (ja) * 1999-06-04 2006-02-01 富士通株式会社 パケットデータ処理装置及びそれを用いたパケット中継装置
US6766381B1 (en) 1999-08-27 2004-07-20 International Business Machines Corporation VLSI network processor and methods
US6771652B1 (en) * 1999-11-23 2004-08-03 International Business Machines Corporation Method and system for controlling transmission of packets in computer networks
US6944153B1 (en) * 1999-12-01 2005-09-13 Cisco Technology, Inc. Time slot interchanger (TSI) and method for a telecommunications node
US6629147B1 (en) * 2000-03-31 2003-09-30 Intel Corporation Segmentation and reassembly of data frames
US7092393B1 (en) * 2001-02-04 2006-08-15 Cisco Technology, Inc. Method and apparatus for distributed reassembly of subdivided packets using multiple reassembly components
US6934760B1 (en) * 2001-02-04 2005-08-23 Cisco Technology, Inc. Method and apparatus for resequencing of packets into an original ordering using multiple resequencing components

Also Published As

Publication number Publication date
TWI254529B (en) 2006-05-01
EP1326475A8 (en) 2003-11-12
US8782287B2 (en) 2014-07-15
KR100941569B1 (ko) 2010-02-10
EP1326475A1 (en) 2003-07-09
JP2003218908A (ja) 2003-07-31
KR20030053050A (ko) 2003-06-27
TW200304302A (en) 2003-09-16
US20030120798A1 (en) 2003-06-26

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