JP4159896B2 - Associative memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an associative memory having a function of detecting an error of data to be searched.
[0002]
[Prior art]
FIG. 3 is a schematic configuration diagram of an example of a conventional content addressable memory. The associative memory (hereinafter referred to as “CAM”) performs a coincidence search between data stored in each of a plurality of CAM words included in the memory array (hereinafter referred to as “data to be searched”) and search key data simultaneously for all CAM words. , Information such as a match flag which is the search result is output. FIG. 3 shows only one CAM word 40 included in the CAM memory array for the sake of simplicity.
[0003]
The CAM word 40 stores data to be searched, compares the data to be searched with the search key data, and outputs the comparison result, N bits (in order from the left side in the figure, bit (N-1), bit (N-2),..., Bit (0)) and whether the data stored in the data storage / comparison unit 12 is a valid search target. A 1-bit valid flag storage unit 16 for storing a valid flag indicating whether it is invalid or not, and a match flag serving as a search result between the data stored in the data storage / comparison unit 12 and the search key data are held. And a word logic (logic circuit unit) 22 having the above functions.
[0004]
The data storage / comparison unit 12 includes a memory cell (hereinafter referred to as a data cell) 24 that stores 1-bit data to be searched, data stored in the data cell 24, and search key data corresponding thereto. And a comparison circuit 26 for outputting the comparison result. The valid flag storage unit 16 includes a 1-bit memory cell (hereinafter referred to as a flag cell) 28 that stores a valid flag.
[0005]
The data cell 24 of the data storage / comparison unit 12 and the flag cell 28 of the valid flag storage unit 16 include a data line D for writing and reading data to and from the data cell 24 and the flag cell 28 and its inverted data line. D￣ is connected to each other. These data cells 24 and flag cells 28 are commonly connected to a word line WL that controls the timing of data writing and reading.
[0006]
The comparison circuit 26 of the data storage / comparison unit 12 is connected to a search line K for supplying corresponding search key data and its inverted search line K￣. In addition, the data stored in the corresponding data cell 24 is input to each comparison circuit 26, and the outputs of all the comparison circuits 26 are commonly connected to the match line ML. The match line ML is connected to the word logic 22, and information such as a match flag is output from the word logic 22.
[0007]
In this CAM, prior to performing a match search, under the control of the word line WL, the data cell 24 of the data storage / comparison unit 12 is subjected to the search via the corresponding data line D and its inverted data line D￣. Data is being written. At the same time, the flag cell 28 indicates that the data stored in the data cell 24 of the CAM word 40 is an effective search target via the corresponding data line D and its inverted data line D￣. The valid flag shown is written.
[0008]
The flag cell 28 of the CAM word in which the data to be searched for is not stored in the data cell 24 indicates that the data stored in the data cell 24 of this CAM word is invalid and not to be searched. A flag is written. This valid flag is used as a signal indicating whether the match flag as a result of the match search is valid or invalid.
[0009]
In the search, the search key data is given to the comparison circuit 26 of the data storage / comparison unit 12 via the corresponding search line K and the inverted search line K￣, and the corresponding comparison circuit 26 responds. The data stored in the data cell 24 is compared with the search key data.
[0010]
As a result, if the data stored in each data cell 24 and the corresponding search key data all match in each data storage / comparison unit 12, a signal indicating that they match is output on the match line ML. Is done. On the other hand, if even one bit of the data stored in the data cell 24 does not match the search key data, a signal indicating a mismatch is output on the match line ML and held in the word logic 22. To be processed.
[0011]
By the way, in a semiconductor memory, even if there is no physical failure in the memory cell itself, it is known that a phenomenon called soft error occurs in which data stored in the memory cell is destroyed during use due to external radiation or the like. It has been. Therefore, there is a need for a technique for detecting the occurrence of an error in stored data within the semiconductor memory or correcting the contents of the memory cell in which the error has occurred when the error actually occurs.
[0012]
For example, in a random access memory (hereinafter referred to as RAM), there is a device for detecting and correcting an error by using a technique for detecting whether or not an error has occurred when reading data written in a memory cell. Some have been given.
[0013]
In CAM, a similar problem has come to occur as the degree of integration increases. However, in the case of CAM, since data written in the CAM cell is used during a search operation, there is a possibility that data reading is not necessarily performed. Therefore, in the case of CAM, the method of detecting whether or not an error has occurred at the time of reading data as in the RAM cannot be applied.
[0014]
For this problem, techniques such as Patent Documents 1 and 2 have been proposed. Patent Document 1 stores an error detection code at the same time when data is stored in the RAM, as in the case of error detection of the RAM, and if the data matches after searching, the error detection code is also confirmed at that time. The method is to check if an error has occurred. Patent Document 2 is a technique related to error correction in general, but a method similar to that of Cited Document 1 is disclosed as a method applicable to CAM.
[0015]
However, in both of these conventional techniques, when both are matched by searching, it is detected whether the matched data is really correct or not. There is a problem that it is impossible to detect a state where the two do not match.
[0016]
Further, according to the conventional method, error detection is performed when a match is found, so that an error detection is not performed if there is no match, and there is very little chance of error detection for data for which no match is detected. Therefore, as in the case of the soft error described above, when errors gradually increase over time, there are problems that if the number of error detection opportunities is small, errors increase over time and detection becomes increasingly difficult. .
[0017]
[Patent Document 1]
JP 9-22595 A [Patent Document 2]
US Patent Application Publication No. 2002/0152442
[Problems to be solved by the invention]
An object of the present invention is to solve the problems based on the prior art and to simultaneously detect errors in data to be searched for all CAM words regardless of data reading, search operation execution, or search result match / mismatch. The object is to provide an associative memory capable of
[0019]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an associative memory in which each CAM word has an error detection function of searched data,
Each of the CAM words stores search target data, compares the search target data with the search key data, and outputs the comparison result, and an error detection code. An error detection code storage unit for storing, and an error detection unit;
The data storage / comparison unit and the error detection code storage unit are each connected to a transfer line via a corresponding switch,
The error detection units of all the CAM words are sequentially input via the transfer line by sequentially turning on the switches, and the data to be searched and the error detection code stored in the data storage / comparison unit Provided is an associative memory characterized in that it uses the error detection code stored in the storage unit to simultaneously detect whether or not there is an error in the searched data stored in the data storage / comparison unit. Is.
Here, each of the CAM words preferably includes a plurality of the data storage / comparison units, and each of the data storage / comparison units is preferably connected to the transfer line via a corresponding switch.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an associative memory of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0021]
FIG. 1 is a schematic configuration diagram of an embodiment of an associative memory according to the present invention. The associative memory (hereinafter referred to as CAM) shown in the figure has a function of detecting an error in data to be searched. In the figure, only one CAM word 10 included in the memory array of the CAM is shown for easy comparison with the conventional CAM shown in FIG. The CAM memory array actually includes one word or a plurality of CAM words 10.
[0022]
The CAM word 10 of this embodiment includes an N-bit data storage / comparison unit 12, a 1-bit parity code storage unit 14, a 1-bit valid flag storage unit 16, a switch 18, and an error detection unit (error detection unit). Part) 20 and a word logic 22. The data storage / comparison unit 12, the valid flag storage unit 16, and the word logic 22 are exactly the same as the CAM word 40 shown in FIG. The detailed explanation is omitted.
[0023]
That is, the data storage / comparison unit 12 includes a data cell 24 and a comparison circuit 26, and the valid flag storage unit 16 includes a flag cell 28.
[0024]
The parity code storage unit 14 includes a 1-bit memory cell (hereinafter referred to as a parity cell) 27 that stores a parity code. The parity cell 27 is connected to a data line D for writing and reading data to and from the parity cell 27 and its inverted data line D￣. The parity cell 27 is connected to a word line WL that is common to the data cell 24 and the flag cell 28 and controls the timing for writing and reading data.
[0025]
Here, the parity code p is calculated according to the following formula (1) by a parity code calculation means (not shown), and the parity cell is simultaneously written with the data to be searched for in the data cell 24 and the valid flag in the flag cell 28. 27 is written with a parity code.
p = bit (N-1) XOR bit (N-2) XOR ... XOR bit (0) ... (1)
Bit (N−1), bit (N−2),..., Bit (0) are data of the data cell 24 of the corresponding bit. Note that the parity code calculation means may be provided either inside or outside the CAM.
[0026]
One switch 18 is provided for each of the data cell 24, the parity cell 27, and the flag cell 28. The data stored in the corresponding data cell 24, parity cell 27, and flag cell 28 are input to each switch 18, and the outputs of all the switches 18 are commonly connected to the transfer line TL. Each switch 18 is connected to a transfer control line C for controlling on / off of the switch.
[0027]
In this embodiment, the switch 18 is turned on when a high level is applied to the transfer control line C, and the data stored in the data cell 24, the parity code stored in the parity cell 27, and the flag cell 28 are stored. One of the enabled flags is output on the transfer line TL. In this embodiment, the switch 18 is in the order of the switch 18 corresponding to the bit (N-1), bit (N-2),..., Bit (0) data cell 24, parity cell 27, and flag cell 28. Turned on sequentially.
[0028]
In this embodiment, the error detection unit 20 detects whether or not the data stored in the data cell 24 includes an error (error) based on the 1-bit parity code stored in the parity cell 27. It comprises an XOR gate 29, a selector (SEL) 30, a flip-flop (FF) 32, and two AND gates 34 and 36. Note that the flip-flop 32 operates in synchronization with a signal CLOCK (not shown).
[0029]
The XOR gate 29 receives the output of the transfer line TL and the flip-flop 32. Further, the output of the XOR gate 29 and the output of the flip-flop 32 are input to the two data input terminals of the selector 30, and the signal CALC is input to the selection control input terminal thereof. The data output of the selector 30 is input to the data input terminal of the flip-flop 32, and the signal CLEAR is input to the clear input terminal. The AND gate 34 receives the transfer line TL and the signal CHECK, the AND gate 36 receives the data output of the flip-flop 32 and the output of the AND gate 34, and the AND gate 36 outputs the error signal ERROR. Yes.
[0030]
In the error detection unit 20, the XOR gate 29, the selector 30 and the flip-flop 32 detect the presence or absence of an error in the syndrome s (output of the flip-flop 32, and generate a signal ERROR as a result of the error detection. A linear feedback shift register is calculated that calculates a signal that holds a value halfway up to.
[0031]
Here, the syndrome s is calculated by the linear feedback shift register according to the following equation (2).
s = bit (N-1) XOR bit (N-2) XOR ... XOR bit (0) XOR parity code p (2)
Bit (N−1), bit (N−2),..., Bit (0) are the data of the data cell 24 of the corresponding bit, respectively, as in the case of the above equation (1). In the case of this embodiment, if the syndrome s is at a low level, it means that there is no error in the data, and if it is at a high level, there is an error of 1 bit (odd bit) in the data. Means.
[0032]
The signal CLEAR is a signal that initializes the flip-flop 32. In the present embodiment, when a high level is given to the signal CLEAR, the syndrome s is cleared to a low level.
[0033]
The signal CALC is a signal for instructing whether or not the signal input via the transfer line TL is used for calculating the syndrome s. In the present embodiment, during the period when the signal CALC is at a low level, the current syndrome s is output from the selector 30, and the value of the syndrome s is retained. On the other hand, during the period when the signal CALC is at the high level, the output of the XOR gate 29, that is, the signal (bit (N-1), bit (N-2),..., Input through the current syndrome s and the transfer line TL). The exclusive OR with the bit (0) data and the parity code) is output from the selector 30, and the value of the syndrome s is updated.
[0034]
The signal CHECK is an instruction to output the signal ERROR using the calculated value of the syndrome s. In the present embodiment, while the signal CHECK is at a low level, the outputs of the AND gates 34 and 36 are at a low level, that is, the signal ERROR is at a low level. on the other hand. When the signal CHECK becomes a high level, a logical product of the signal (valid flag) input through the transfer line TL and the syndrome s is obtained, and the result is output as the signal ERROR. That is, when the valid flag is at a low level, no valid data to be searched is stored in the data cell 24 of the CAM word 10, so that the signal ERROR is at a low level. On the other hand, if the valid flag is at a high level, the value of syndrome s is output as signal ERROR.
[0035]
Next, the operation of the CAM shown in FIG. 1 will be described.
Since the operation at the time of searching the CAM shown in FIG. 1 is exactly the same as that of the CAM shown in FIG. 3, the repetitive description is omitted here, and error detection is performed with reference to the timing chart shown in FIG. The operation of CAM in the case of performing will be described. Note that the data cell 24, the parity cell 27, and the flag cell 28 of the CAM word 10 indicate that the search target data, the parity code, and the data stored in the data cell 24 are valid search targets. It is assumed that valid flags shown are stored respectively.
[0036]
In FIG. 2, signal C (N−1), signal C (N−2),..., Signal C (0) are bit (N−1) and bit (N−2) of data cell 24, respectively. ,... Is a transfer control signal C connected to the switch 18 corresponding to the bit (0). Similarly, the signal C (parity code) is a transfer control signal C connected to the switch 18 corresponding to the parity cell 27, and the signal C (valid flag) is connected to the switch 18 corresponding to the flag cell 28. Transfer control signal C.
[0037]
When error detection is performed, as shown in the timing chart of FIG. 2, first, a high level is given to the signal CLEAR in synchronization with the rise of the signal CLOCK. At this time, the signal CALC, the signal CHECK, the signal C (N-1), the signal C (N-2), ..., the signal C (0), the signal C (parity code), and the signal C (valid flag) are all at a low level. It is said.
[0038]
As a result, the flip-flop 32 is initialized according to the low level of the signal CLEAR, and the syndrome s output from the data output terminal becomes the low level. Further, according to the low level of the signal CALC, the syndrome s output from the flip-flop 32 is selectively output from the selector 30, and the value of the syndrome s is held. Further, the output signal of the AND gate 34 becomes low level according to the low level of the signal CHECK, and the output of the AND gate 36, that is, the signal ERROR becomes low level.
[0039]
Subsequently, in synchronization with the rise of the next signal CLOCK, the signal CLEAR is set to the low level, and at the same time, the signal C (N−1) is set to the high level for one clock time. Thereafter, similarly, in synchronization with the rise of the signal CLOCK, the signal C (N−2),..., The signal C (0), and the signal C (parity code) are sequentially set to the high level for one clock time in this order. Further, the signal CALC is also in a state where the signal C (N−1), the signal C (N−2),..., The signal C (0), and the signal C (parity code) are sequentially set to the high level in this order, that is, (N + 1). ) High level during clock time.
[0040]
Thereby, the initialization of the flip-flop 32 is completed according to the low level of the signal CLEAR. Thereafter, the switch 18 corresponding to the data cell 24 of the bit (N-1) is turned on according to the high level of the signal C (N-1), and the data of the bit (N-1) is transmitted via the transfer line TL. Data stored in the cell 24 is input to the XOR gate 29. In the error detection unit 20, the XOR gate 29 performs exclusive OR of the data stored in the data cell 24 of the bit (N−1) and the syndrome s output from the flip-flop 32, and this XOR gate. 29 is output from the selector 30 in response to the high level of the signal CALC and held in the flip-flop 32.
[0041]
Similarly, the bit (N-2) of the data cell 24 is transferred via the transfer line TL according to the high level of the signal C (N-2),..., The signal C (0), and the signal C (parity code). ,..., The bit (0) data of the data cell 24 and the parity code of the parity cell 27 are sequentially input to the XOR gate 29 in this order, and exclusive ORed with the syndrome s and sequentially the value of the syndrome s. Is updated, and finally the value of the syndrome s shown in the above equation (2) is calculated.
[0042]
Subsequently, in synchronization with the rise of the next signal CLOCK, the signal CALC is set to the low level, and at the same time, the signal CHECK and the signal C (valid flag) are set to the high level for one clock time.
[0043]
Thereby, the value of the syndrome s is determined according to the low level of the signal CALC. Further, the switch 18 corresponding to the flag cell 28 is turned on according to the high level of the signal C (valid flag), and the valid flag stored in the flag cell 28 is input to the AND gate 34 via the transfer line TL. . In the error detection unit 20, the AND gate 34 performs a logical product of the signal CHECK and the valid flag, and the AND gate 36 then performs a logical product of the output of the AND gate 34 and the syndrome s to obtain the signal ERROR. Is output.
[0044]
Here, when the valid flag is high level, that is, when the data stored in the data cell 24 is valid to be searched, the output of the AND gate 34 becomes high level, and the AND gate 36 outputs the signal ERROR. The final value of syndrome s is output. If the signal ERROR is at a high level, it means that a 1-bit (odd bit) error exists in the N-bit data stored in the data cell 24. On the other hand, when the valid flag is at the low level, the output of the AND gate 34 is at the low level, and the output of the AND gate 36, that is, the signal ERROR is also at the low level. That is, the signal ERROR outputs a meaningful value only when the valid flag is at a high level.
[0045]
The above error detection operation can be performed at any time regardless of the reading of data stored in the data cell 24, the execution of the search operation, and the match / mismatch of the search results. In the illustrated example, only one CAM word is shown and described. However, when a CAM memory array includes a plurality of CAM words, errors in all the CAM words are detected in the same manner as described above. It can be detected at the same time. It is also possible to perform error correction using the error detection result.
[0046]
Note that the error detection method is not limited to the parity code. For example, any conventionally known error detection method such as a Hamming code or a BCH code can be applied. That is, each word of the CAM to which the present invention is applied only needs to include an error detection code storage unit that stores an error detection code corresponding to the error detection method to be applied, and an error detection unit.
[0047]
The error detection code is not limited to 1 bit, and a multi-bit error detection code such as a Hamming code or a BCH code may be used. For example, if a Hamming code is applied, 1-bit error correction can be performed in addition to error detection. If a BCH code is applied, error correction up to 2 bits is possible. If the data stored in the data cells of all the CAM words included in the CAM memory array is always valid data to be searched, the validity flag is not an essential requirement.
[0048]
The present invention is basically as described above.
The content addressable memory of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the spirit of the present invention. .
[0049]
【The invention's effect】
As described above in detail, the associative memory of the present invention has the error detection stored in the data storage / comparison unit and the data to be searched and the error detection code storage unit sequentially input via the transfer line. This is to detect whether or not there is an error in the searched data stored in the data storage / comparison unit using the reference code.
Thus, according to the associative memory of the present invention, the data to be searched can be simultaneously read in all CAM words at any time regardless of reading of data stored in the CAM word, execution of search operation, and match / mismatch of search results. It is possible to detect the presence or absence of errors.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an embodiment of an associative memory according to the present invention.
2 is a timing chart of an embodiment showing the operation of the content addressable memory shown in FIG. 1. FIG.
FIG. 3 is a schematic configuration diagram of an example of a conventional associative memory.
[Explanation of symbols]
10, 40 CAM word 12 Data storage / comparison unit 14 Parity code storage unit 16 Valid flag storage unit 18 Switch 20 Error detection unit 22 Word logic 24 Data cell 26 Comparison circuit 27 Parity cell 28 Flag cell 29 XOR gate 30 Selector 32 Flip-flop 34 36 AND gate

Claims (2)

Each CAM word is an associative memory having an error detection function for data to be searched,
Each of the CAM words stores search target data, compares the search target data with the search key data, and outputs the comparison result, and an error detection code. An error detection code storage unit for storing, and an error detection unit;
The data storage / comparison unit and the error detection code storage unit are each connected to a transfer line via a corresponding switch,
The error detection units of all the CAM words are sequentially input via the transfer line by sequentially turning on the switches, and the data to be searched and the error detection code stored in the data storage / comparison unit An associative memory characterized by simultaneously detecting whether or not an error exists in data to be searched stored in the data storage / comparison unit by using an error detection code stored in the storage unit.   Each of the CAM words includes a plurality of the data storage / comparison units, and each of the data storage / comparison units is connected to the transfer line via a corresponding switch. 1. The associative memory according to 1.

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