JP4159820B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor (hereinafter referred to as TFT) using a semiconductor film (semiconductor layer) formed on a substrate, a semiconductor device using the thin film transistor, and a manufacturing method thereof. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and a semiconductor device manufactured according to the present invention is a display device represented by a liquid crystal display device or an EL display device incorporating a TFT. Semiconductor integrated circuits (microprocessors, signal processing circuits, high-frequency circuits, etc.) are included in the category.
[0002]
[Prior art]
With the development of information communication technology, display devices as means for receiving information have been changed from CRTs to flat panel displays. Until now, CRT (Cathode Ray Tube), which has been used for the display of televisions that have provided a lot of information, has a problem that it cannot sufficiently cope with the amount of information in recent years (for example, improvement in image quality). . In addition to the high resolution for displaying high-quality video, there also arises a problem that it is not possible to sufficiently cope with the enlargement of the screen. For example, if an attempt is made to increase the screen size, the weight of the CRT itself will increase considerably, making it difficult to carry. Moreover, even if the screen size is the same, the resolution is reduced and the depth has to be increased when the resolution is increased, and there are considerable restrictions on installation at home.
[0003]
Thus, flat panel displays characterized by small size, light weight, and space saving are attracting attention as candidates for display devices that can meet the demand for high resolution and large screen. In particular, liquid crystal display devices have attracted attention, and large-scale research and development has been promoted.
[0004]
In order to cope with the increased amount of information, it must be possible to write data in a short time. In addition, it is required to incorporate a drive circuit in the display device in order to save space and reduce the amount of money. In order to realize such a display device, high-speed operation is required for TFTs that form pixel switching elements and drive circuits.
[0005]
As a method for realizing high-speed operation of TFT, for example, the semiconductor layer is changed from amorphous to polycrystalline, or a dual gate structure in which the semiconductor layer is sandwiched between a pair of gate electrodes described in Japanese Patent No. 2737780 Etc. are considered.
[0006]
However, even when a TFT is formed using polycrystalline silicon, for example, the field effect mobility is 1/10 or less of that of single crystal silicon, and the electrical characteristics of MOS transistors formed on a single crystal silicon substrate are supposed to be. It is not comparable to the characteristics. In addition, there is a new problem that off current is increased due to defects formed in crystal grain boundaries.
[0007]
When an integrated circuit is formed using TFTs, the threshold voltage (Vth) needs to be controlled in order to obtain a desired switching operation. The threshold voltage (Vth) is an important parameter representing the switching characteristics of the TFT, and if this value deviates from a desired value, it will hinder circuit operation. Therefore, in order to control the threshold value, for example, in the case of an n-channel TFT, it shifts to the minus side and becomes normally on (a state in which the gate voltage is not applied). Is a problem. In order to prevent this, means for adding a p-type impurity (acceptor) to the channel region (channel formation region) to shift the threshold voltage to the positive side is taken.
[0008]
Further, the data line side driving circuit has a high driving capability (ON current, I _on ) And hot carrier effect to prevent deterioration and to improve reliability. On the other hand, in order to obtain high quality image quality, a low off-current (I _off ) Is required. As described above, in order to satisfy the requirements for the liquid crystal display device, it is important to realize TFTs having the characteristics required for each circuit.
[0009]
[Problems to be solved by the invention]
Conventionally, threshold control is performed by adding a low-concentration impurity element to the channel region. However, in the case of a structure in which a semiconductor layer is sandwiched between a pair of gate electrodes, carriers are generated at the interface between the semiconductor layer and the insulating film. There is a problem that the probability is high and carriers are injected into the insulating film or the interface between the insulating film and the semiconductor layer, thereby increasing the threshold value. Further, according to the energy band structure of the channel region, the carrier path is only near the interface between the semiconductor layer and the insulating film. For this reason, the decrease in mobility and drain current due to hot carriers accelerated by the voltage applied to the drain being injected into the interface between the insulating film and the semiconductor layer or into the insulating film has been a serious problem.
[0010]
In view of the above problems, an object of the present invention is to realize a highly reliable semiconductor device by realizing high drain current and field effect mobility.
[0011]
[Means for Solving the Problems]
In the present invention, regions having the same conductivity type are provided above and below the channel region, and regions between the upper and lower portions are provided with intrinsic regions or regions with the same conductivity type added at a low concentration, It is characterized by providing a wide region through which the water flows. That is, an impurity region imparting p-type is provided above and below the channel region of the n-channel thin film transistor, and an impurity region imparting n-type is provided above and below the channel region of the p-channel thin film transistor. It is characterized by.
[0012]
Reclaim
Specifically, the present invention relates to a first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. A second semiconductor film provided on the first semiconductor film, a third semiconductor film provided on the second semiconductor film, and a second semiconductor film provided on the third semiconductor film A thin film transistor having a second gate insulating film and a second gate electrode provided on the second gate insulating film, the channel forming region of the first semiconductor film and the third semiconductor film The channel formation region of 1 × 10 ¹⁵ ~ 1x10 ¹⁷ /cm ^Three And the channel formation region of the second semiconductor film is intrinsic or 1 × 10 5. ¹⁵ /cm ^Three It is characterized by a thin film transistor containing an impurity element imparting the conductivity type at the following concentration.
[0013]
The present invention also provides a first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. A second semiconductor film provided on the first semiconductor film, a third semiconductor film provided on the second semiconductor film, and a second semiconductor film provided on the third semiconductor film. An n-channel thin film transistor and a p-channel thin film transistor each having a second gate electrode provided on the second gate insulating film, wherein the first channel in the n-channel thin film transistor The channel formation region of the semiconductor film and the channel formation region of the third semiconductor film are 1 × 10 ¹⁵ ~ 1x10 ¹⁷ /cm ^Three And the channel formation region of the second semiconductor film is intrinsic or 1 × 10 5. ¹⁵ /cm ^Three The channel formation region of the first semiconductor film and the channel formation region of the third semiconductor film in the p-channel thin film transistor include an impurity element imparting p-type at the following concentrations: 1 × 10 ¹⁵ ~ 1x10 ¹⁷ /cm ^Three The channel formation region of the second semiconductor film includes an impurity element imparting n-type at a concentration of 1 × 10 ¹⁵ /cm ^Three A thin film transistor including an impurity element imparting n-type at the following concentration is characterized.
[0014]
When a voltage higher than a threshold voltage that causes an inversion state is applied to the TFT of the present invention, the first semiconductor layer and the third semiconductor layer to which an impurity element imparting one conductivity type serving as a potential barrier is added. Since an inversion layer is widely formed in the intrinsic second semiconductor layer formed therebetween, a region where carriers flow is widened, a drain current is increased, and a subthreshold coefficient (S value) is decreased. An element having a small S value can be said to be an ideal switch having a sharp rise. Note that the impurity of one conductivity type added to the first and third semiconductor layers is added to the channel region of the second semiconductor layer by 1 × 10 5. ¹⁵ /cm ^Three You may add with the following density | concentrations.
[0015]
In addition, since the main inversion layer is formed in the second semiconductor layer, carriers generated in this region are not scattered at the interface between the insulating film and the semiconductor layer, and have a conventional channel region structure. The value of field effect mobility is improved as compared with. Furthermore, the second semiconductor layer is surrounded by a potential generated by a difference in Fermi energy between the first semiconductor layer and the second semiconductor layer, or the second semiconductor layer and the third semiconductor layer, and this potential is Scatter injection of hot carriers generated in the second semiconductor layer into the insulating film is prevented. For this reason, the channel region structure of the present invention can reduce the influence of hot carrier deterioration on the drain current.
[0016]
Note that a channel region is a region that is inverted (has an inversion layer) in a semiconductor layer in which carriers flow, and each of the first to third semiconductor layers has a channel region.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor device disclosed in the present invention is shown in FIG.
[0018]
1A includes a first gate electrode 11, a first gate insulating film 12, a first semiconductor layer 13, a second semiconductor layer 14, and a third semiconductor layer over a substrate 10. 15, a second gate insulating film 18, and a second gate electrode 19. 1B also has a low concentration impurity region (LDD region) in which an impurity element imparting a conductivity type is added between the channel region and the source or drain regions 16b and 17b at a low concentration. ) 16a, 17a.
[0019]
Note that in this specification, an electrode formed between the substrate and the semiconductor layer is referred to as a first gate electrode, and an electrode formed between the semiconductor layer and the pixel electrode is referred to as a second gate electrode. The insulating film formed in contact with the first gate electrode is referred to as a first gate insulating film, and the insulating film formed between the semiconductor layer and the second gate electrode is referred to as a second gate insulating film.
[0020]
A first semiconductor layer 13 is formed in contact with the first gate insulating film 12. In the channel region of the first semiconductor layer, an impurity element imparting one conductivity type (for example, boron if the impurity element imparts p-type conductivity) is 1 × 10 6. ¹⁵ ~ 1x10 ¹⁷ /cm ^Three Is added at a concentration of
[0021]
A second semiconductor layer 14 is formed in contact with the first semiconductor layer 13. An impurity element is not added to the channel formation region of the second semiconductor layer 14 and is substantially intrinsic.
[0022]
A third semiconductor layer 15 is formed in contact with the second semiconductor layer 14. In the channel formation region of the third semiconductor layer 15, an impurity element imparting one conductivity type (which may be the same conductivity type as the impurity element added to the first semiconductor layer) is 1 × 10. ¹⁵ ~ 1x10 ¹⁷ /cm ^Three Is added at a concentration of
[0023]
In the region to be the source region or the drain region 16, 17 (16b, 17b) of the semiconductor layer, an n-type impurity element is 1 × 10 in the case of an n-channel TFT. ¹⁹ ~ 1x10 ^{twenty one} /cm ^Three Is added at a concentration of In the case of a p-channel TFT, the p-type impurity element is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} /cm ^Three Is added at a concentration of Further, in the regions to be the low concentration impurity regions (LDD regions) 16a and 17a, an impurity element imparting conductivity type is 1 × 10 ¹⁸ ~ 1x10 ²⁰ /cm ^Three Is added at a concentration of
[0024]
FIG. 2A-2 shows a band structure when a voltage higher than the threshold voltage is applied to a TFT having a channel region structure (a plurality of semiconductor layers having different conductivity types are stacked) as shown in FIG. Show. For comparison, FIG. 2B-2 shows a band structure in the case where a voltage higher than the threshold voltage is applied to a TFT having a structure of a channel formation region of a conventional TFT.
[0025]
According to the present invention, the conduction band of the intrinsic region is close to the Fermi level, and an inversion layer is formed. As shown in FIG. 2A-2, a region where the carrier exists (moves) is formed in a wide range. In the case of the conventional channel structure, the inversion layer is formed at the interface between the semiconductor layer and the insulating film.
[0026]
In the TFT of the present invention, an inversion layer is also formed at the interface between the semiconductor layer and the insulating film as in the conventional structure, but hot carriers are generated and injected into the interface between the insulating film and the semiconductor layer and the insulating film. Even if it is done, since the main inversion layer is a region formed in the intrinsic second semiconductor layer, it is possible to suppress deterioration such as a decrease in drain current or an increase in S value. Further, since the inversion layer is widely formed in the second semiconductor layer, the drain current increases and the S value becomes a small value. In addition, since the concentration of the impurity element contained in the first semiconductor layer and the third semiconductor layer can be changed in conjunction with the thickness of the insulating film, the degree of freedom in controlling the threshold is improved. be able to.
[0027]
Next, when a voltage that causes the TFT to be in an accumulation state (off state) is applied, the Fermi level of the TFT of the present invention approaches the mid gap, the inversion layer is not formed, and no current flows.
[0028]
As described above, the TFT of the present invention can perform switching operation like a TFT having a normal structure, and further improve characteristics such as field effect mobility, S value, and threshold voltage. be able to.
[0029]
【Example】
(Example 1)
An example of a method for manufacturing the semiconductor device of the present invention will be described with reference to FIGS. Note that the shape of the semiconductor device manufactured here is an example, and the shape of the semiconductor device and the manufacturing process shown in this embodiment are not limited.
[0030]
In FIG. 3A, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 101. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0031]
Wirings 102 to 108 to be first gate electrodes are formed on the insulating surface of the substrate 101. The first gate electrode is formed of one or more conductive materials selected from W, Mo, Ti, and Ta. FIG. 7A shows a top view of them in the pixel portion. Here, the wiring 105 is used as a data line.
[0032]
After the first gate electrode is formed, a first gate insulating film 109 is formed. The first gate insulating film 109 is formed using a silicon oxynitride film with a thickness of 10 to 50 nm, and is formed using a silicon oxide film or a silicon oxynitride film with a thickness of 0.5 to 1 μm. Also good.
[0033]
Note that the surface of the first gate insulating film may be planarized. CMP may be used as a planarization method. As the CMP abrasive (slurry), for example, fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution, and the first gate insulating film 109 is 0.1. The surface may be flattened by removing about ˜0.5 μm.
[0034]
Next, a semiconductor film is formed over the first gate insulating film 109. As the first semiconductor layer 110, an amorphous silicon film is formed and crystallized by a known method (for example, heat treatment using a furnace), whereby the first semiconductor layer is made a crystalline semiconductor layer. In this embodiment, the thickness of the first semiconductor layer is 20 nm. Subsequently, an impurity element imparting one conductivity type is added to the channel region. Regions 112a to 112c to which an impurity element imparting p-type (hereinafter referred to as p-type impurity element) is added are formed in a region to be an n-channel TFT later (FIG. 3B). Next, a region 114 to which an impurity element imparting n-type conductivity is added is formed in a region to be a p-channel TFT later using the mask 113 (FIG. 3C).
[0035]
Next, the second semiconductor layer 115 is formed over the first semiconductor layer 110 (FIG. 4A). The second semiconductor layer is formed into an amorphous semiconductor layer and then crystallized by heat treatment to form a crystalline semiconductor layer. Note that in order to prevent the impurity element in the first semiconductor layer from diffusing, the second semiconductor layer is preferably crystallized using a laser. In this embodiment, the thickness of the second semiconductor layer is 50 nm.
[0036]
Subsequently, a third semiconductor layer 116 is formed over the second semiconductor layer 115. In the same manner as the first semiconductor layer 110, the third semiconductor layer 116 is formed by forming an amorphous semiconductor layer and then crystallizing it by a known method (for example, heat treatment using a furnace). Is a crystalline semiconductor layer. In this embodiment, the thickness of the third semiconductor layer is 20 nm. Subsequently, an impurity element imparting one conductivity type is added to the channel region. Regions 118a to 118c to which a p-type impurity element is added are formed in a region to be an n-channel TFT later (FIG. 4B), and a mask 119 is formed in a region to be a p-channel TFT later. A region 120 to which an n-type impurity element is added is formed using (FIG. 4C).
[0037]
In this embodiment, the thickness of each semiconductor layer is determined as described above. However, the thickness is not limited to this thickness, and the thickness of each semiconductor layer can be determined as appropriate by the practitioner. Good.
[0038]
In this embodiment, the third semiconductor layer is newly formed. However, the second semiconductor layer is formed to a thickness including the third semiconductor layer, and is assumed to be the third semiconductor layer. An impurity element imparting one conductivity type may be added to the channel region up to the depth of the film thickness.
[0039]
As a method of adding an impurity element imparting one conductivity type to the first semiconductor layer, an ion implantation method for performing mass separation, a method of doping with a low acceleration voltage by an ion doping method, a plasma doping method, The practitioner may appropriately determine and use any method such as a method (thermal diffusion method) in which the impurity element is vapor-deposited on the third semiconductor layer and is then heat-treated and diffused into the third semiconductor layer.
[0040]
In addition, as a method of adding an impurity element imparting one conductivity type to the third semiconductor layer, an ion implantation method for performing mass separation, a method of doping with a low acceleration voltage by an ion doping method, plasma doping, or the like The practitioner may determine and use any method among the methods. In addition, the practitioner may determine the thickness of the semiconductor layer as appropriate.
[0041]
Note that in the case of using a circuit having an NMOS structure or a PMOS structure, a doped-poly silicon film (crystalline silicon film, polysilicon film) formed with an impurity element imparting one conductivity type added is formed. The channel structure of the present invention is formed by laminating a poly-silicon film that does not contain impurities, and then laminating a doped-poly silicon film that is deposited with an impurity element imparting one conductivity type added. It is also possible to form.
[0042]
In addition, in the case of using a circuit having a CMOS structure, a doped-poly silicon film is formed in a state where an impurity element imparting one conductivity type is added, and a mask is used for a portion where the polarity is reversed. After adding an impurity element that imparts a type, a poly silicon film that does not contain an impurity is laminated, and a doped-poly silicon film that is formed with an impurity element that imparts one conductivity type is further formed. The channel structure of the present invention can be formed by adding an impurity element imparting one conductivity type using a mask to a portion whose polarity is reversed.
[0043]
In any semiconductor layer crystallization step, the crystallization rate can be improved by irradiating laser light after the crystallization step by heat treatment. The material of the amorphous semiconductor film is not limited, and silicon, silicon germanium (Si _1-x Ge _x ; 0 <x <1, typically x = 0.001 to 0.05) In addition to the alloy, a compound semiconductor layer such as GaAs, InP, SiC, ZnSe, or GaN may be used.
[0044]
As described above, the impurity element imparting one conductivity type to the channel regions of the first semiconductor layer and the third semiconductor layer is 1 × 10 5. ¹⁵ ~ 1x10 ¹⁷ /cm ^Three In the channel region of the second semiconductor layer, a channel structure including an intrinsic element or an impurity element imparting a very small amount of one conductivity type is formed.
[0045]
After that, the semiconductor films 110, 115, and 116 are divided by etching, and semiconductor films 121 to 123 are formed as shown in FIG.
[0046]
Next, as illustrated in FIG. 5B, a second gate insulating film 124 is formed so as to cover the semiconductor films 121 to 123. The second gate insulating film 124 is formed using an insulator containing silicon by a plasma CVD method or a sputtering method. The thickness is 40 to 150 nm.
[0047]
Next, a conductive film is formed over the second gate insulating film 124 in order to form a gate electrode and a wiring. In this embodiment, the gate electrode is formed by stacking two or more conductive films. The first conductive film 125 formed over the second gate insulating film 124 is formed using a nitride of a refractory metal such as molybdenum or tungsten, and the second conductive film 126 formed over the first conductive film 125 is formed using a refractory metal or aluminum. Or low resistance metal such as copper, or polysilicon. Specifically, one or a plurality of nitrides selected from W, Mo, Ta, and Ti are selected as the first conductive film, and W, Mo, Ta, Ti, Al, and Cu are selected as the second conductive film. One or plural kinds of alloys selected from the above, or n-type polycrystalline silicon is used. After the first conductive film 125 and the second conductive film 126 form a mask (not shown), a first etching process is performed to form second gate electrodes 127 to 130. FIG. 7B shows a top view thereof.
[0048]
A first shape electrode having a taper at the end is formed by the first etching process (not shown). Next, using the first shape electrode formed by the first etching process as a mask, a first doping process is performed to form n-type impurity regions having a first concentration in the semiconductor films 121 to 123. The first concentration is 1 × 10 ²⁰ ~ 1.5 × 10 ^{twenty one} /cm ^Three And
[0049]
Next, a second etching process is performed without removing the resist mask. In this etching process, the first shape electrode is anisotropically etched to form the second shape electrode. The second shape electrode is formed so that its width is reduced by this etching process and its end is located inside the n-type impurity region of the first concentration. The length of the LDD is determined by the receding width of the conductive film.
[0050]
Then, a second doping process is performed to add an n-type impurity element to the semiconductor films 121 to 123. The n-type impurity region having the second concentration formed by this doping treatment is self-aligned so as to partially overlap with the first conductive film constituting the second shape electrodes (second gate electrodes) 127 to 130. It is formed consistently. Note that the second gate electrodes 127 to 130 include first conductive films 127a to 130a having a second shape and second conductive films 127b to 130b having a second shape. Impurities added by the ion doping method are added through the first conductive films 127a to 130a constituting the second gate electrode, so that the number of ions reaching the semiconductor film is reduced, inevitably having a low concentration. It becomes. Its concentration is 1 × 10 ¹⁷ ~ 1x10 ¹⁹ /cm ^Three It becomes.
[0051]
Next, a resist mask is formed to cover and conceal a region to be an n-channel TFT, and then a third doping process is performed. By this third doping treatment, p-type impurity regions 132 and 135 to which a third concentration of p-type impurity element is added are formed in the semiconductor film 122. The p-type impurity region of the third concentration is 1.5 × 10 ²⁰ ~ 5x10 ^{twenty one} /cm ^Three The p-type impurity element is added in the concentration range of.
[0052]
In the above-described steps, a region in which an impurity for controlling valence electrons is added to the second gate electrode and the semiconductor film of each TFT, and a high concentration (1 × 10 6 ¹⁹ ~ 1x10 ^{twenty one} /cm ^Three ) Regions 131 and 133 doped with n-type impurities and a low concentration (1 × 10 ¹⁸ ~ 1x10 ²⁰ /cm ^Three ) Regions 134 and 136 to which an n-type impurity element is added are formed. The first gate electrodes 103, 104, 106, and 108 and the second gate electrodes 127 to 129 function as gate electrodes at positions that intersect the semiconductor film. In addition, the second shape wiring 130 serves as one capacitor wiring of the storage capacitor element (FIG. 5C).
[0053]
Thereafter, a step of activating the impurity element added to each semiconductor film is performed. This activation is performed using a gas heating type instantaneous thermal annealing method. The temperature of the heat treatment is 400 to 700 ° C. in a nitrogen atmosphere, typically 450 to 500 ° C. In addition, a laser annealing method using the second harmonic (532 nm) of a YAG laser can be applied. In order to perform activation by irradiation with laser light, the semiconductor film is irradiated with the second harmonic (532 nm) of a YAG laser. Of course, the RTA method using a lamp light source is not limited to the laser light, and the semiconductor film is heated by radiation of the lamp light source from both surfaces of the substrate or one surface (for example, the back surface) of the substrate.
[0054]
Thereafter, as shown in FIG. 6A, a first interlayer insulating film 137 made of silicon nitride is formed to a thickness of 50 to 100 nm by plasma CVD, and heat treatment is performed at 410 ° C. using a clean oven. The semiconductor film is hydrogenated with hydrogen released from the silicon nitride film.
[0055]
Next, a second interlayer insulating film 138 made of an organic insulating material is formed on the first interlayer insulating film 137. The reason for using the organic insulating material is to planarize the surface of the second interlayer insulating film 138. In order to obtain a more complete flat surface, it is desirable to flatten this surface by CMP. When the CMP method is used in combination, a silicon oxide film formed by a plasma CVD method, SOG (Spin on Glass) or PSG formed by a coating method can be used as the second interlayer insulating film.
[0056]
Thereafter, an opening is formed in the first gate insulating film, the second gate insulating film, the first interlayer insulating film, or the second gate insulating film and the second interlayer insulating film, and wirings 139 to 143, A pixel electrode 144 is formed. This wiring is formed by stacking a titanium film and an aluminum film (FIG. 6B). FIG. 8 shows a state in which the active matrix substrate manufactured through the steps up to here is viewed from above.
[0057]
As described above, an active matrix substrate including the driving circuit 205 including the n-channel TFT 201 and the p-channel TFT 202, the switching pixel TFT 203, and the pixel portion 206 having the storage capacitor element 204 can be realized on the same substrate. it can.
[0058]
As shown in FIG. 14, the pixel electrode is a reflective electrode 144 that is a reflective electrode (typically, a conductive film mainly composed of Al as shown in this embodiment) and a transmissive electrode. A transflective display device using the transparent electrode 160 (typically indium tin oxide (ITO)) can also be used. In order to increase the reflection efficiency of the reflective electrode, the reflective electrode may be formed after the surface of the interlayer insulating film is subjected to a treatment such as etching to form irregularities.
[0059]
The n-channel TFT 201 of the driver circuit 205 includes a first gate electrode 103, a first gate insulating film 109, and a p-type impurity element 1 × 10 ¹⁵ ~ 1x10 ¹⁷ /cm ^Three Region comprising a first semiconductor layer 112a and a third semiconductor layer 118a, and a substantially intrinsic second semiconductor layer 150 between the first semiconductor layer and the third semiconductor layer. , A low concentration (n-type) impurity region 134, a semiconductor layer 121 including a high concentration (n-type) impurity region 131 to be a source region or a drain region, a second gate insulating film 124, and a second gate electrode 127.
[0060]
The p-channel TFT 202 of the driver circuit 205 includes a first gate electrode 104, a first gate insulating film 109, and an n-type impurity element that is 1 × 10. ¹⁵ ~ 1x10 ¹⁷ /cm ^Three Region comprising a first semiconductor layer 114 and a third semiconductor layer 120 which are contained at a concentration of the second semiconductor layer 151 and a substantially intrinsic second semiconductor layer 151 between the first semiconductor layer and the third semiconductor layer. , A semiconductor layer 122 including a low-concentration (p-type) impurity region 135, a high-concentration (p-type) impurity region 132 serving as a source region or a drain region, a second gate insulating film 124, and a second gate electrode 128.
[0061]
The TFT 203 in the pixel portion 206 includes a first gate electrode 105, a first gate insulating film 109, and a p-type impurity element of 1 × 10 ¹⁵ ~ 1x10 ¹⁷ /cm ^Three First semiconductor layers 112b and 112c and third semiconductor layers 118b and 118c, and a second semiconductor layer 152 that is substantially intrinsic between the first semiconductor layer and the third semiconductor layer. , A semiconductor layer 123 including a low concentration (n-type) impurity region 136, a high concentration (n-type) impurity region 133 to be a source region or a drain region, a second gate insulating film 124, and a second gate electrode 129.
[0062]
The storage capacitor element 204 of the pixel portion 206 includes a semiconductor layer 123 formed continuously from the semiconductor layer 123 of the pixel TFT, a second-shaped capacitor wiring 130, and a second gate insulating film 124 serving as a dielectric.
[0063]
In each TFT, the length of the low concentration impurity region (LDD region) in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. Such an LDD configuration is mainly intended to prevent TFT deterioration due to the hot carrier effect.
[0064]
A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, or the like can be formed using the n-channel TFT and the p-channel TFT. In particular, the structure of the n-channel TFT 201 is suitable for a buffer circuit having a high drive voltage in order to prevent deterioration due to the hot carrier effect.
[0065]
Further, the present invention can be similarly applied to a circuit based on NMOS or PMOS without using a CMOS structure.
[0066]
(Example 2)
In this embodiment, an example of a process for manufacturing an active matrix liquid crystal display device using the active matrix substrate manufactured in Embodiment 1 will be described.
[0067]
After the formation up to FIG. 6B, an alignment film 153 is formed as shown in FIG. 9, and a rubbing process is performed. Although not shown, before the alignment film 153 is formed, columnar spacers for maintaining the substrate interval may be formed at desired positions by patterning an organic resin film such as an acrylic resin film. . Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0068]
Next, a counter electrode 155 is formed over the counter substrate 154, an alignment film 156 is formed thereon, and a rubbing process is performed. The counter electrode 155 is made of ITO. Then, the counter substrate 154 provided with the seal pattern 157 is attached. Thereafter, a liquid crystal material 158 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix driving liquid crystal display device shown in FIG. 9 is completed.
[0069]
(Example 3)
The present invention can also be applied to TFTs having structures other than those of the embodiment and Example 1. Note that the same reference numerals as those used in FIG. 1 are used.
[0070]
10 shows a first gate electrode 11 on a substrate 10, a first gate insulating film 12 on the first gate electrode 11, a first semiconductor layer 13 on the first gate insulating film 12, A second semiconductor layer 14 is formed on the first semiconductor layer 13, a third semiconductor layer 15 is formed on the second semiconductor layer 14, a second gate insulating film 18 is formed on the third semiconductor layer 15, A second gate electrode 19 is provided on the two gate insulating films 18. In addition, the channel region of the first semiconductor layer 13 and the third semiconductor layer 15 includes an impurity element imparting one conductivity type (in the case of an n-channel TFT, a p-type impurity element; In the case, n-type impurity element) is 1 × 10 ¹⁵ ~ 1x10 ¹⁷ /cm ^Three Is added at a concentration of
[0071]
In the first semiconductor layer 13, the second semiconductor layer 14, and the third semiconductor layer 15, an impurity element imparting a conductivity type different from the conductivity type added to the channel region (in the case of an n-channel TFT, It is an n-type impurity element. In the case of a p-channel TFT, a p-type impurity element) has a high concentration (1 × 10 ²⁰ ~ 5x10 ^{twenty one} /cm ^Three The impurity element imparting a conductivity type different from the conductivity type added to the channel region between the added source region or drain region and the channel region and the source or drain regions 16b and 17b is low in concentration. (1 × 10 ¹⁸ ~ 1x10 ²⁰ /cm ^Three ) Added in low concentration impurity regions (also referred to as LDD regions) 16a and 17a.
[0072]
The first gate electrode 11 is formed so as to overlap the channel region with the first gate insulating film 12 interposed therebetween, and the second gate electrode 19 is formed with the LDD region 16a, the second gate insulating film 18 interposed therebetween. It is formed so as to overlap 17a.
[0073]
A structure in which the gate electrode overlaps the LDD region through an insulating film is known as a GOLD (Gate-drain Overlapped LDD) structure, and a high electric field in the vicinity of the drain is relaxed to prevent hot carrier injection. It is effective for prevention.
[0074]
By combining the present invention with the above GOLD structure, deterioration due to hot carrier injection can be prevented, and a semiconductor device with higher field effect mobility, drain current, low S value, threshold value and high reliability can be realized. .
[0075]
Example 4
In this embodiment, a semiconductor device including a channel region having an energy band structure as illustrated in FIG. 2A-1 by stacking mixed crystal semiconductors will be described. Note that FIG. 2B-1 is an explanatory diagram of a semiconductor device including a channel region having a conventional energy band structure.
[0076]
As in the first embodiment, a first gate electrode is formed over the substrate, and a first gate insulating film is formed over the first gate electrode.
[0077]
Next, as a first semiconductor layer on the first gate insulating film, Al _x GaAs _1-x A film is formed, and then a GaAs film is formed as a second semiconductor layer on the first semiconductor layer. Furthermore, as a third semiconductor layer on the second semiconductor layer, Al _x GaAs _1-x A film is formed.
[0078]
In accordance with Embodiment 1, after forming a second gate insulating film and forming a second gate electrode on the second gate insulating film, an n-type impurity element is formed in the source region or drain region of the n-channel TFT. A semiconductor device having an energy band structure as shown in FIG. 2A-1 can be realized by adding a p-type impurity element to a source region or a drain region of a p-channel TFT.
[0079]
By stacking the mixed crystal semiconductor films in this manner, a channel region having an energy band structure as shown in FIG. 2A-1 can be formed without stacking a semiconductor layer to which an impurity element is added. .
[0080]
(Example 5)
A CMOS circuit and a pixel portion formed by implementing the present invention can be used for an active matrix liquid crystal display (liquid crystal display device). That is, the present invention can be implemented in all electric appliances in which these liquid crystal display devices are incorporated in a display portion.
[0081]
Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned. Examples of these are shown in FIGS. 11, 12 and 13.
[0082]
FIG. 11A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like.
[0083]
FIG. 11B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like.
[0084]
FIG. 11C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like.
[0085]
FIG. 11D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like.
[0086]
FIG. 11E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.
[0087]
FIG. 11F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like.
[0088]
FIG. 12A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like.
[0089]
FIG. 12B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like.
[0090]
FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0091]
FIG. 12D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 12D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0092]
However, the projector shown in FIG. 12 shows a case where a transmissive electro-optical device is used, and an application example of a reflective liquid crystal display device is not shown.
[0093]
FIG. 13A shows a mobile phone, 3001 is a display panel, and 3002 is an operation panel. The display panel 3001 and the operation panel 3002 are connected at a connection portion 3003. An angle θ between the surface of the connection unit 3003 on which the display unit 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 on which the operation keys 3006 are provided can be arbitrarily changed.
Further, it has an audio output unit 3005, operation keys 3006, a power switch 3007, and an audio input unit 3008.
[0094]
FIG. 13B illustrates a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, an antenna 3106, and the like.
[0095]
FIG. 13C illustrates a display, which includes a main body 3201, a support base 3202, a display portion 3203, and the like. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0096]
As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields.
[0097]
(Example 6)
In this example, simulation of gm, drain current, etc. was performed using the dual gate structure (configuration a) of the present invention and a general dual gate structure (configuration b). The transistors of configurations a and b were assumed to have a single drain structure with L / W = 10/8 μm. In the configuration a, the thickness of the first semiconductor film and the third semiconductor film is 10 nm, the thickness of the second semiconductor film is 30 nm, and the channel regions of the first semiconductor film and the third semiconductor film are formed. Boron 2 × 10 ¹⁶ / Cm ^Three And the channel region of the second semiconductor film is intrinsic (carrier concentration is 1 × 10 ^Ten / Cm ^Three ). In the configuration b, the thickness of the semiconductor film is 50 nm, and boron is 2 × 10 6 in the channel region. ¹⁶ / Cm ^Three Added. The simulation results are shown in FIGS. 15 (A) and (B).
[0098]
FIG. 15A shows a graph (A) indicating gm (transconductance) and a graph (B) indicating Vg-Id characteristics. From the graph (a), it can be seen that the configuration a has a higher gm than the configuration b. This gm has a certain proportional relationship with the mobility of the transistor, and it can be said that the mobility of the configuration a is larger than that of the configuration b.
[0099]
Also, from the graph (b), it can be seen that the configuration a has a higher Id (drain current) than the configuration b in the saturation region. The configuration a having a high drain current can make the channel region smaller and the transistor can be highly integrated than the configuration b capable of obtaining the same drain current.
[0100]
FIG. 15B shows a graph showing the Vd-Id characteristics. It can be clearly seen from FIG. 15B that the configuration a has a higher Id (drain current) than the configuration b. The configuration a having a high drain current can make the channel region smaller and the transistor can be highly integrated than the configuration b capable of obtaining the same drain current.
[0101]
As described above, according to the present invention, a transistor with improved mobility and drain current can be obtained. Such a transistor with improved mobility and drain current is preferably used for a driver circuit.
[0102]
【The invention's effect】
When a voltage higher than a threshold voltage that causes an inversion state is applied to the TFT having the structure of the present invention, the first semiconductor layer to which an impurity element imparting one conductivity type serving as a potential barrier is added and the third semiconductor layer Since an inversion layer is widely formed in the intrinsic second semiconductor layer formed between the semiconductor layers, a region where carriers flow is increased, a drain current is increased, and a subthreshold coefficient (S value) is decreased. An element having a small S value can be said to be an ideal switch having a sharp rise.
[0103]
In addition, since the main inversion layer is formed in the second semiconductor layer by forming the channel region as described above, hot carriers generated in the second semiconductor layer are scattered and injected at the interface of the insulating film. There is nothing. Accordingly, the field effect mobility is improved, and the second semiconductor layer is surrounded by the potential generated by the difference in Fermi energy between the first semiconductor layer and the second semiconductor layer or between the second semiconductor layer and the third semiconductor layer. Therefore, hot carriers generated in the second semiconductor layer can be prevented from being scattered and injected into the insulating film, and the influence of hot carrier deterioration on the drain current can be reduced.
[0104]
As described above, according to the present invention, a semiconductor device having excellent reliability and electrical characteristics can be realized.
[Brief description of the drawings]
FIG. 1 shows a TFT of the present invention.
FIG. 2 is a diagram showing an energy band structure of a channel region of the present invention.
FIG. 3 is a diagram showing an example of implementation of the present invention.
FIG. 4 is a diagram showing an example of implementation of the present invention.
FIG. 5 is a diagram showing an example of implementation of the present invention.
FIG. 6 is a diagram showing an example of implementation of the present invention.
FIG. 7 is a diagram showing an example of implementation of the present invention.
FIG. 8 is a diagram showing an example of implementation of the present invention.
FIG. 9 is a diagram showing an example of implementation of the present invention.
FIG. 10 is a diagram showing an example of implementation of the present invention.
FIG. 11 illustrates an example of an electric appliance.
FIG. 12 is a diagram showing an example of an electric appliance.
FIG. 13 shows an example of an electric appliance.
FIG. 14 is a diagram showing an example of implementation of the present invention.
FIG. 15 is a graph showing characteristics of a TFT of the present invention.

Claims (8)

Forming a first gate electrode on the insulating surface;
Forming a first gate insulating film on the first conductive film;
Forming a first semiconductor film on the first gate insulating film;
Adding a first conductivity type impurity to the channel formation region of the first semiconductor film;
Forming a second semiconductor film on the first semiconductor film;
Forming a third semiconductor film on the second semiconductor film;
Adding a first conductivity type impurity to the channel formation region of the third semiconductor film;
Forming source and drain regions of a conductivity type different from the first conductivity type in the first to third semiconductor films;
Forming a second gate insulating film on the channel formation region of the third semiconductor film ;
A second gate electrode formed on said second gate insulating film,
A method for manufacturing a semiconductor device, wherein an impurity is not added to the second semiconductor film over a channel formation region of the first semiconductor film . In a method for manufacturing a thin film transistor including an n-channel thin film transistor and a p-channel thin film transistor over an insulating surface,
Forming a first gate electrode of each of the n-channel thin film transistor and the p-channel thin film transistor on an insulating surface;
Forming a first gate insulating film on the first gate electrode ;
Forming a first semiconductor film on the first gate insulating film;
In the region for forming the n-channel thin film transistor, a p-type impurity is added to the channel formation region of the first semiconductor film,
In the region for forming the p-channel thin film transistor, an n-type impurity is added to the channel formation region of the first semiconductor film,
Forming a second semiconductor film on the first semiconductor film;
Forming a third semiconductor film on the second semiconductor film;
In the region for forming the n-channel thin film transistor, a p-type impurity is added to the channel formation region of the third semiconductor film,
In the region for forming the p-channel thin film transistor, an n-type impurity is added to the channel formation region of the third semiconductor film,
Forming source and drain regions of the n-channel thin film transistor and p-channel thin film transistor in the first to third semiconductor films, respectively ;
Forming a second gate insulating film on a channel formation region of the third semiconductor film of the n-channel thin film transistor and the p-channel thin film transistor ;
Forming second gate electrodes of the n-channel thin film transistor and the p-channel thin film transistor on the second gate insulating film ,
A method for manufacturing a semiconductor device, wherein an impurity is not added to the second semiconductor film over a channel formation region of the first semiconductor film of the n-channel thin film transistor and the p-channel thin film transistor . In Claim 1 or 2, the 1st semiconductor film is crystallized by heating or laser irradiation,
Crystallizing the second semiconductor film by laser irradiation;
A method for manufacturing a semiconductor device, wherein the third semiconductor film is crystallized by heating or laser irradiation.   4. The method according to claim 1, wherein the impurity is added to the channel formation region of the first semiconductor film by any one of an ion implantation method, an ion doping method, a plasma doping method, and a thermal diffusion method. A method for manufacturing a semiconductor device.   5. The method according to claim 1, wherein the impurity is added to the channel formation region of the third semiconductor film by any one of an ion implantation method, an ion doping method, and a plasma doping method. A method for manufacturing a semiconductor device. In any one of claims 1 to 5, wherein the second gate electrode have a tapered,
The doping process have row and the second gate electrode as a mask, a method for manufacturing a semiconductor device, which comprises forming the source and drain regions. Forming a first gate electrode on the insulating surface;
Forming a first gate insulating film on the first gate electrode ;
Forming a first crystalline silicon film to which an impurity element imparting p-type is added on the first gate insulating film;
The second crystalline silicon film is formed over the first crystalline silicon film,
Forming a third crystalline silicon film to which an impurity element imparting p-type on the second crystalline silicon film is added,
Forming a second gate insulating film on the third crystalline silicon film;
Forming a second gate electrode on the second gate insulating film;
An impurity element imparting n-type conductivity is implanted into the first to third crystalline silicon films to form a source region and a drain region ,
A method for manufacturing a semiconductor device, wherein an impurity is not added to the second crystalline silicon film in a region to which an impurity element imparting p-type conductivity is added in the first crystalline silicon film . Forming a first gate electrode on the insulating surface;
Forming a first gate insulating film on the first gate electrode ;
Forming a first crystalline silicon film to which an impurity element imparting n-type is added on the first gate insulating film;
The second crystalline silicon film is formed over the first crystalline silicon film,
Forming a third crystalline silicon film to which an impurity element imparting n-type on the second crystalline silicon film is added,
Forming a second gate insulating film on the third crystalline silicon film;
Forming a second gate electrode on the second gate insulating film;
An impurity element imparting p-type conductivity is implanted into the first to third crystalline silicon films to form a source region and a drain region ,
A method for manufacturing a semiconductor device, wherein an impurity is not added to the second crystalline silicon film in a region where an impurity element imparting n-type conductivity is added to the first crystalline silicon film .

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